arch/powerpc/kernel/pci_64.c

   1 /*
   2  * Port for PPC64 David Engebretsen, IBM Corp.
   3  * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
   4  *
   5  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
   6  *   Rework, based on alpha PCI code.
   7  *
   8  *      This program is free software; you can redistribute it and/or
   9  *      modify it under the terms of the GNU General Public License
  10  *      as published by the Free Software Foundation; either version
  11  *      2 of the License, or (at your option) any later version.
  12  */
  13
  14 #undef DEBUG
  15
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/string.h>
  19 #include <linux/init.h>
  20 #include <linux/bootmem.h>
  21 #include <linux/mm.h>
  22 #include <linux/list.h>
  23 #include <linux/syscalls.h>
  24 #include <linux/irq.h>
  25 #include <linux/vmalloc.h>
  26
  27 #include <asm/processor.h>
  28 #include <asm/io.h>
  29 #include <asm/prom.h>
  30 #include <asm/pci-bridge.h>
  31 #include <asm/byteorder.h>
  32 #include <asm/machdep.h>
  33 #include <asm/ppc-pci.h>
  34
  35 unsigned long pci_probe_only = 1;
  36
  37 /* pci_io_base -- the base address from which io bars are offsets.
  38  * This is the lowest I/O base address (so bar values are always positive),
  39  * and it *must* be the start of ISA space if an ISA bus exists because
  40  * ISA drivers use hard coded offsets.  If no ISA bus exists nothing
  41  * is mapped on the first 64K of IO space
  42  */
  43 unsigned long pci_io_base = ISA_IO_BASE;
  44 EXPORT_SYMBOL(pci_io_base);
  45
  46 static void fixup_broken_pcnet32(struct pci_dev* dev)
  47 {
  48         if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
  49                 dev->vendor = PCI_VENDOR_ID_AMD;
  50                 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
  51         }
  52 }
  53 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
  54
  55
  56 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
  57 {
  58         const u32 *prop;
  59         int len;
  60
  61         prop = of_get_property(np, name, &len);
  62         if (prop && len >= 4)
  63                 return *prop;
  64         return def;
  65 }
  66
  67 static unsigned int pci_parse_of_flags(u32 addr0, int bridge)
  68 {
  69         unsigned int flags = 0;
  70
  71         if (addr0 & 0x02000000) {
  72                 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
  73                 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
  74                 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
  75                 if (addr0 & 0x40000000)
  76                         flags |= IORESOURCE_PREFETCH
  77                                  | PCI_BASE_ADDRESS_MEM_PREFETCH;
  78                 /* Note: We don't know whether the ROM has been left enabled
  79                  * by the firmware or not. We mark it as disabled (ie, we do
  80                  * not set the IORESOURCE_ROM_ENABLE flag) for now rather than
  81                  * do a config space read, it will be force-enabled if needed
  82                  */
  83                 if (!bridge && (addr0 & 0xff) == 0x30)
  84                         flags |= IORESOURCE_READONLY;
  85         } else if (addr0 & 0x01000000)
  86                 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
  87         if (flags)
  88                 flags |= IORESOURCE_SIZEALIGN;
  89         return flags;
  90 }
  91
  92
  93 static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
  94 {
  95         u64 base, size;
  96         unsigned int flags;
  97         struct resource *res;
  98         const u32 *addrs;
  99         u32 i;
 100         int proplen;
 101
 102         addrs = of_get_property(node, "assigned-addresses", &proplen);
 103         if (!addrs)
 104                 return;
 105         pr_debug("    parse addresses (%d bytes) @ %p\n", proplen, addrs);
 106         for (; proplen >= 20; proplen -= 20, addrs += 5) {
 107                 flags = pci_parse_of_flags(addrs[0], 0);
 108                 if (!flags)
 109                         continue;
 110                 base = of_read_number(&addrs[1], 2);
 111                 size = of_read_number(&addrs[3], 2);
 112                 if (!size)
 113                         continue;
 114                 i = addrs[0] & 0xff;
 115                 pr_debug("  base: %llx, size: %llx, i: %x\n",
 116                          (unsigned long long)base,
 117                          (unsigned long long)size, i);
 118
 119                 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
 120                         res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
 121                 } else if (i == dev->rom_base_reg) {
 122                         res = &dev->resource[PCI_ROM_RESOURCE];
 123                         flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
 124                 } else {
 125                         printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
 126                         continue;
 127                 }
 128                 res->start = base;
 129                 res->end = base + size - 1;
 130                 res->flags = flags;
 131                 res->name = pci_name(dev);
 132         }
 133 }
 134
 135 struct pci_dev *of_create_pci_dev(struct device_node *node,
 136                                  struct pci_bus *bus, int devfn)
 137 {
 138         struct pci_dev *dev;
 139         const char *type;
 140
 141         dev = alloc_pci_dev();
 142         if (!dev)
 143                 return NULL;
 144         type = of_get_property(node, "device_type", NULL);
 145         if (type == NULL)
 146                 type = "";
 147
 148         pr_debug("    create device, devfn: %x, type: %s\n", devfn, type);
 149
 150         dev->bus = bus;
 151         dev->sysdata = node;
 152         dev->dev.parent = bus->bridge;
 153         dev->dev.bus = &pci_bus_type;
 154         dev->devfn = devfn;
 155         dev->multifunction = 0;         /* maybe a lie? */
 156
 157         dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
 158         dev->device = get_int_prop(node, "device-id", 0xffff);
 159         dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
 160         dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
 161
 162         dev->cfg_size = pci_cfg_space_size(dev);
 163
 164         dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
 165                 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
 166         dev->class = get_int_prop(node, "class-code", 0);
 167         dev->revision = get_int_prop(node, "revision-id", 0);
 168
 169         pr_debug("    class: 0x%x\n", dev->class);
 170         pr_debug("    revision: 0x%x\n", dev->revision);
 171
 172         dev->current_state = 4;         /* unknown power state */
 173         dev->error_state = pci_channel_io_normal;
 174         dev->dma_mask = 0xffffffff;
 175
 176         if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
 177                 /* a PCI-PCI bridge */
 178                 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
 179                 dev->rom_base_reg = PCI_ROM_ADDRESS1;
 180         } else if (!strcmp(type, "cardbus")) {
 181                 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
 182         } else {
 183                 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
 184                 dev->rom_base_reg = PCI_ROM_ADDRESS;
 185                 /* Maybe do a default OF mapping here */
 186                 dev->irq = NO_IRQ;
 187         }
 188
 189         pci_parse_of_addrs(node, dev);
 190
 191         pr_debug("    adding to system ...\n");
 192
 193         pci_device_add(dev, bus);
 194
 195         return dev;
 196 }
 197 EXPORT_SYMBOL(of_create_pci_dev);
 198
 199 static void __devinit __of_scan_bus(struct device_node *node,
 200                                     struct pci_bus *bus, int rescan_existing)
 201 {
 202         struct device_node *child;
 203         const u32 *reg;
 204         int reglen, devfn;
 205         struct pci_dev *dev;
 206
 207         pr_debug("of_scan_bus(%s) bus no %d... \n",
 208                  node->full_name, bus->number);
 209
 210         /* Scan direct children */
 211         for_each_child_of_node(node, child) {
 212                 pr_debug("  * %s\n", child->full_name);
 213                 reg = of_get_property(child, "reg", &reglen);
 214                 if (reg == NULL || reglen < 20)
 215                         continue;
 216                 devfn = (reg[0] >> 8) & 0xff;
 217
 218                 /* create a new pci_dev for this device */
 219                 dev = of_create_pci_dev(child, bus, devfn);
 220                 if (!dev)
 221                         continue;
 222                 pr_debug("    dev header type: %x\n", dev->hdr_type);
 223         }
 224
 225         /* Apply all fixups necessary. We don't fixup the bus "self"
 226          * for an existing bridge that is being rescanned
 227          */
 228         if (!rescan_existing)
 229                 pcibios_setup_bus_self(bus);
 230         pcibios_setup_bus_devices(bus);
 231
 232         /* Now scan child busses */
 233         list_for_each_entry(dev, &bus->devices, bus_list) {
 234                 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
 235                     dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) {
 236                         struct device_node *child = pci_device_to_OF_node(dev);
 237                         if (dev)
 238                                 of_scan_pci_bridge(child, dev);
 239                 }
 240         }
 241 }
 242
 243 void __devinit of_scan_bus(struct device_node *node,
 244                            struct pci_bus *bus)
 245 {
 246         __of_scan_bus(node, bus, 0);
 247 }
 248 EXPORT_SYMBOL_GPL(of_scan_bus);
 249
 250 void __devinit of_rescan_bus(struct device_node *node,
 251                              struct pci_bus *bus)
 252 {
 253         __of_scan_bus(node, bus, 1);
 254 }
 255 EXPORT_SYMBOL_GPL(of_rescan_bus);
 256
 257 void __devinit of_scan_pci_bridge(struct device_node *node,
 258                                   struct pci_dev *dev)
 259 {
 260         struct pci_bus *bus;
 261         const u32 *busrange, *ranges;
 262         int len, i, mode;
 263         struct resource *res;
 264         unsigned int flags;
 265         u64 size;
 266
 267         pr_debug("of_scan_pci_bridge(%s)\n", node->full_name);
 268
 269         /* parse bus-range property */
 270         busrange = of_get_property(node, "bus-range", &len);
 271         if (busrange == NULL || len != 8) {
 272                 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
 273                        node->full_name);
 274                 return;
 275         }
 276         ranges = of_get_property(node, "ranges", &len);
 277         if (ranges == NULL) {
 278                 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
 279                        node->full_name);
 280                 return;
 281         }
 282
 283         bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
 284         if (!bus) {
 285                 printk(KERN_ERR "Failed to create pci bus for %s\n",
 286                        node->full_name);
 287                 return;
 288         }
 289
 290         bus->primary = dev->bus->number;
 291         bus->subordinate = busrange[1];
 292         bus->bridge_ctl = 0;
 293         bus->sysdata = node;
 294
 295         /* parse ranges property */
 296         /* PCI #address-cells == 3 and #size-cells == 2 always */
 297         res = &dev->resource[PCI_BRIDGE_RESOURCES];
 298         for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
 299                 res->flags = 0;
 300                 bus->resource[i] = res;
 301                 ++res;
 302         }
 303         i = 1;
 304         for (; len >= 32; len -= 32, ranges += 8) {
 305                 flags = pci_parse_of_flags(ranges[0], 1);
 306                 size = of_read_number(&ranges[6], 2);
 307                 if (flags == 0 || size == 0)
 308                         continue;
 309                 if (flags & IORESOURCE_IO) {
 310                         res = bus->resource[0];
 311                         if (res->flags) {
 312                                 printk(KERN_ERR "PCI: ignoring extra I/O range"
 313                                        " for bridge %s\n", node->full_name);
 314                                 continue;
 315                         }
 316                 } else {
 317                         if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
 318                                 printk(KERN_ERR "PCI: too many memory ranges"
 319                                        " for bridge %s\n", node->full_name);
 320                                 continue;
 321                         }
 322                         res = bus->resource[i];
 323                         ++i;
 324                 }
 325                 res->start = of_read_number(&ranges[1], 2);
 326                 res->end = res->start + size - 1;
 327                 res->flags = flags;
 328         }
 329         sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
 330                 bus->number);
 331         pr_debug("    bus name: %s\n", bus->name);
 332
 333         mode = PCI_PROBE_NORMAL;
 334         if (ppc_md.pci_probe_mode)
 335                 mode = ppc_md.pci_probe_mode(bus);
 336         pr_debug("    probe mode: %d\n", mode);
 337
 338         if (mode == PCI_PROBE_DEVTREE)
 339                 of_scan_bus(node, bus);
 340         else if (mode == PCI_PROBE_NORMAL)
 341                 pci_scan_child_bus(bus);
 342 }
 343 EXPORT_SYMBOL(of_scan_pci_bridge);
 344
 345 void __devinit scan_phb(struct pci_controller *hose)
 346 {
 347         struct pci_bus *bus;
 348         struct device_node *node = hose->dn;
 349         int mode;
 350
 351         pr_debug("PCI: Scanning PHB %s\n",
 352                  node ? node->full_name : "<NO NAME>");
 353
 354         /* Create an empty bus for the toplevel */
 355         bus = pci_create_bus(hose->parent, hose->first_busno, hose->ops, node);
 356         if (bus == NULL) {
 357                 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
 358                        hose->global_number);
 359                 return;
 360         }
 361         bus->secondary = hose->first_busno;
 362         hose->bus = bus;
 363
 364         /* Get some IO space for the new PHB */
 365         pcibios_map_io_space(bus);
 366
 367         /* Wire up PHB bus resources */
 368         pcibios_setup_phb_resources(hose);
 369
 370         /* Get probe mode and perform scan */
 371         mode = PCI_PROBE_NORMAL;
 372         if (node && ppc_md.pci_probe_mode)
 373                 mode = ppc_md.pci_probe_mode(bus);
 374         pr_debug("    probe mode: %d\n", mode);
 375         if (mode == PCI_PROBE_DEVTREE) {
 376                 bus->subordinate = hose->last_busno;
 377                 of_scan_bus(node, bus);
 378         }
 379
 380         if (mode == PCI_PROBE_NORMAL)
 381                 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
 382 }
 383
 384 static int __init pcibios_init(void)
 385 {
 386         struct pci_controller *hose, *tmp;
 387
 388         printk(KERN_INFO "PCI: Probing PCI hardware\n");
 389
 390         /* For now, override phys_mem_access_prot. If we need it,g
 391          * later, we may move that initialization to each ppc_md
 392          */
 393         ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
 394
 395         if (pci_probe_only)
 396                 ppc_pci_flags |= PPC_PCI_PROBE_ONLY;
 397
 398         /* On ppc64, we always enable PCI domains and we keep domain 0
 399          * backward compatible in /proc for video cards
 400          */
 401         ppc_pci_flags |= PPC_PCI_ENABLE_PROC_DOMAINS | PPC_PCI_COMPAT_DOMAIN_0;
 402
 403         /* Scan all of the recorded PCI controllers.  */
 404         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 405                 scan_phb(hose);
 406                 pci_bus_add_devices(hose->bus);
 407         }
 408
 409         /* Call common code to handle resource allocation */
 410         pcibios_resource_survey();
 411
 412         printk(KERN_DEBUG "PCI: Probing PCI hardware done\n");
 413
 414         return 0;
 415 }
 416
 417 subsys_initcall(pcibios_init);
 418
 419 #ifdef CONFIG_HOTPLUG
 420
 421 int pcibios_unmap_io_space(struct pci_bus *bus)
 422 {
 423         struct pci_controller *hose;
 424
 425         WARN_ON(bus == NULL);
 426
 427         /* If this is not a PHB, we only flush the hash table over
 428          * the area mapped by this bridge. We don't play with the PTE
 429          * mappings since we might have to deal with sub-page alignemnts
 430          * so flushing the hash table is the only sane way to make sure
 431          * that no hash entries are covering that removed bridge area
 432          * while still allowing other busses overlapping those pages
 433          */
 434         if (bus->self) {
 435                 struct resource *res = bus->resource[0];
 436
 437                 pr_debug("IO unmapping for PCI-PCI bridge %s\n",
 438                          pci_name(bus->self));
 439
 440                 __flush_hash_table_range(&init_mm, res->start + _IO_BASE,
 441                                          res->end + _IO_BASE + 1);
 442                 return 0;
 443         }
 444
 445         /* Get the host bridge */
 446         hose = pci_bus_to_host(bus);
 447
 448         /* Check if we have IOs allocated */
 449         if (hose->io_base_alloc == 0)
 450                 return 0;
 451
 452         pr_debug("IO unmapping for PHB %s\n", hose->dn->full_name);
 453         pr_debug("  alloc=0x%p\n", hose->io_base_alloc);
 454
 455         /* This is a PHB, we fully unmap the IO area */
 456         vunmap(hose->io_base_alloc);
 457
 458         return 0;
 459 }
 460 EXPORT_SYMBOL_GPL(pcibios_unmap_io_space);
 461
 462 #endif /* CONFIG_HOTPLUG */
 463
 464 int __devinit pcibios_map_io_space(struct pci_bus *bus)
 465 {
 466         struct vm_struct *area;
 467         unsigned long phys_page;
 468         unsigned long size_page;
 469         unsigned long io_virt_offset;
 470         struct pci_controller *hose;
 471
 472         WARN_ON(bus == NULL);
 473
 474         /* If this not a PHB, nothing to do, page tables still exist and
 475          * thus HPTEs will be faulted in when needed
 476          */
 477         if (bus->self) {
 478                 pr_debug("IO mapping for PCI-PCI bridge %s\n",
 479                          pci_name(bus->self));
 480                 pr_debug("  virt=0x%016llx...0x%016llx\n",
 481                          bus->resource[0]->start + _IO_BASE,
 482                          bus->resource[0]->end + _IO_BASE);
 483                 return 0;
 484         }
 485
 486         /* Get the host bridge */
 487         hose = pci_bus_to_host(bus);
 488         phys_page = _ALIGN_DOWN(hose->io_base_phys, PAGE_SIZE);
 489         size_page = _ALIGN_UP(hose->pci_io_size, PAGE_SIZE);
 490
 491         /* Make sure IO area address is clear */
 492         hose->io_base_alloc = NULL;
 493
 494         /* If there's no IO to map on that bus, get away too */
 495         if (hose->pci_io_size == 0 || hose->io_base_phys == 0)
 496                 return 0;
 497
 498         /* Let's allocate some IO space for that guy. We don't pass
 499          * VM_IOREMAP because we don't care about alignment tricks that
 500          * the core does in that case. Maybe we should due to stupid card
 501          * with incomplete address decoding but I'd rather not deal with
 502          * those outside of the reserved 64K legacy region.
 503          */
 504         area = __get_vm_area(size_page, 0, PHB_IO_BASE, PHB_IO_END);
 505         if (area == NULL)
 506                 return -ENOMEM;
 507         hose->io_base_alloc = area->addr;
 508         hose->io_base_virt = (void __iomem *)(area->addr +
 509                                               hose->io_base_phys - phys_page);
 510
 511         pr_debug("IO mapping for PHB %s\n", hose->dn->full_name);
 512         pr_debug("  phys=0x%016llx, virt=0x%p (alloc=0x%p)\n",
 513                  hose->io_base_phys, hose->io_base_virt, hose->io_base_alloc);
 514         pr_debug("  size=0x%016lx (alloc=0x%016lx)\n",
 515                  hose->pci_io_size, size_page);
 516
 517         /* Establish the mapping */
 518         if (__ioremap_at(phys_page, area->addr, size_page,
 519                          _PAGE_NO_CACHE | _PAGE_GUARDED) == NULL)
 520                 return -ENOMEM;
 521
 522         /* Fixup hose IO resource */
 523         io_virt_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
 524         hose->io_resource.start += io_virt_offset;
 525         hose->io_resource.end += io_virt_offset;
 526
 527         pr_debug("  hose->io_resource=0x%016llx...0x%016llx\n",
 528                  hose->io_resource.start, hose->io_resource.end);
 529
 530         return 0;
 531 }
 532 EXPORT_SYMBOL_GPL(pcibios_map_io_space);
 533
 534 #define IOBASE_BRIDGE_NUMBER    0
 535 #define IOBASE_MEMORY           1
 536 #define IOBASE_IO               2
 537 #define IOBASE_ISA_IO           3
 538 #define IOBASE_ISA_MEM          4
 539
 540 long sys_pciconfig_iobase(long which, unsigned long in_bus,
 541                           unsigned long in_devfn)
 542 {
 543         struct pci_controller* hose;
 544         struct list_head *ln;
 545         struct pci_bus *bus = NULL;
 546         struct device_node *hose_node;
 547
 548         /* Argh ! Please forgive me for that hack, but that's the
 549          * simplest way to get existing XFree to not lockup on some
 550          * G5 machines... So when something asks for bus 0 io base
 551          * (bus 0 is HT root), we return the AGP one instead.
 552          */
 553         if (in_bus == 0 && machine_is_compatible("MacRISC4")) {
 554                 struct device_node *agp;
 555
 556                 agp = of_find_compatible_node(NULL, NULL, "u3-agp");
 557                 if (agp)
 558                         in_bus = 0xf0;
 559                 of_node_put(agp);
 560         }
 561
 562         /* That syscall isn't quite compatible with PCI domains, but it's
 563          * used on pre-domains setup. We return the first match
 564          */
 565
 566         for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
 567                 bus = pci_bus_b(ln);
 568                 if (in_bus >= bus->number && in_bus <= bus->subordinate)
 569                         break;
 570                 bus = NULL;
 571         }
 572         if (bus == NULL || bus->sysdata == NULL)
 573                 return -ENODEV;
 574
 575         hose_node = (struct device_node *)bus->sysdata;
 576         hose = PCI_DN(hose_node)->phb;
 577
 578         switch (which) {
 579         case IOBASE_BRIDGE_NUMBER:
 580                 return (long)hose->first_busno;
 581         case IOBASE_MEMORY:
 582                 return (long)hose->pci_mem_offset;
 583         case IOBASE_IO:
 584                 return (long)hose->io_base_phys;
 585         case IOBASE_ISA_IO:
 586                 return (long)isa_io_base;
 587         case IOBASE_ISA_MEM:
 588                 return -EINVAL;
 589         }
 590
 591         return -EOPNOTSUPP;
 592 }
 593
 594 #ifdef CONFIG_NUMA
 595 int pcibus_to_node(struct pci_bus *bus)
 596 {
 597         struct pci_controller *phb = pci_bus_to_host(bus);
 598         return phb->node;
 599 }
 600 EXPORT_SYMBOL(pcibus_to_node);
 601 #endif