arch/powerpc/kernel/perf_event.c

   1 /*
   2  * Performance event support - powerpc architecture code
   3  *
   4  * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/sched.h>
  13 #include <linux/perf_event.h>
  14 #include <linux/percpu.h>
  15 #include <linux/hardirq.h>
  16 #include <asm/reg.h>
  17 #include <asm/pmc.h>
  18 #include <asm/machdep.h>
  19 #include <asm/firmware.h>
  20 #include <asm/ptrace.h>
  21
  22 struct cpu_hw_events {
  23         int n_events;
  24         int n_percpu;
  25         int disabled;
  26         int n_added;
  27         int n_limited;
  28         u8  pmcs_enabled;
  29         struct perf_event *event[MAX_HWEVENTS];
  30         u64 events[MAX_HWEVENTS];
  31         unsigned int flags[MAX_HWEVENTS];
  32         unsigned long mmcr[3];
  33         struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS];
  34         u8  limited_hwidx[MAX_LIMITED_HWCOUNTERS];
  35         u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
  36         unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
  37         unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
  38
  39         unsigned int group_flag;
  40         int n_txn_start;
  41 };
  42 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
  43
  44 struct power_pmu *ppmu;
  45
  46 /*
  47  * Normally, to ignore kernel events we set the FCS (freeze counters
  48  * in supervisor mode) bit in MMCR0, but if the kernel runs with the
  49  * hypervisor bit set in the MSR, or if we are running on a processor
  50  * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
  51  * then we need to use the FCHV bit to ignore kernel events.
  52  */
  53 static unsigned int freeze_events_kernel = MMCR0_FCS;
  54
  55 /*
  56  * 32-bit doesn't have MMCRA but does have an MMCR2,
  57  * and a few other names are different.
  58  */
  59 #ifdef CONFIG_PPC32
  60
  61 #define MMCR0_FCHV              0
  62 #define MMCR0_PMCjCE            MMCR0_PMCnCE
  63
  64 #define SPRN_MMCRA              SPRN_MMCR2
  65 #define MMCRA_SAMPLE_ENABLE     0
  66
  67 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
  68 {
  69         return 0;
  70 }
  71 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { }
  72 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
  73 {
  74         return 0;
  75 }
  76 static inline void perf_read_regs(struct pt_regs *regs) { }
  77 static inline int perf_intr_is_nmi(struct pt_regs *regs)
  78 {
  79         return 0;
  80 }
  81
  82 #endif /* CONFIG_PPC32 */
  83
  84 /*
  85  * Things that are specific to 64-bit implementations.
  86  */
  87 #ifdef CONFIG_PPC64
  88
  89 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
  90 {
  91         unsigned long mmcra = regs->dsisr;
  92
  93         if ((mmcra & MMCRA_SAMPLE_ENABLE) && !(ppmu->flags & PPMU_ALT_SIPR)) {
  94                 unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
  95                 if (slot > 1)
  96                         return 4 * (slot - 1);
  97         }
  98         return 0;
  99 }
 100
 101 /*
 102  * The user wants a data address recorded.
 103  * If we're not doing instruction sampling, give them the SDAR
 104  * (sampled data address).  If we are doing instruction sampling, then
 105  * only give them the SDAR if it corresponds to the instruction
 106  * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC
 107  * bit in MMCRA.
 108  */
 109 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp)
 110 {
 111         unsigned long mmcra = regs->dsisr;
 112         unsigned long sdsync = (ppmu->flags & PPMU_ALT_SIPR) ?
 113                 POWER6_MMCRA_SDSYNC : MMCRA_SDSYNC;
 114
 115         if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync))
 116                 *addrp = mfspr(SPRN_SDAR);
 117 }
 118
 119 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
 120 {
 121         unsigned long mmcra = regs->dsisr;
 122         unsigned long sihv = MMCRA_SIHV;
 123         unsigned long sipr = MMCRA_SIPR;
 124
 125         if (TRAP(regs) != 0xf00)
 126                 return 0;       /* not a PMU interrupt */
 127
 128         if (ppmu->flags & PPMU_ALT_SIPR) {
 129                 sihv = POWER6_MMCRA_SIHV;
 130                 sipr = POWER6_MMCRA_SIPR;
 131         }
 132
 133         /* PR has priority over HV, so order below is important */
 134         if (mmcra & sipr)
 135                 return PERF_RECORD_MISC_USER;
 136         if ((mmcra & sihv) && (freeze_events_kernel != MMCR0_FCHV))
 137                 return PERF_RECORD_MISC_HYPERVISOR;
 138         return PERF_RECORD_MISC_KERNEL;
 139 }
 140
 141 /*
 142  * Overload regs->dsisr to store MMCRA so we only need to read it once
 143  * on each interrupt.
 144  */
 145 static inline void perf_read_regs(struct pt_regs *regs)
 146 {
 147         regs->dsisr = mfspr(SPRN_MMCRA);
 148 }
 149
 150 /*
 151  * If interrupts were soft-disabled when a PMU interrupt occurs, treat
 152  * it as an NMI.
 153  */
 154 static inline int perf_intr_is_nmi(struct pt_regs *regs)
 155 {
 156         return !regs->softe;
 157 }
 158
 159 #endif /* CONFIG_PPC64 */
 160
 161 static void perf_event_interrupt(struct pt_regs *regs);
 162
 163 void perf_event_print_debug(void)
 164 {
 165 }
 166
 167 /*
 168  * Read one performance monitor counter (PMC).
 169  */
 170 static unsigned long read_pmc(int idx)
 171 {
 172         unsigned long val;
 173
 174         switch (idx) {
 175         case 1:
 176                 val = mfspr(SPRN_PMC1);
 177                 break;
 178         case 2:
 179                 val = mfspr(SPRN_PMC2);
 180                 break;
 181         case 3:
 182                 val = mfspr(SPRN_PMC3);
 183                 break;
 184         case 4:
 185                 val = mfspr(SPRN_PMC4);
 186                 break;
 187         case 5:
 188                 val = mfspr(SPRN_PMC5);
 189                 break;
 190         case 6:
 191                 val = mfspr(SPRN_PMC6);
 192                 break;
 193 #ifdef CONFIG_PPC64
 194         case 7:
 195                 val = mfspr(SPRN_PMC7);
 196                 break;
 197         case 8:
 198                 val = mfspr(SPRN_PMC8);
 199                 break;
 200 #endif /* CONFIG_PPC64 */
 201         default:
 202                 printk(KERN_ERR "oops trying to read PMC%d\n", idx);
 203                 val = 0;
 204         }
 205         return val;
 206 }
 207
 208 /*
 209  * Write one PMC.
 210  */
 211 static void write_pmc(int idx, unsigned long val)
 212 {
 213         switch (idx) {
 214         case 1:
 215                 mtspr(SPRN_PMC1, val);
 216                 break;
 217         case 2:
 218                 mtspr(SPRN_PMC2, val);
 219                 break;
 220         case 3:
 221                 mtspr(SPRN_PMC3, val);
 222                 break;
 223         case 4:
 224                 mtspr(SPRN_PMC4, val);
 225                 break;
 226         case 5:
 227                 mtspr(SPRN_PMC5, val);
 228                 break;
 229         case 6:
 230                 mtspr(SPRN_PMC6, val);
 231                 break;
 232 #ifdef CONFIG_PPC64
 233         case 7:
 234                 mtspr(SPRN_PMC7, val);
 235                 break;
 236         case 8:
 237                 mtspr(SPRN_PMC8, val);
 238                 break;
 239 #endif /* CONFIG_PPC64 */
 240         default:
 241                 printk(KERN_ERR "oops trying to write PMC%d\n", idx);
 242         }
 243 }
 244
 245 /*
 246  * Check if a set of events can all go on the PMU at once.
 247  * If they can't, this will look at alternative codes for the events
 248  * and see if any combination of alternative codes is feasible.
 249  * The feasible set is returned in event_id[].
 250  */
 251 static int power_check_constraints(struct cpu_hw_events *cpuhw,
 252                                    u64 event_id[], unsigned int cflags[],
 253                                    int n_ev)
 254 {
 255         unsigned long mask, value, nv;
 256         unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS];
 257         int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS];
 258         int i, j;
 259         unsigned long addf = ppmu->add_fields;
 260         unsigned long tadd = ppmu->test_adder;
 261
 262         if (n_ev > ppmu->n_counter)
 263                 return -1;
 264
 265         /* First see if the events will go on as-is */
 266         for (i = 0; i < n_ev; ++i) {
 267                 if ((cflags[i] & PPMU_LIMITED_PMC_REQD)
 268                     && !ppmu->limited_pmc_event(event_id[i])) {
 269                         ppmu->get_alternatives(event_id[i], cflags[i],
 270                                                cpuhw->alternatives[i]);
 271                         event_id[i] = cpuhw->alternatives[i][0];
 272                 }
 273                 if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0],
 274                                          &cpuhw->avalues[i][0]))
 275                         return -1;
 276         }
 277         value = mask = 0;
 278         for (i = 0; i < n_ev; ++i) {
 279                 nv = (value | cpuhw->avalues[i][0]) +
 280                         (value & cpuhw->avalues[i][0] & addf);
 281                 if ((((nv + tadd) ^ value) & mask) != 0 ||
 282                     (((nv + tadd) ^ cpuhw->avalues[i][0]) &
 283                      cpuhw->amasks[i][0]) != 0)
 284                         break;
 285                 value = nv;
 286                 mask |= cpuhw->amasks[i][0];
 287         }
 288         if (i == n_ev)
 289                 return 0;       /* all OK */
 290
 291         /* doesn't work, gather alternatives... */
 292         if (!ppmu->get_alternatives)
 293                 return -1;
 294         for (i = 0; i < n_ev; ++i) {
 295                 choice[i] = 0;
 296                 n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i],
 297                                                   cpuhw->alternatives[i]);
 298                 for (j = 1; j < n_alt[i]; ++j)
 299                         ppmu->get_constraint(cpuhw->alternatives[i][j],
 300                                              &cpuhw->amasks[i][j],
 301                                              &cpuhw->avalues[i][j]);
 302         }
 303
 304         /* enumerate all possibilities and see if any will work */
 305         i = 0;
 306         j = -1;
 307         value = mask = nv = 0;
 308         while (i < n_ev) {
 309                 if (j >= 0) {
 310                         /* we're backtracking, restore context */
 311                         value = svalues[i];
 312                         mask = smasks[i];
 313                         j = choice[i];
 314                 }
 315                 /*
 316                  * See if any alternative k for event_id i,
 317                  * where k > j, will satisfy the constraints.
 318                  */
 319                 while (++j < n_alt[i]) {
 320                         nv = (value | cpuhw->avalues[i][j]) +
 321                                 (value & cpuhw->avalues[i][j] & addf);
 322                         if ((((nv + tadd) ^ value) & mask) == 0 &&
 323                             (((nv + tadd) ^ cpuhw->avalues[i][j])
 324                              & cpuhw->amasks[i][j]) == 0)
 325                                 break;
 326                 }
 327                 if (j >= n_alt[i]) {
 328                         /*
 329                          * No feasible alternative, backtrack
 330                          * to event_id i-1 and continue enumerating its
 331                          * alternatives from where we got up to.
 332                          */
 333                         if (--i < 0)
 334                                 return -1;
 335                 } else {
 336                         /*
 337                          * Found a feasible alternative for event_id i,
 338                          * remember where we got up to with this event_id,
 339                          * go on to the next event_id, and start with
 340                          * the first alternative for it.
 341                          */
 342                         choice[i] = j;
 343                         svalues[i] = value;
 344                         smasks[i] = mask;
 345                         value = nv;
 346                         mask |= cpuhw->amasks[i][j];
 347                         ++i;
 348                         j = -1;
 349                 }
 350         }
 351
 352         /* OK, we have a feasible combination, tell the caller the solution */
 353         for (i = 0; i < n_ev; ++i)
 354                 event_id[i] = cpuhw->alternatives[i][choice[i]];
 355         return 0;
 356 }
 357
 358 /*
 359  * Check if newly-added events have consistent settings for
 360  * exclude_{user,kernel,hv} with each other and any previously
 361  * added events.
 362  */
 363 static int check_excludes(struct perf_event **ctrs, unsigned int cflags[],
 364                           int n_prev, int n_new)
 365 {
 366         int eu = 0, ek = 0, eh = 0;
 367         int i, n, first;
 368         struct perf_event *event;
 369
 370         n = n_prev + n_new;
 371         if (n <= 1)
 372                 return 0;
 373
 374         first = 1;
 375         for (i = 0; i < n; ++i) {
 376                 if (cflags[i] & PPMU_LIMITED_PMC_OK) {
 377                         cflags[i] &= ~PPMU_LIMITED_PMC_REQD;
 378                         continue;
 379                 }
 380                 event = ctrs[i];
 381                 if (first) {
 382                         eu = event->attr.exclude_user;
 383                         ek = event->attr.exclude_kernel;
 384                         eh = event->attr.exclude_hv;
 385                         first = 0;
 386                 } else if (event->attr.exclude_user != eu ||
 387                            event->attr.exclude_kernel != ek ||
 388                            event->attr.exclude_hv != eh) {
 389                         return -EAGAIN;
 390                 }
 391         }
 392
 393         if (eu || ek || eh)
 394                 for (i = 0; i < n; ++i)
 395                         if (cflags[i] & PPMU_LIMITED_PMC_OK)
 396                                 cflags[i] |= PPMU_LIMITED_PMC_REQD;
 397
 398         return 0;
 399 }
 400
 401 static void power_pmu_read(struct perf_event *event)
 402 {
 403         s64 val, delta, prev;
 404
 405         if (event->hw.state & PERF_HES_STOPPED)
 406                 return;
 407
 408         if (!event->hw.idx)
 409                 return;
 410         /*
 411          * Performance monitor interrupts come even when interrupts
 412          * are soft-disabled, as long as interrupts are hard-enabled.
 413          * Therefore we treat them like NMIs.
 414          */
 415         do {
 416                 prev = local64_read(&event->hw.prev_count);
 417                 barrier();
 418                 val = read_pmc(event->hw.idx);
 419         } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
 420
 421         /* The counters are only 32 bits wide */
 422         delta = (val - prev) & 0xfffffffful;
 423         local64_add(delta, &event->count);
 424         local64_sub(delta, &event->hw.period_left);
 425 }
 426
 427 /*
 428  * On some machines, PMC5 and PMC6 can't be written, don't respect
 429  * the freeze conditions, and don't generate interrupts.  This tells
 430  * us if `event' is using such a PMC.
 431  */
 432 static int is_limited_pmc(int pmcnum)
 433 {
 434         return (ppmu->flags & PPMU_LIMITED_PMC5_6)
 435                 && (pmcnum == 5 || pmcnum == 6);
 436 }
 437
 438 static void freeze_limited_counters(struct cpu_hw_events *cpuhw,
 439                                     unsigned long pmc5, unsigned long pmc6)
 440 {
 441         struct perf_event *event;
 442         u64 val, prev, delta;
 443         int i;
 444
 445         for (i = 0; i < cpuhw->n_limited; ++i) {
 446                 event = cpuhw->limited_counter[i];
 447                 if (!event->hw.idx)
 448                         continue;
 449                 val = (event->hw.idx == 5) ? pmc5 : pmc6;
 450                 prev = local64_read(&event->hw.prev_count);
 451                 event->hw.idx = 0;
 452                 delta = (val - prev) & 0xfffffffful;
 453                 local64_add(delta, &event->count);
 454         }
 455 }
 456
 457 static void thaw_limited_counters(struct cpu_hw_events *cpuhw,
 458                                   unsigned long pmc5, unsigned long pmc6)
 459 {
 460         struct perf_event *event;
 461         u64 val;
 462         int i;
 463
 464         for (i = 0; i < cpuhw->n_limited; ++i) {
 465                 event = cpuhw->limited_counter[i];
 466                 event->hw.idx = cpuhw->limited_hwidx[i];
 467                 val = (event->hw.idx == 5) ? pmc5 : pmc6;
 468                 local64_set(&event->hw.prev_count, val);
 469                 perf_event_update_userpage(event);
 470         }
 471 }
 472
 473 /*
 474  * Since limited events don't respect the freeze conditions, we
 475  * have to read them immediately after freezing or unfreezing the
 476  * other events.  We try to keep the values from the limited
 477  * events as consistent as possible by keeping the delay (in
 478  * cycles and instructions) between freezing/unfreezing and reading
 479  * the limited events as small and consistent as possible.
 480  * Therefore, if any limited events are in use, we read them
 481  * both, and always in the same order, to minimize variability,
 482  * and do it inside the same asm that writes MMCR0.
 483  */
 484 static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0)
 485 {
 486         unsigned long pmc5, pmc6;
 487
 488         if (!cpuhw->n_limited) {
 489                 mtspr(SPRN_MMCR0, mmcr0);
 490                 return;
 491         }
 492
 493         /*
 494          * Write MMCR0, then read PMC5 and PMC6 immediately.
 495          * To ensure we don't get a performance monitor interrupt
 496          * between writing MMCR0 and freezing/thawing the limited
 497          * events, we first write MMCR0 with the event overflow
 498          * interrupt enable bits turned off.
 499          */
 500         asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
 501                      : "=&r" (pmc5), "=&r" (pmc6)
 502                      : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)),
 503                        "i" (SPRN_MMCR0),
 504                        "i" (SPRN_PMC5), "i" (SPRN_PMC6));
 505
 506         if (mmcr0 & MMCR0_FC)
 507                 freeze_limited_counters(cpuhw, pmc5, pmc6);
 508         else
 509                 thaw_limited_counters(cpuhw, pmc5, pmc6);
 510
 511         /*
 512          * Write the full MMCR0 including the event overflow interrupt
 513          * enable bits, if necessary.
 514          */
 515         if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE))
 516                 mtspr(SPRN_MMCR0, mmcr0);
 517 }
 518
 519 /*
 520  * Disable all events to prevent PMU interrupts and to allow
 521  * events to be added or removed.
 522  */
 523 static void power_pmu_disable(struct pmu *pmu)
 524 {
 525         struct cpu_hw_events *cpuhw;
 526         unsigned long flags;
 527
 528         if (!ppmu)
 529                 return;
 530         local_irq_save(flags);
 531         cpuhw = &__get_cpu_var(cpu_hw_events);
 532
 533         if (!cpuhw->disabled) {
 534                 cpuhw->disabled = 1;
 535                 cpuhw->n_added = 0;
 536
 537                 /*
 538                  * Check if we ever enabled the PMU on this cpu.
 539                  */
 540                 if (!cpuhw->pmcs_enabled) {
 541                         ppc_enable_pmcs();
 542                         cpuhw->pmcs_enabled = 1;
 543                 }
 544
 545                 /*
 546                  * Disable instruction sampling if it was enabled
 547                  */
 548                 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
 549                         mtspr(SPRN_MMCRA,
 550                               cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
 551                         mb();
 552                 }
 553
 554                 /*
 555                  * Set the 'freeze counters' bit.
 556                  * The barrier is to make sure the mtspr has been
 557                  * executed and the PMU has frozen the events
 558                  * before we return.
 559                  */
 560                 write_mmcr0(cpuhw, mfspr(SPRN_MMCR0) | MMCR0_FC);
 561                 mb();
 562         }
 563         local_irq_restore(flags);
 564 }
 565
 566 /*
 567  * Re-enable all events if disable == 0.
 568  * If we were previously disabled and events were added, then
 569  * put the new config on the PMU.
 570  */
 571 static void power_pmu_enable(struct pmu *pmu)
 572 {
 573         struct perf_event *event;
 574         struct cpu_hw_events *cpuhw;
 575         unsigned long flags;
 576         long i;
 577         unsigned long val;
 578         s64 left;
 579         unsigned int hwc_index[MAX_HWEVENTS];
 580         int n_lim;
 581         int idx;
 582
 583         if (!ppmu)
 584                 return;
 585         local_irq_save(flags);
 586         cpuhw = &__get_cpu_var(cpu_hw_events);
 587         if (!cpuhw->disabled) {
 588                 local_irq_restore(flags);
 589                 return;
 590         }
 591         cpuhw->disabled = 0;
 592
 593         /*
 594          * If we didn't change anything, or only removed events,
 595          * no need to recalculate MMCR* settings and reset the PMCs.
 596          * Just reenable the PMU with the current MMCR* settings
 597          * (possibly updated for removal of events).
 598          */
 599         if (!cpuhw->n_added) {
 600                 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
 601                 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
 602                 if (cpuhw->n_events == 0)
 603                         ppc_set_pmu_inuse(0);
 604                 goto out_enable;
 605         }
 606
 607         /*
 608          * Compute MMCR* values for the new set of events
 609          */
 610         if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index,
 611                                cpuhw->mmcr)) {
 612                 /* shouldn't ever get here */
 613                 printk(KERN_ERR "oops compute_mmcr failed\n");
 614                 goto out;
 615         }
 616
 617         /*
 618          * Add in MMCR0 freeze bits corresponding to the
 619          * attr.exclude_* bits for the first event.
 620          * We have already checked that all events have the
 621          * same values for these bits as the first event.
 622          */
 623         event = cpuhw->event[0];
 624         if (event->attr.exclude_user)
 625                 cpuhw->mmcr[0] |= MMCR0_FCP;
 626         if (event->attr.exclude_kernel)
 627                 cpuhw->mmcr[0] |= freeze_events_kernel;
 628         if (event->attr.exclude_hv)
 629                 cpuhw->mmcr[0] |= MMCR0_FCHV;
 630
 631         /*
 632          * Write the new configuration to MMCR* with the freeze
 633          * bit set and set the hardware events to their initial values.
 634          * Then unfreeze the events.
 635          */
 636         ppc_set_pmu_inuse(1);
 637         mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
 638         mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
 639         mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
 640                                 | MMCR0_FC);
 641
 642         /*
 643          * Read off any pre-existing events that need to move
 644          * to another PMC.
 645          */
 646         for (i = 0; i < cpuhw->n_events; ++i) {
 647                 event = cpuhw->event[i];
 648                 if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) {
 649                         power_pmu_read(event);
 650                         write_pmc(event->hw.idx, 0);
 651                         event->hw.idx = 0;
 652                 }
 653         }
 654
 655         /*
 656          * Initialize the PMCs for all the new and moved events.
 657          */
 658         cpuhw->n_limited = n_lim = 0;
 659         for (i = 0; i < cpuhw->n_events; ++i) {
 660                 event = cpuhw->event[i];
 661                 if (event->hw.idx)
 662                         continue;
 663                 idx = hwc_index[i] + 1;
 664                 if (is_limited_pmc(idx)) {
 665                         cpuhw->limited_counter[n_lim] = event;
 666                         cpuhw->limited_hwidx[n_lim] = idx;
 667                         ++n_lim;
 668                         continue;
 669                 }
 670                 val = 0;
 671                 if (event->hw.sample_period) {
 672                         left = local64_read(&event->hw.period_left);
 673                         if (left < 0x80000000L)
 674                                 val = 0x80000000L - left;
 675                 }
 676                 local64_set(&event->hw.prev_count, val);
 677                 event->hw.idx = idx;
 678                 if (event->hw.state & PERF_HES_STOPPED)
 679                         val = 0;
 680                 write_pmc(idx, val);
 681                 perf_event_update_userpage(event);
 682         }
 683         cpuhw->n_limited = n_lim;
 684         cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
 685
 686  out_enable:
 687         mb();
 688         write_mmcr0(cpuhw, cpuhw->mmcr[0]);
 689
 690         /*
 691          * Enable instruction sampling if necessary
 692          */
 693         if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
 694                 mb();
 695                 mtspr(SPRN_MMCRA, cpuhw->mmcr[2]);
 696         }
 697
 698  out:
 699         local_irq_restore(flags);
 700 }
 701
 702 static int collect_events(struct perf_event *group, int max_count,
 703                           struct perf_event *ctrs[], u64 *events,
 704                           unsigned int *flags)
 705 {
 706         int n = 0;
 707         struct perf_event *event;
 708
 709         if (!is_software_event(group)) {
 710                 if (n >= max_count)
 711                         return -1;
 712                 ctrs[n] = group;
 713                 flags[n] = group->hw.event_base;
 714                 events[n++] = group->hw.config;
 715         }
 716         list_for_each_entry(event, &group->sibling_list, group_entry) {
 717                 if (!is_software_event(event) &&
 718                     event->state != PERF_EVENT_STATE_OFF) {
 719                         if (n >= max_count)
 720                                 return -1;
 721                         ctrs[n] = event;
 722                         flags[n] = event->hw.event_base;
 723                         events[n++] = event->hw.config;
 724                 }
 725         }
 726         return n;
 727 }
 728
 729 /*
 730  * Add a event to the PMU.
 731  * If all events are not already frozen, then we disable and
 732  * re-enable the PMU in order to get hw_perf_enable to do the
 733  * actual work of reconfiguring the PMU.
 734  */
 735 static int power_pmu_add(struct perf_event *event, int ef_flags)
 736 {
 737         struct cpu_hw_events *cpuhw;
 738         unsigned long flags;
 739         int n0;
 740         int ret = -EAGAIN;
 741
 742         local_irq_save(flags);
 743         perf_pmu_disable(event->pmu);
 744
 745         /*
 746          * Add the event to the list (if there is room)
 747          * and check whether the total set is still feasible.
 748          */
 749         cpuhw = &__get_cpu_var(cpu_hw_events);
 750         n0 = cpuhw->n_events;
 751         if (n0 >= ppmu->n_counter)
 752                 goto out;
 753         cpuhw->event[n0] = event;
 754         cpuhw->events[n0] = event->hw.config;
 755         cpuhw->flags[n0] = event->hw.event_base;
 756
 757         if (!(ef_flags & PERF_EF_START))
 758                 event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
 759
 760         /*
 761          * If group events scheduling transaction was started,
 762          * skip the schedulability test here, it will be peformed
 763          * at commit time(->commit_txn) as a whole
 764          */
 765         if (cpuhw->group_flag & PERF_EVENT_TXN)
 766                 goto nocheck;
 767
 768         if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1))
 769                 goto out;
 770         if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1))
 771                 goto out;
 772         event->hw.config = cpuhw->events[n0];
 773
 774 nocheck:
 775         ++cpuhw->n_events;
 776         ++cpuhw->n_added;
 777
 778         ret = 0;
 779  out:
 780         perf_pmu_enable(event->pmu);
 781         local_irq_restore(flags);
 782         return ret;
 783 }
 784
 785 /*
 786  * Remove a event from the PMU.
 787  */
 788 static void power_pmu_del(struct perf_event *event, int ef_flags)
 789 {
 790         struct cpu_hw_events *cpuhw;
 791         long i;
 792         unsigned long flags;
 793
 794         local_irq_save(flags);
 795         perf_pmu_disable(event->pmu);
 796
 797         power_pmu_read(event);
 798
 799         cpuhw = &__get_cpu_var(cpu_hw_events);
 800         for (i = 0; i < cpuhw->n_events; ++i) {
 801                 if (event == cpuhw->event[i]) {
 802                         while (++i < cpuhw->n_events) {
 803                                 cpuhw->event[i-1] = cpuhw->event[i];
 804                                 cpuhw->events[i-1] = cpuhw->events[i];
 805                                 cpuhw->flags[i-1] = cpuhw->flags[i];
 806                         }
 807                         --cpuhw->n_events;
 808                         ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr);
 809                         if (event->hw.idx) {
 810                                 write_pmc(event->hw.idx, 0);
 811                                 event->hw.idx = 0;
 812                         }
 813                         perf_event_update_userpage(event);
 814                         break;
 815                 }
 816         }
 817         for (i = 0; i < cpuhw->n_limited; ++i)
 818                 if (event == cpuhw->limited_counter[i])
 819                         break;
 820         if (i < cpuhw->n_limited) {
 821                 while (++i < cpuhw->n_limited) {
 822                         cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i];
 823                         cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i];
 824                 }
 825                 --cpuhw->n_limited;
 826         }
 827         if (cpuhw->n_events == 0) {
 828                 /* disable exceptions if no events are running */
 829                 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
 830         }
 831
 832         perf_pmu_enable(event->pmu);
 833         local_irq_restore(flags);
 834 }
 835
 836 /*
 837  * POWER-PMU does not support disabling individual counters, hence
 838  * program their cycle counter to their max value and ignore the interrupts.
 839  */
 840
 841 static void power_pmu_start(struct perf_event *event, int ef_flags)
 842 {
 843         unsigned long flags;
 844         s64 left;
 845
 846         if (!event->hw.idx || !event->hw.sample_period)
 847                 return;
 848
 849         if (!(event->hw.state & PERF_HES_STOPPED))
 850                 return;
 851
 852         if (ef_flags & PERF_EF_RELOAD)
 853                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
 854
 855         local_irq_save(flags);
 856         perf_pmu_disable(event->pmu);
 857
 858         event->hw.state = 0;
 859         left = local64_read(&event->hw.period_left);
 860         write_pmc(event->hw.idx, left);
 861
 862         perf_event_update_userpage(event);
 863         perf_pmu_enable(event->pmu);
 864         local_irq_restore(flags);
 865 }
 866
 867 static void power_pmu_stop(struct perf_event *event, int ef_flags)
 868 {
 869         unsigned long flags;
 870
 871         if (!event->hw.idx || !event->hw.sample_period)
 872                 return;
 873
 874         if (event->hw.state & PERF_HES_STOPPED)
 875                 return;
 876
 877         local_irq_save(flags);
 878         perf_pmu_disable(event->pmu);
 879
 880         power_pmu_read(event);
 881         event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 882         write_pmc(event->hw.idx, 0);
 883
 884         perf_event_update_userpage(event);
 885         perf_pmu_enable(event->pmu);
 886         local_irq_restore(flags);
 887 }
 888
 889 /*
 890  * Start group events scheduling transaction
 891  * Set the flag to make pmu::enable() not perform the
 892  * schedulability test, it will be performed at commit time
 893  */
 894 void power_pmu_start_txn(struct pmu *pmu)
 895 {
 896         struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
 897
 898         perf_pmu_disable(pmu);
 899         cpuhw->group_flag |= PERF_EVENT_TXN;
 900         cpuhw->n_txn_start = cpuhw->n_events;
 901 }
 902
 903 /*
 904  * Stop group events scheduling transaction
 905  * Clear the flag and pmu::enable() will perform the
 906  * schedulability test.
 907  */
 908 void power_pmu_cancel_txn(struct pmu *pmu)
 909 {
 910         struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
 911
 912         cpuhw->group_flag &= ~PERF_EVENT_TXN;
 913         perf_pmu_enable(pmu);
 914 }
 915
 916 /*
 917  * Commit group events scheduling transaction
 918  * Perform the group schedulability test as a whole
 919  * Return 0 if success
 920  */
 921 int power_pmu_commit_txn(struct pmu *pmu)
 922 {
 923         struct cpu_hw_events *cpuhw;
 924         long i, n;
 925
 926         if (!ppmu)
 927                 return -EAGAIN;
 928         cpuhw = &__get_cpu_var(cpu_hw_events);
 929         n = cpuhw->n_events;
 930         if (check_excludes(cpuhw->event, cpuhw->flags, 0, n))
 931                 return -EAGAIN;
 932         i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n);
 933         if (i < 0)
 934                 return -EAGAIN;
 935
 936         for (i = cpuhw->n_txn_start; i < n; ++i)
 937                 cpuhw->event[i]->hw.config = cpuhw->events[i];
 938
 939         cpuhw->group_flag &= ~PERF_EVENT_TXN;
 940         perf_pmu_enable(pmu);
 941         return 0;
 942 }
 943
 944 /*
 945  * Return 1 if we might be able to put event on a limited PMC,
 946  * or 0 if not.
 947  * A event can only go on a limited PMC if it counts something
 948  * that a limited PMC can count, doesn't require interrupts, and
 949  * doesn't exclude any processor mode.
 950  */
 951 static int can_go_on_limited_pmc(struct perf_event *event, u64 ev,
 952                                  unsigned int flags)
 953 {
 954         int n;
 955         u64 alt[MAX_EVENT_ALTERNATIVES];
 956
 957         if (event->attr.exclude_user
 958             || event->attr.exclude_kernel
 959             || event->attr.exclude_hv
 960             || event->attr.sample_period)
 961                 return 0;
 962
 963         if (ppmu->limited_pmc_event(ev))
 964                 return 1;
 965
 966         /*
 967          * The requested event_id isn't on a limited PMC already;
 968          * see if any alternative code goes on a limited PMC.
 969          */
 970         if (!ppmu->get_alternatives)
 971                 return 0;
 972
 973         flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD;
 974         n = ppmu->get_alternatives(ev, flags, alt);
 975
 976         return n > 0;
 977 }
 978
 979 /*
 980  * Find an alternative event_id that goes on a normal PMC, if possible,
 981  * and return the event_id code, or 0 if there is no such alternative.
 982  * (Note: event_id code 0 is "don't count" on all machines.)
 983  */
 984 static u64 normal_pmc_alternative(u64 ev, unsigned long flags)
 985 {
 986         u64 alt[MAX_EVENT_ALTERNATIVES];
 987         int n;
 988
 989         flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD);
 990         n = ppmu->get_alternatives(ev, flags, alt);
 991         if (!n)
 992                 return 0;
 993         return alt[0];
 994 }
 995
 996 /* Number of perf_events counting hardware events */
 997 static atomic_t num_events;
 998 /* Used to avoid races in calling reserve/release_pmc_hardware */
 999 static DEFINE_MUTEX(pmc_reserve_mutex);
1000
1001 /*
1002  * Release the PMU if this is the last perf_event.
1003  */
1004 static void hw_perf_event_destroy(struct perf_event *event)
1005 {
1006         if (!atomic_add_unless(&num_events, -1, 1)) {
1007                 mutex_lock(&pmc_reserve_mutex);
1008                 if (atomic_dec_return(&num_events) == 0)
1009                         release_pmc_hardware();
1010                 mutex_unlock(&pmc_reserve_mutex);
1011         }
1012 }
1013
1014 /*
1015  * Translate a generic cache event_id config to a raw event_id code.
1016  */
1017 static int hw_perf_cache_event(u64 config, u64 *eventp)
1018 {
1019         unsigned long type, op, result;
1020         int ev;
1021
1022         if (!ppmu->cache_events)
1023                 return -EINVAL;
1024
1025         /* unpack config */
1026         type = config & 0xff;
1027         op = (config >> 8) & 0xff;
1028         result = (config >> 16) & 0xff;
1029
1030         if (type >= PERF_COUNT_HW_CACHE_MAX ||
1031             op >= PERF_COUNT_HW_CACHE_OP_MAX ||
1032             result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
1033                 return -EINVAL;
1034
1035         ev = (*ppmu->cache_events)[type][op][result];
1036         if (ev == 0)
1037                 return -EOPNOTSUPP;
1038         if (ev == -1)
1039                 return -EINVAL;
1040         *eventp = ev;
1041         return 0;
1042 }
1043
1044 static int power_pmu_event_init(struct perf_event *event)
1045 {
1046         u64 ev;
1047         unsigned long flags;
1048         struct perf_event *ctrs[MAX_HWEVENTS];
1049         u64 events[MAX_HWEVENTS];
1050         unsigned int cflags[MAX_HWEVENTS];
1051         int n;
1052         int err;
1053         struct cpu_hw_events *cpuhw;
1054
1055         if (!ppmu)
1056                 return -ENOENT;
1057
1058         switch (event->attr.type) {
1059         case PERF_TYPE_HARDWARE:
1060                 ev = event->attr.config;
1061                 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
1062                         return -EOPNOTSUPP;
1063                 ev = ppmu->generic_events[ev];
1064                 break;
1065         case PERF_TYPE_HW_CACHE:
1066                 err = hw_perf_cache_event(event->attr.config, &ev);
1067                 if (err)
1068                         return err;
1069                 break;
1070         case PERF_TYPE_RAW:
1071                 ev = event->attr.config;
1072                 break;
1073         default:
1074                 return -ENOENT;
1075         }
1076
1077         event->hw.config_base = ev;
1078         event->hw.idx = 0;
1079
1080         /*
1081          * If we are not running on a hypervisor, force the
1082          * exclude_hv bit to 0 so that we don't care what
1083          * the user set it to.
1084          */
1085         if (!firmware_has_feature(FW_FEATURE_LPAR))
1086                 event->attr.exclude_hv = 0;
1087
1088         /*
1089          * If this is a per-task event, then we can use
1090          * PM_RUN_* events interchangeably with their non RUN_*
1091          * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
1092          * XXX we should check if the task is an idle task.
1093          */
1094         flags = 0;
1095         if (event->attach_state & PERF_ATTACH_TASK)
1096                 flags |= PPMU_ONLY_COUNT_RUN;
1097
1098         /*
1099          * If this machine has limited events, check whether this
1100          * event_id could go on a limited event.
1101          */
1102         if (ppmu->flags & PPMU_LIMITED_PMC5_6) {
1103                 if (can_go_on_limited_pmc(event, ev, flags)) {
1104                         flags |= PPMU_LIMITED_PMC_OK;
1105                 } else if (ppmu->limited_pmc_event(ev)) {
1106                         /*
1107                          * The requested event_id is on a limited PMC,
1108                          * but we can't use a limited PMC; see if any
1109                          * alternative goes on a normal PMC.
1110                          */
1111                         ev = normal_pmc_alternative(ev, flags);
1112                         if (!ev)
1113                                 return -EINVAL;
1114                 }
1115         }
1116
1117         /*
1118          * If this is in a group, check if it can go on with all the
1119          * other hardware events in the group.  We assume the event
1120          * hasn't been linked into its leader's sibling list at this point.
1121          */
1122         n = 0;
1123         if (event->group_leader != event) {
1124                 n = collect_events(event->group_leader, ppmu->n_counter - 1,
1125                                    ctrs, events, cflags);
1126                 if (n < 0)
1127                         return -EINVAL;
1128         }
1129         events[n] = ev;
1130         ctrs[n] = event;
1131         cflags[n] = flags;
1132         if (check_excludes(ctrs, cflags, n, 1))
1133                 return -EINVAL;
1134
1135         cpuhw = &get_cpu_var(cpu_hw_events);
1136         err = power_check_constraints(cpuhw, events, cflags, n + 1);
1137         put_cpu_var(cpu_hw_events);
1138         if (err)
1139                 return -EINVAL;
1140
1141         event->hw.config = events[n];
1142         event->hw.event_base = cflags[n];
1143         event->hw.last_period = event->hw.sample_period;
1144         local64_set(&event->hw.period_left, event->hw.last_period);
1145
1146         /*
1147          * See if we need to reserve the PMU.
1148          * If no events are currently in use, then we have to take a
1149          * mutex to ensure that we don't race with another task doing
1150          * reserve_pmc_hardware or release_pmc_hardware.
1151          */
1152         err = 0;
1153         if (!atomic_inc_not_zero(&num_events)) {
1154                 mutex_lock(&pmc_reserve_mutex);
1155                 if (atomic_read(&num_events) == 0 &&
1156                     reserve_pmc_hardware(perf_event_interrupt))
1157                         err = -EBUSY;
1158                 else
1159                         atomic_inc(&num_events);
1160                 mutex_unlock(&pmc_reserve_mutex);
1161         }
1162         event->destroy = hw_perf_event_destroy;
1163
1164         return err;
1165 }
1166
1167 struct pmu power_pmu = {
1168         .pmu_enable     = power_pmu_enable,
1169         .pmu_disable    = power_pmu_disable,
1170         .event_init     = power_pmu_event_init,
1171         .add            = power_pmu_add,
1172         .del            = power_pmu_del,
1173         .start          = power_pmu_start,
1174         .stop           = power_pmu_stop,
1175         .read           = power_pmu_read,
1176         .start_txn      = power_pmu_start_txn,
1177         .cancel_txn     = power_pmu_cancel_txn,
1178         .commit_txn     = power_pmu_commit_txn,
1179 };
1180
1181 /*
1182  * A counter has overflowed; update its count and record
1183  * things if requested.  Note that interrupts are hard-disabled
1184  * here so there is no possibility of being interrupted.
1185  */
1186 static void record_and_restart(struct perf_event *event, unsigned long val,
1187                                struct pt_regs *regs, int nmi)
1188 {
1189         u64 period = event->hw.sample_period;
1190         s64 prev, delta, left;
1191         int record = 0;
1192
1193         if (event->hw.state & PERF_HES_STOPPED) {
1194                 write_pmc(event->hw.idx, 0);
1195                 return;
1196         }
1197
1198         /* we don't have to worry about interrupts here */
1199         prev = local64_read(&event->hw.prev_count);
1200         delta = (val - prev) & 0xfffffffful;
1201         local64_add(delta, &event->count);
1202
1203         /*
1204          * See if the total period for this event has expired,
1205          * and update for the next period.
1206          */
1207         val = 0;
1208         left = local64_read(&event->hw.period_left) - delta;
1209         if (period) {
1210                 if (left <= 0) {
1211                         left += period;
1212                         if (left <= 0)
1213                                 left = period;
1214                         record = 1;
1215                         event->hw.last_period = event->hw.sample_period;
1216                 }
1217                 if (left < 0x80000000LL)
1218                         val = 0x80000000LL - left;
1219         }
1220
1221         write_pmc(event->hw.idx, val);
1222         local64_set(&event->hw.prev_count, val);
1223         local64_set(&event->hw.period_left, left);
1224         perf_event_update_userpage(event);
1225
1226         /*
1227          * Finally record data if requested.
1228          */
1229         if (record) {
1230                 struct perf_sample_data data;
1231
1232                 perf_sample_data_init(&data, ~0ULL);
1233                 data.period = event->hw.last_period;
1234
1235                 if (event->attr.sample_type & PERF_SAMPLE_ADDR)
1236                         perf_get_data_addr(regs, &data.addr);
1237
1238                 if (perf_event_overflow(event, nmi, &data, regs))
1239                         power_pmu_stop(event, 0);
1240         }
1241 }
1242
1243 /*
1244  * Called from generic code to get the misc flags (i.e. processor mode)
1245  * for an event_id.
1246  */
1247 unsigned long perf_misc_flags(struct pt_regs *regs)
1248 {
1249         u32 flags = perf_get_misc_flags(regs);
1250
1251         if (flags)
1252                 return flags;
1253         return user_mode(regs) ? PERF_RECORD_MISC_USER :
1254                 PERF_RECORD_MISC_KERNEL;
1255 }
1256
1257 /*
1258  * Called from generic code to get the instruction pointer
1259  * for an event_id.
1260  */
1261 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1262 {
1263         unsigned long ip;
1264
1265         if (TRAP(regs) != 0xf00)
1266                 return regs->nip;       /* not a PMU interrupt */
1267
1268         ip = mfspr(SPRN_SIAR) + perf_ip_adjust(regs);
1269         return ip;
1270 }
1271
1272 /*
1273  * Performance monitor interrupt stuff
1274  */
1275 static void perf_event_interrupt(struct pt_regs *regs)
1276 {
1277         int i;
1278         struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1279         struct perf_event *event;
1280         unsigned long val;
1281         int found = 0;
1282         int nmi;
1283
1284         if (cpuhw->n_limited)
1285                 freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5),
1286                                         mfspr(SPRN_PMC6));
1287
1288         perf_read_regs(regs);
1289
1290         nmi = perf_intr_is_nmi(regs);
1291         if (nmi)
1292                 nmi_enter();
1293         else
1294                 irq_enter();
1295
1296         for (i = 0; i < cpuhw->n_events; ++i) {
1297                 event = cpuhw->event[i];
1298                 if (!event->hw.idx || is_limited_pmc(event->hw.idx))
1299                         continue;
1300                 val = read_pmc(event->hw.idx);
1301                 if ((int)val < 0) {
1302                         /* event has overflowed */
1303                         found = 1;
1304                         record_and_restart(event, val, regs, nmi);
1305                 }
1306         }
1307
1308         /*
1309          * In case we didn't find and reset the event that caused
1310          * the interrupt, scan all events and reset any that are
1311          * negative, to avoid getting continual interrupts.
1312          * Any that we processed in the previous loop will not be negative.
1313          */
1314         if (!found) {
1315                 for (i = 0; i < ppmu->n_counter; ++i) {
1316                         if (is_limited_pmc(i + 1))
1317                                 continue;
1318                         val = read_pmc(i + 1);
1319                         if ((int)val < 0)
1320                                 write_pmc(i + 1, 0);
1321                 }
1322         }
1323
1324         /*
1325          * Reset MMCR0 to its normal value.  This will set PMXE and
1326          * clear FC (freeze counters) and PMAO (perf mon alert occurred)
1327          * and thus allow interrupts to occur again.
1328          * XXX might want to use MSR.PM to keep the events frozen until
1329          * we get back out of this interrupt.
1330          */
1331         write_mmcr0(cpuhw, cpuhw->mmcr[0]);
1332
1333         if (nmi)
1334                 nmi_exit();
1335         else
1336                 irq_exit();
1337 }
1338
1339 static void power_pmu_setup(int cpu)
1340 {
1341         struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
1342
1343         if (!ppmu)
1344                 return;
1345         memset(cpuhw, 0, sizeof(*cpuhw));
1346         cpuhw->mmcr[0] = MMCR0_FC;
1347 }
1348
1349 static int __cpuinit
1350 power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1351 {
1352         unsigned int cpu = (long)hcpu;
1353
1354         switch (action & ~CPU_TASKS_FROZEN) {
1355         case CPU_UP_PREPARE:
1356                 power_pmu_setup(cpu);
1357                 break;
1358
1359         default:
1360                 break;
1361         }
1362
1363         return NOTIFY_OK;
1364 }
1365
1366 int register_power_pmu(struct power_pmu *pmu)
1367 {
1368         if (ppmu)
1369                 return -EBUSY;          /* something's already registered */
1370
1371         ppmu = pmu;
1372         pr_info("%s performance monitor hardware support registered\n",
1373                 pmu->name);
1374
1375 #ifdef MSR_HV
1376         /*
1377          * Use FCHV to ignore kernel events if MSR.HV is set.
1378          */
1379         if (mfmsr() & MSR_HV)
1380                 freeze_events_kernel = MMCR0_FCHV;
1381 #endif /* CONFIG_PPC64 */
1382
1383         perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW);
1384         perf_cpu_notifier(power_pmu_notifier);
1385
1386         return 0;
1387 }