2 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
21 #include <linux/smp.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/slab.h>
26 #include <linux/user.h>
27 #include <linux/elf.h>
28 #include <linux/prctl.h>
29 #include <linux/init_task.h>
30 #include <linux/export.h>
31 #include <linux/kallsyms.h>
32 #include <linux/mqueue.h>
33 #include <linux/hardirq.h>
34 #include <linux/utsname.h>
35 #include <linux/ftrace.h>
36 #include <linux/kernel_stat.h>
37 #include <linux/personality.h>
38 #include <linux/random.h>
39 #include <linux/hw_breakpoint.h>
40 #include <linux/uaccess.h>
41 #include <linux/elf-randomize.h>
43 #include <asm/pgtable.h>
45 #include <asm/processor.h>
48 #include <asm/machdep.h>
50 #include <asm/runlatch.h>
51 #include <asm/syscalls.h>
52 #include <asm/switch_to.h>
54 #include <asm/debug.h>
56 #include <asm/firmware.h>
58 #include <asm/code-patching.h>
60 #include <asm/livepatch.h>
62 #include <linux/kprobes.h>
63 #include <linux/kdebug.h>
65 /* Transactional Memory debug */
67 #define TM_DEBUG(x...) printk(KERN_INFO x)
69 #define TM_DEBUG(x...) do { } while(0)
72 extern unsigned long _get_SP(void);
74 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
75 static void check_if_tm_restore_required(struct task_struct
*tsk
)
78 * If we are saving the current thread's registers, and the
79 * thread is in a transactional state, set the TIF_RESTORE_TM
80 * bit so that we know to restore the registers before
81 * returning to userspace.
83 if (tsk
== current
&& tsk
->thread
.regs
&&
84 MSR_TM_ACTIVE(tsk
->thread
.regs
->msr
) &&
85 !test_thread_flag(TIF_RESTORE_TM
)) {
86 tsk
->thread
.ckpt_regs
.msr
= tsk
->thread
.regs
->msr
;
87 set_thread_flag(TIF_RESTORE_TM
);
91 static inline void check_if_tm_restore_required(struct task_struct
*tsk
) { }
92 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
94 bool strict_msr_control
;
95 EXPORT_SYMBOL(strict_msr_control
);
97 static int __init
enable_strict_msr_control(char *str
)
99 strict_msr_control
= true;
100 pr_info("Enabling strict facility control\n");
104 early_param("ppc_strict_facility_enable", enable_strict_msr_control
);
106 void msr_check_and_set(unsigned long bits
)
108 unsigned long oldmsr
= mfmsr();
109 unsigned long newmsr
;
111 newmsr
= oldmsr
| bits
;
114 if (cpu_has_feature(CPU_FTR_VSX
) && (bits
& MSR_FP
))
118 if (oldmsr
!= newmsr
)
122 void __msr_check_and_clear(unsigned long bits
)
124 unsigned long oldmsr
= mfmsr();
125 unsigned long newmsr
;
127 newmsr
= oldmsr
& ~bits
;
130 if (cpu_has_feature(CPU_FTR_VSX
) && (bits
& MSR_FP
))
134 if (oldmsr
!= newmsr
)
137 EXPORT_SYMBOL(__msr_check_and_clear
);
139 #ifdef CONFIG_PPC_FPU
140 void __giveup_fpu(struct task_struct
*tsk
)
143 tsk
->thread
.regs
->msr
&= ~MSR_FP
;
145 if (cpu_has_feature(CPU_FTR_VSX
))
146 tsk
->thread
.regs
->msr
&= ~MSR_VSX
;
150 void giveup_fpu(struct task_struct
*tsk
)
152 check_if_tm_restore_required(tsk
);
154 msr_check_and_set(MSR_FP
);
156 msr_check_and_clear(MSR_FP
);
158 EXPORT_SYMBOL(giveup_fpu
);
161 * Make sure the floating-point register state in the
162 * the thread_struct is up to date for task tsk.
164 void flush_fp_to_thread(struct task_struct
*tsk
)
166 if (tsk
->thread
.regs
) {
168 * We need to disable preemption here because if we didn't,
169 * another process could get scheduled after the regs->msr
170 * test but before we have finished saving the FP registers
171 * to the thread_struct. That process could take over the
172 * FPU, and then when we get scheduled again we would store
173 * bogus values for the remaining FP registers.
176 if (tsk
->thread
.regs
->msr
& MSR_FP
) {
178 * This should only ever be called for current or
179 * for a stopped child process. Since we save away
180 * the FP register state on context switch,
181 * there is something wrong if a stopped child appears
182 * to still have its FP state in the CPU registers.
184 BUG_ON(tsk
!= current
);
190 EXPORT_SYMBOL_GPL(flush_fp_to_thread
);
192 void enable_kernel_fp(void)
194 WARN_ON(preemptible());
196 msr_check_and_set(MSR_FP
);
198 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_FP
)) {
199 check_if_tm_restore_required(current
);
200 __giveup_fpu(current
);
203 EXPORT_SYMBOL(enable_kernel_fp
);
205 static int restore_fp(struct task_struct
*tsk
) {
206 if (tsk
->thread
.load_fp
) {
207 load_fp_state(¤t
->thread
.fp_state
);
208 current
->thread
.load_fp
++;
214 static int restore_fp(struct task_struct
*tsk
) { return 0; }
215 #endif /* CONFIG_PPC_FPU */
217 #ifdef CONFIG_ALTIVEC
218 #define loadvec(thr) ((thr).load_vec)
220 static void __giveup_altivec(struct task_struct
*tsk
)
223 tsk
->thread
.regs
->msr
&= ~MSR_VEC
;
225 if (cpu_has_feature(CPU_FTR_VSX
))
226 tsk
->thread
.regs
->msr
&= ~MSR_VSX
;
230 void giveup_altivec(struct task_struct
*tsk
)
232 check_if_tm_restore_required(tsk
);
234 msr_check_and_set(MSR_VEC
);
235 __giveup_altivec(tsk
);
236 msr_check_and_clear(MSR_VEC
);
238 EXPORT_SYMBOL(giveup_altivec
);
240 void enable_kernel_altivec(void)
242 WARN_ON(preemptible());
244 msr_check_and_set(MSR_VEC
);
246 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VEC
)) {
247 check_if_tm_restore_required(current
);
248 __giveup_altivec(current
);
251 EXPORT_SYMBOL(enable_kernel_altivec
);
254 * Make sure the VMX/Altivec register state in the
255 * the thread_struct is up to date for task tsk.
257 void flush_altivec_to_thread(struct task_struct
*tsk
)
259 if (tsk
->thread
.regs
) {
261 if (tsk
->thread
.regs
->msr
& MSR_VEC
) {
262 BUG_ON(tsk
!= current
);
268 EXPORT_SYMBOL_GPL(flush_altivec_to_thread
);
270 static int restore_altivec(struct task_struct
*tsk
)
272 if (cpu_has_feature(CPU_FTR_ALTIVEC
) && tsk
->thread
.load_vec
) {
273 load_vr_state(&tsk
->thread
.vr_state
);
274 tsk
->thread
.used_vr
= 1;
275 tsk
->thread
.load_vec
++;
282 #define loadvec(thr) 0
283 static inline int restore_altivec(struct task_struct
*tsk
) { return 0; }
284 #endif /* CONFIG_ALTIVEC */
287 static void __giveup_vsx(struct task_struct
*tsk
)
289 if (tsk
->thread
.regs
->msr
& MSR_FP
)
291 if (tsk
->thread
.regs
->msr
& MSR_VEC
)
292 __giveup_altivec(tsk
);
293 tsk
->thread
.regs
->msr
&= ~MSR_VSX
;
296 static void giveup_vsx(struct task_struct
*tsk
)
298 check_if_tm_restore_required(tsk
);
300 msr_check_and_set(MSR_FP
|MSR_VEC
|MSR_VSX
);
302 msr_check_and_clear(MSR_FP
|MSR_VEC
|MSR_VSX
);
305 static void save_vsx(struct task_struct
*tsk
)
307 if (tsk
->thread
.regs
->msr
& MSR_FP
)
309 if (tsk
->thread
.regs
->msr
& MSR_VEC
)
313 void enable_kernel_vsx(void)
315 WARN_ON(preemptible());
317 msr_check_and_set(MSR_FP
|MSR_VEC
|MSR_VSX
);
319 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VSX
)) {
320 check_if_tm_restore_required(current
);
321 if (current
->thread
.regs
->msr
& MSR_FP
)
322 __giveup_fpu(current
);
323 if (current
->thread
.regs
->msr
& MSR_VEC
)
324 __giveup_altivec(current
);
325 __giveup_vsx(current
);
328 EXPORT_SYMBOL(enable_kernel_vsx
);
330 void flush_vsx_to_thread(struct task_struct
*tsk
)
332 if (tsk
->thread
.regs
) {
334 if (tsk
->thread
.regs
->msr
& MSR_VSX
) {
335 BUG_ON(tsk
!= current
);
341 EXPORT_SYMBOL_GPL(flush_vsx_to_thread
);
343 static int restore_vsx(struct task_struct
*tsk
)
345 if (cpu_has_feature(CPU_FTR_VSX
)) {
346 tsk
->thread
.used_vsr
= 1;
353 static inline int restore_vsx(struct task_struct
*tsk
) { return 0; }
354 static inline void save_vsx(struct task_struct
*tsk
) { }
355 #endif /* CONFIG_VSX */
358 void giveup_spe(struct task_struct
*tsk
)
360 check_if_tm_restore_required(tsk
);
362 msr_check_and_set(MSR_SPE
);
364 msr_check_and_clear(MSR_SPE
);
366 EXPORT_SYMBOL(giveup_spe
);
368 void enable_kernel_spe(void)
370 WARN_ON(preemptible());
372 msr_check_and_set(MSR_SPE
);
374 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_SPE
)) {
375 check_if_tm_restore_required(current
);
376 __giveup_spe(current
);
379 EXPORT_SYMBOL(enable_kernel_spe
);
381 void flush_spe_to_thread(struct task_struct
*tsk
)
383 if (tsk
->thread
.regs
) {
385 if (tsk
->thread
.regs
->msr
& MSR_SPE
) {
386 BUG_ON(tsk
!= current
);
387 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
393 #endif /* CONFIG_SPE */
395 static unsigned long msr_all_available
;
397 static int __init
init_msr_all_available(void)
399 #ifdef CONFIG_PPC_FPU
400 msr_all_available
|= MSR_FP
;
402 #ifdef CONFIG_ALTIVEC
403 if (cpu_has_feature(CPU_FTR_ALTIVEC
))
404 msr_all_available
|= MSR_VEC
;
407 if (cpu_has_feature(CPU_FTR_VSX
))
408 msr_all_available
|= MSR_VSX
;
411 if (cpu_has_feature(CPU_FTR_SPE
))
412 msr_all_available
|= MSR_SPE
;
417 early_initcall(init_msr_all_available
);
419 void giveup_all(struct task_struct
*tsk
)
421 unsigned long usermsr
;
423 if (!tsk
->thread
.regs
)
426 usermsr
= tsk
->thread
.regs
->msr
;
428 if ((usermsr
& msr_all_available
) == 0)
431 msr_check_and_set(msr_all_available
);
433 #ifdef CONFIG_PPC_FPU
434 if (usermsr
& MSR_FP
)
437 #ifdef CONFIG_ALTIVEC
438 if (usermsr
& MSR_VEC
)
439 __giveup_altivec(tsk
);
442 if (usermsr
& MSR_VSX
)
446 if (usermsr
& MSR_SPE
)
450 msr_check_and_clear(msr_all_available
);
452 EXPORT_SYMBOL(giveup_all
);
454 void restore_math(struct pt_regs
*regs
)
458 if (!current
->thread
.load_fp
&& !loadvec(current
->thread
))
462 msr_check_and_set(msr_all_available
);
465 * Only reload if the bit is not set in the user MSR, the bit BEING set
466 * indicates that the registers are hot
468 if ((!(msr
& MSR_FP
)) && restore_fp(current
))
469 msr
|= MSR_FP
| current
->thread
.fpexc_mode
;
471 if ((!(msr
& MSR_VEC
)) && restore_altivec(current
))
474 if ((msr
& (MSR_FP
| MSR_VEC
)) == (MSR_FP
| MSR_VEC
) &&
475 restore_vsx(current
)) {
479 msr_check_and_clear(msr_all_available
);
484 void save_all(struct task_struct
*tsk
)
486 unsigned long usermsr
;
488 if (!tsk
->thread
.regs
)
491 usermsr
= tsk
->thread
.regs
->msr
;
493 if ((usermsr
& msr_all_available
) == 0)
496 msr_check_and_set(msr_all_available
);
499 * Saving the way the register space is in hardware, save_vsx boils
500 * down to a save_fpu() and save_altivec()
502 if (usermsr
& MSR_VSX
) {
505 if (usermsr
& MSR_FP
)
508 if (usermsr
& MSR_VEC
)
512 if (usermsr
& MSR_SPE
)
515 msr_check_and_clear(msr_all_available
);
518 void flush_all_to_thread(struct task_struct
*tsk
)
520 if (tsk
->thread
.regs
) {
522 BUG_ON(tsk
!= current
);
526 if (tsk
->thread
.regs
->msr
& MSR_SPE
)
527 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
533 EXPORT_SYMBOL(flush_all_to_thread
);
535 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
536 void do_send_trap(struct pt_regs
*regs
, unsigned long address
,
537 unsigned long error_code
, int signal_code
, int breakpt
)
541 current
->thread
.trap_nr
= signal_code
;
542 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
543 11, SIGSEGV
) == NOTIFY_STOP
)
546 /* Deliver the signal to userspace */
547 info
.si_signo
= SIGTRAP
;
548 info
.si_errno
= breakpt
; /* breakpoint or watchpoint id */
549 info
.si_code
= signal_code
;
550 info
.si_addr
= (void __user
*)address
;
551 force_sig_info(SIGTRAP
, &info
, current
);
553 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
554 void do_break (struct pt_regs
*regs
, unsigned long address
,
555 unsigned long error_code
)
559 current
->thread
.trap_nr
= TRAP_HWBKPT
;
560 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
561 11, SIGSEGV
) == NOTIFY_STOP
)
564 if (debugger_break_match(regs
))
567 /* Clear the breakpoint */
568 hw_breakpoint_disable();
570 /* Deliver the signal to userspace */
571 info
.si_signo
= SIGTRAP
;
573 info
.si_code
= TRAP_HWBKPT
;
574 info
.si_addr
= (void __user
*)address
;
575 force_sig_info(SIGTRAP
, &info
, current
);
577 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
579 static DEFINE_PER_CPU(struct arch_hw_breakpoint
, current_brk
);
581 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
583 * Set the debug registers back to their default "safe" values.
585 static void set_debug_reg_defaults(struct thread_struct
*thread
)
587 thread
->debug
.iac1
= thread
->debug
.iac2
= 0;
588 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
589 thread
->debug
.iac3
= thread
->debug
.iac4
= 0;
591 thread
->debug
.dac1
= thread
->debug
.dac2
= 0;
592 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
593 thread
->debug
.dvc1
= thread
->debug
.dvc2
= 0;
595 thread
->debug
.dbcr0
= 0;
598 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
600 thread
->debug
.dbcr1
= DBCR1_IAC1US
| DBCR1_IAC2US
|
601 DBCR1_IAC3US
| DBCR1_IAC4US
;
603 * Force Data Address Compare User/Supervisor bits to be User-only
604 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
606 thread
->debug
.dbcr2
= DBCR2_DAC1US
| DBCR2_DAC2US
;
608 thread
->debug
.dbcr1
= 0;
612 static void prime_debug_regs(struct debug_reg
*debug
)
615 * We could have inherited MSR_DE from userspace, since
616 * it doesn't get cleared on exception entry. Make sure
617 * MSR_DE is clear before we enable any debug events.
619 mtmsr(mfmsr() & ~MSR_DE
);
621 mtspr(SPRN_IAC1
, debug
->iac1
);
622 mtspr(SPRN_IAC2
, debug
->iac2
);
623 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
624 mtspr(SPRN_IAC3
, debug
->iac3
);
625 mtspr(SPRN_IAC4
, debug
->iac4
);
627 mtspr(SPRN_DAC1
, debug
->dac1
);
628 mtspr(SPRN_DAC2
, debug
->dac2
);
629 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
630 mtspr(SPRN_DVC1
, debug
->dvc1
);
631 mtspr(SPRN_DVC2
, debug
->dvc2
);
633 mtspr(SPRN_DBCR0
, debug
->dbcr0
);
634 mtspr(SPRN_DBCR1
, debug
->dbcr1
);
636 mtspr(SPRN_DBCR2
, debug
->dbcr2
);
640 * Unless neither the old or new thread are making use of the
641 * debug registers, set the debug registers from the values
642 * stored in the new thread.
644 void switch_booke_debug_regs(struct debug_reg
*new_debug
)
646 if ((current
->thread
.debug
.dbcr0
& DBCR0_IDM
)
647 || (new_debug
->dbcr0
& DBCR0_IDM
))
648 prime_debug_regs(new_debug
);
650 EXPORT_SYMBOL_GPL(switch_booke_debug_regs
);
651 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
652 #ifndef CONFIG_HAVE_HW_BREAKPOINT
653 static void set_debug_reg_defaults(struct thread_struct
*thread
)
655 thread
->hw_brk
.address
= 0;
656 thread
->hw_brk
.type
= 0;
657 set_breakpoint(&thread
->hw_brk
);
659 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
660 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
662 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
663 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
665 mtspr(SPRN_DAC1
, dabr
);
666 #ifdef CONFIG_PPC_47x
671 #elif defined(CONFIG_PPC_BOOK3S)
672 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
674 mtspr(SPRN_DABR
, dabr
);
675 if (cpu_has_feature(CPU_FTR_DABRX
))
676 mtspr(SPRN_DABRX
, dabrx
);
680 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
686 static inline int set_dabr(struct arch_hw_breakpoint
*brk
)
688 unsigned long dabr
, dabrx
;
690 dabr
= brk
->address
| (brk
->type
& HW_BRK_TYPE_DABR
);
691 dabrx
= ((brk
->type
>> 3) & 0x7);
694 return ppc_md
.set_dabr(dabr
, dabrx
);
696 return __set_dabr(dabr
, dabrx
);
699 static inline int set_dawr(struct arch_hw_breakpoint
*brk
)
701 unsigned long dawr
, dawrx
, mrd
;
705 dawrx
= (brk
->type
& (HW_BRK_TYPE_READ
| HW_BRK_TYPE_WRITE
)) \
706 << (63 - 58); //* read/write bits */
707 dawrx
|= ((brk
->type
& (HW_BRK_TYPE_TRANSLATE
)) >> 2) \
708 << (63 - 59); //* translate */
709 dawrx
|= (brk
->type
& (HW_BRK_TYPE_PRIV_ALL
)) \
710 >> 3; //* PRIM bits */
711 /* dawr length is stored in field MDR bits 48:53. Matches range in
712 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
714 brk->len is in bytes.
715 This aligns up to double word size, shifts and does the bias.
717 mrd
= ((brk
->len
+ 7) >> 3) - 1;
718 dawrx
|= (mrd
& 0x3f) << (63 - 53);
721 return ppc_md
.set_dawr(dawr
, dawrx
);
722 mtspr(SPRN_DAWR
, dawr
);
723 mtspr(SPRN_DAWRX
, dawrx
);
727 void __set_breakpoint(struct arch_hw_breakpoint
*brk
)
729 memcpy(this_cpu_ptr(¤t_brk
), brk
, sizeof(*brk
));
731 if (cpu_has_feature(CPU_FTR_DAWR
))
737 void set_breakpoint(struct arch_hw_breakpoint
*brk
)
740 __set_breakpoint(brk
);
745 DEFINE_PER_CPU(struct cpu_usage
, cpu_usage_array
);
748 static inline bool hw_brk_match(struct arch_hw_breakpoint
*a
,
749 struct arch_hw_breakpoint
*b
)
751 if (a
->address
!= b
->address
)
753 if (a
->type
!= b
->type
)
755 if (a
->len
!= b
->len
)
760 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
761 static void tm_reclaim_thread(struct thread_struct
*thr
,
762 struct thread_info
*ti
, uint8_t cause
)
764 unsigned long msr_diff
= 0;
767 * If FP/VSX registers have been already saved to the
768 * thread_struct, move them to the transact_fp array.
769 * We clear the TIF_RESTORE_TM bit since after the reclaim
770 * the thread will no longer be transactional.
772 if (test_ti_thread_flag(ti
, TIF_RESTORE_TM
)) {
773 msr_diff
= thr
->ckpt_regs
.msr
& ~thr
->regs
->msr
;
774 if (msr_diff
& MSR_FP
)
775 memcpy(&thr
->transact_fp
, &thr
->fp_state
,
776 sizeof(struct thread_fp_state
));
777 if (msr_diff
& MSR_VEC
)
778 memcpy(&thr
->transact_vr
, &thr
->vr_state
,
779 sizeof(struct thread_vr_state
));
780 clear_ti_thread_flag(ti
, TIF_RESTORE_TM
);
781 msr_diff
&= MSR_FP
| MSR_VEC
| MSR_VSX
| MSR_FE0
| MSR_FE1
;
785 * Use the current MSR TM suspended bit to track if we have
786 * checkpointed state outstanding.
787 * On signal delivery, we'd normally reclaim the checkpointed
788 * state to obtain stack pointer (see:get_tm_stackpointer()).
789 * This will then directly return to userspace without going
790 * through __switch_to(). However, if the stack frame is bad,
791 * we need to exit this thread which calls __switch_to() which
792 * will again attempt to reclaim the already saved tm state.
793 * Hence we need to check that we've not already reclaimed
795 * We do this using the current MSR, rather tracking it in
796 * some specific thread_struct bit, as it has the additional
797 * benifit of checking for a potential TM bad thing exception.
799 if (!MSR_TM_SUSPENDED(mfmsr()))
802 tm_reclaim(thr
, thr
->regs
->msr
, cause
);
804 /* Having done the reclaim, we now have the checkpointed
805 * FP/VSX values in the registers. These might be valid
806 * even if we have previously called enable_kernel_fp() or
807 * flush_fp_to_thread(), so update thr->regs->msr to
808 * indicate their current validity.
810 thr
->regs
->msr
|= msr_diff
;
813 void tm_reclaim_current(uint8_t cause
)
816 tm_reclaim_thread(¤t
->thread
, current_thread_info(), cause
);
819 static inline void tm_reclaim_task(struct task_struct
*tsk
)
821 /* We have to work out if we're switching from/to a task that's in the
822 * middle of a transaction.
824 * In switching we need to maintain a 2nd register state as
825 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
826 * checkpointed (tbegin) state in ckpt_regs and saves the transactional
827 * (current) FPRs into oldtask->thread.transact_fpr[].
829 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
831 struct thread_struct
*thr
= &tsk
->thread
;
836 if (!MSR_TM_ACTIVE(thr
->regs
->msr
))
837 goto out_and_saveregs
;
839 /* Stash the original thread MSR, as giveup_fpu et al will
840 * modify it. We hold onto it to see whether the task used
841 * FP & vector regs. If the TIF_RESTORE_TM flag is set,
842 * ckpt_regs.msr is already set.
844 if (!test_ti_thread_flag(task_thread_info(tsk
), TIF_RESTORE_TM
))
845 thr
->ckpt_regs
.msr
= thr
->regs
->msr
;
847 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
848 "ccr=%lx, msr=%lx, trap=%lx)\n",
849 tsk
->pid
, thr
->regs
->nip
,
850 thr
->regs
->ccr
, thr
->regs
->msr
,
853 tm_reclaim_thread(thr
, task_thread_info(tsk
), TM_CAUSE_RESCHED
);
855 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
859 /* Always save the regs here, even if a transaction's not active.
860 * This context-switches a thread's TM info SPRs. We do it here to
861 * be consistent with the restore path (in recheckpoint) which
862 * cannot happen later in _switch().
867 extern void __tm_recheckpoint(struct thread_struct
*thread
,
868 unsigned long orig_msr
);
870 void tm_recheckpoint(struct thread_struct
*thread
,
871 unsigned long orig_msr
)
875 /* We really can't be interrupted here as the TEXASR registers can't
876 * change and later in the trecheckpoint code, we have a userspace R1.
877 * So let's hard disable over this region.
879 local_irq_save(flags
);
882 /* The TM SPRs are restored here, so that TEXASR.FS can be set
883 * before the trecheckpoint and no explosion occurs.
885 tm_restore_sprs(thread
);
887 __tm_recheckpoint(thread
, orig_msr
);
889 local_irq_restore(flags
);
892 static inline void tm_recheckpoint_new_task(struct task_struct
*new)
896 if (!cpu_has_feature(CPU_FTR_TM
))
899 /* Recheckpoint the registers of the thread we're about to switch to.
901 * If the task was using FP, we non-lazily reload both the original and
902 * the speculative FP register states. This is because the kernel
903 * doesn't see if/when a TM rollback occurs, so if we take an FP
904 * unavoidable later, we are unable to determine which set of FP regs
905 * need to be restored.
907 if (!new->thread
.regs
)
910 if (!MSR_TM_ACTIVE(new->thread
.regs
->msr
)){
911 tm_restore_sprs(&new->thread
);
914 msr
= new->thread
.ckpt_regs
.msr
;
915 /* Recheckpoint to restore original checkpointed register state. */
916 TM_DEBUG("*** tm_recheckpoint of pid %d "
917 "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
918 new->pid
, new->thread
.regs
->msr
, msr
);
920 /* This loads the checkpointed FP/VEC state, if used */
921 tm_recheckpoint(&new->thread
, msr
);
923 /* This loads the speculative FP/VEC state, if used */
925 do_load_up_transact_fpu(&new->thread
);
926 new->thread
.regs
->msr
|=
927 (MSR_FP
| new->thread
.fpexc_mode
);
929 #ifdef CONFIG_ALTIVEC
931 do_load_up_transact_altivec(&new->thread
);
932 new->thread
.regs
->msr
|= MSR_VEC
;
935 /* We may as well turn on VSX too since all the state is restored now */
937 new->thread
.regs
->msr
|= MSR_VSX
;
939 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
940 "(kernel msr 0x%lx)\n",
944 static inline void __switch_to_tm(struct task_struct
*prev
)
946 if (cpu_has_feature(CPU_FTR_TM
)) {
948 tm_reclaim_task(prev
);
953 * This is called if we are on the way out to userspace and the
954 * TIF_RESTORE_TM flag is set. It checks if we need to reload
955 * FP and/or vector state and does so if necessary.
956 * If userspace is inside a transaction (whether active or
957 * suspended) and FP/VMX/VSX instructions have ever been enabled
958 * inside that transaction, then we have to keep them enabled
959 * and keep the FP/VMX/VSX state loaded while ever the transaction
960 * continues. The reason is that if we didn't, and subsequently
961 * got a FP/VMX/VSX unavailable interrupt inside a transaction,
962 * we don't know whether it's the same transaction, and thus we
963 * don't know which of the checkpointed state and the transactional
966 void restore_tm_state(struct pt_regs
*regs
)
968 unsigned long msr_diff
;
970 clear_thread_flag(TIF_RESTORE_TM
);
971 if (!MSR_TM_ACTIVE(regs
->msr
))
974 msr_diff
= current
->thread
.ckpt_regs
.msr
& ~regs
->msr
;
975 msr_diff
&= MSR_FP
| MSR_VEC
| MSR_VSX
;
979 regs
->msr
|= msr_diff
;
983 #define tm_recheckpoint_new_task(new)
984 #define __switch_to_tm(prev)
985 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
987 static inline void save_sprs(struct thread_struct
*t
)
989 #ifdef CONFIG_ALTIVEC
990 if (cpu_has_feature(CPU_FTR_ALTIVEC
))
991 t
->vrsave
= mfspr(SPRN_VRSAVE
);
993 #ifdef CONFIG_PPC_BOOK3S_64
994 if (cpu_has_feature(CPU_FTR_DSCR
))
995 t
->dscr
= mfspr(SPRN_DSCR
);
997 if (cpu_has_feature(CPU_FTR_ARCH_207S
)) {
998 t
->bescr
= mfspr(SPRN_BESCR
);
999 t
->ebbhr
= mfspr(SPRN_EBBHR
);
1000 t
->ebbrr
= mfspr(SPRN_EBBRR
);
1002 t
->fscr
= mfspr(SPRN_FSCR
);
1005 * Note that the TAR is not available for use in the kernel.
1006 * (To provide this, the TAR should be backed up/restored on
1007 * exception entry/exit instead, and be in pt_regs. FIXME,
1008 * this should be in pt_regs anyway (for debug).)
1010 t
->tar
= mfspr(SPRN_TAR
);
1015 static inline void restore_sprs(struct thread_struct
*old_thread
,
1016 struct thread_struct
*new_thread
)
1018 #ifdef CONFIG_ALTIVEC
1019 if (cpu_has_feature(CPU_FTR_ALTIVEC
) &&
1020 old_thread
->vrsave
!= new_thread
->vrsave
)
1021 mtspr(SPRN_VRSAVE
, new_thread
->vrsave
);
1023 #ifdef CONFIG_PPC_BOOK3S_64
1024 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1025 u64 dscr
= get_paca()->dscr_default
;
1026 u64 fscr
= old_thread
->fscr
& ~FSCR_DSCR
;
1028 if (new_thread
->dscr_inherit
) {
1029 dscr
= new_thread
->dscr
;
1033 if (old_thread
->dscr
!= dscr
)
1034 mtspr(SPRN_DSCR
, dscr
);
1036 if (old_thread
->fscr
!= fscr
)
1037 mtspr(SPRN_FSCR
, fscr
);
1040 if (cpu_has_feature(CPU_FTR_ARCH_207S
)) {
1041 if (old_thread
->bescr
!= new_thread
->bescr
)
1042 mtspr(SPRN_BESCR
, new_thread
->bescr
);
1043 if (old_thread
->ebbhr
!= new_thread
->ebbhr
)
1044 mtspr(SPRN_EBBHR
, new_thread
->ebbhr
);
1045 if (old_thread
->ebbrr
!= new_thread
->ebbrr
)
1046 mtspr(SPRN_EBBRR
, new_thread
->ebbrr
);
1048 if (old_thread
->tar
!= new_thread
->tar
)
1049 mtspr(SPRN_TAR
, new_thread
->tar
);
1054 struct task_struct
*__switch_to(struct task_struct
*prev
,
1055 struct task_struct
*new)
1057 struct thread_struct
*new_thread
, *old_thread
;
1058 struct task_struct
*last
;
1059 #ifdef CONFIG_PPC_BOOK3S_64
1060 struct ppc64_tlb_batch
*batch
;
1063 new_thread
= &new->thread
;
1064 old_thread
= ¤t
->thread
;
1066 WARN_ON(!irqs_disabled());
1070 * Collect processor utilization data per process
1072 if (firmware_has_feature(FW_FEATURE_SPLPAR
)) {
1073 struct cpu_usage
*cu
= this_cpu_ptr(&cpu_usage_array
);
1074 long unsigned start_tb
, current_tb
;
1075 start_tb
= old_thread
->start_tb
;
1076 cu
->current_tb
= current_tb
= mfspr(SPRN_PURR
);
1077 old_thread
->accum_tb
+= (current_tb
- start_tb
);
1078 new_thread
->start_tb
= current_tb
;
1080 #endif /* CONFIG_PPC64 */
1082 #ifdef CONFIG_PPC_STD_MMU_64
1083 batch
= this_cpu_ptr(&ppc64_tlb_batch
);
1084 if (batch
->active
) {
1085 current_thread_info()->local_flags
|= _TLF_LAZY_MMU
;
1087 __flush_tlb_pending(batch
);
1090 #endif /* CONFIG_PPC_STD_MMU_64 */
1092 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1093 switch_booke_debug_regs(&new->thread
.debug
);
1096 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1099 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1100 if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk
), &new->thread
.hw_brk
)))
1101 __set_breakpoint(&new->thread
.hw_brk
);
1102 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1106 * We need to save SPRs before treclaim/trecheckpoint as these will
1107 * change a number of them.
1109 save_sprs(&prev
->thread
);
1111 __switch_to_tm(prev
);
1113 /* Save FPU, Altivec, VSX and SPE state */
1117 * We can't take a PMU exception inside _switch() since there is a
1118 * window where the kernel stack SLB and the kernel stack are out
1119 * of sync. Hard disable here.
1123 tm_recheckpoint_new_task(new);
1126 * Call restore_sprs() before calling _switch(). If we move it after
1127 * _switch() then we miss out on calling it for new tasks. The reason
1128 * for this is we manually create a stack frame for new tasks that
1129 * directly returns through ret_from_fork() or
1130 * ret_from_kernel_thread(). See copy_thread() for details.
1132 restore_sprs(old_thread
, new_thread
);
1134 last
= _switch(old_thread
, new_thread
);
1136 #ifdef CONFIG_PPC_STD_MMU_64
1137 if (current_thread_info()->local_flags
& _TLF_LAZY_MMU
) {
1138 current_thread_info()->local_flags
&= ~_TLF_LAZY_MMU
;
1139 batch
= this_cpu_ptr(&ppc64_tlb_batch
);
1143 if (current_thread_info()->task
->thread
.regs
)
1144 restore_math(current_thread_info()->task
->thread
.regs
);
1145 #endif /* CONFIG_PPC_STD_MMU_64 */
1150 static int instructions_to_print
= 16;
1152 static void show_instructions(struct pt_regs
*regs
)
1155 unsigned long pc
= regs
->nip
- (instructions_to_print
* 3 / 4 *
1158 printk("Instruction dump:");
1160 for (i
= 0; i
< instructions_to_print
; i
++) {
1166 #if !defined(CONFIG_BOOKE)
1167 /* If executing with the IMMU off, adjust pc rather
1168 * than print XXXXXXXX.
1170 if (!(regs
->msr
& MSR_IR
))
1171 pc
= (unsigned long)phys_to_virt(pc
);
1174 if (!__kernel_text_address(pc
) ||
1175 probe_kernel_address((unsigned int __user
*)pc
, instr
)) {
1176 printk(KERN_CONT
"XXXXXXXX ");
1178 if (regs
->nip
== pc
)
1179 printk(KERN_CONT
"<%08x> ", instr
);
1181 printk(KERN_CONT
"%08x ", instr
);
1195 static struct regbit msr_bits
[] = {
1196 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1218 #ifndef CONFIG_BOOKE
1225 static void print_bits(unsigned long val
, struct regbit
*bits
, const char *sep
)
1229 for (; bits
->bit
; ++bits
)
1230 if (val
& bits
->bit
) {
1231 printk("%s%s", s
, bits
->name
);
1236 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1237 static struct regbit msr_tm_bits
[] = {
1244 static void print_tm_bits(unsigned long val
)
1247 * This only prints something if at least one of the TM bit is set.
1248 * Inside the TM[], the output means:
1249 * E: Enabled (bit 32)
1250 * S: Suspended (bit 33)
1251 * T: Transactional (bit 34)
1253 if (val
& (MSR_TM
| MSR_TS_S
| MSR_TS_T
)) {
1255 print_bits(val
, msr_tm_bits
, "");
1260 static void print_tm_bits(unsigned long val
) {}
1263 static void print_msr_bits(unsigned long val
)
1266 print_bits(val
, msr_bits
, ",");
1272 #define REG "%016lx"
1273 #define REGS_PER_LINE 4
1274 #define LAST_VOLATILE 13
1277 #define REGS_PER_LINE 8
1278 #define LAST_VOLATILE 12
1281 void show_regs(struct pt_regs
* regs
)
1285 show_regs_print_info(KERN_DEFAULT
);
1287 printk("NIP: "REG
" LR: "REG
" CTR: "REG
"\n",
1288 regs
->nip
, regs
->link
, regs
->ctr
);
1289 printk("REGS: %p TRAP: %04lx %s (%s)\n",
1290 regs
, regs
->trap
, print_tainted(), init_utsname()->release
);
1291 printk("MSR: "REG
" ", regs
->msr
);
1292 print_msr_bits(regs
->msr
);
1293 printk(" CR: %08lx XER: %08lx\n", regs
->ccr
, regs
->xer
);
1295 if ((regs
->trap
!= 0xc00) && cpu_has_feature(CPU_FTR_CFAR
))
1296 printk("CFAR: "REG
" ", regs
->orig_gpr3
);
1297 if (trap
== 0x200 || trap
== 0x300 || trap
== 0x600)
1298 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1299 printk("DEAR: "REG
" ESR: "REG
" ", regs
->dar
, regs
->dsisr
);
1301 printk("DAR: "REG
" DSISR: %08lx ", regs
->dar
, regs
->dsisr
);
1304 printk("SOFTE: %ld ", regs
->softe
);
1306 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1307 if (MSR_TM_ACTIVE(regs
->msr
))
1308 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch
);
1311 for (i
= 0; i
< 32; i
++) {
1312 if ((i
% REGS_PER_LINE
) == 0)
1313 printk("\nGPR%02d: ", i
);
1314 printk(REG
" ", regs
->gpr
[i
]);
1315 if (i
== LAST_VOLATILE
&& !FULL_REGS(regs
))
1319 #ifdef CONFIG_KALLSYMS
1321 * Lookup NIP late so we have the best change of getting the
1322 * above info out without failing
1324 printk("NIP ["REG
"] %pS\n", regs
->nip
, (void *)regs
->nip
);
1325 printk("LR ["REG
"] %pS\n", regs
->link
, (void *)regs
->link
);
1327 show_stack(current
, (unsigned long *) regs
->gpr
[1]);
1328 if (!user_mode(regs
))
1329 show_instructions(regs
);
1332 void flush_thread(void)
1334 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1335 flush_ptrace_hw_breakpoint(current
);
1336 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1337 set_debug_reg_defaults(¤t
->thread
);
1338 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1342 release_thread(struct task_struct
*t
)
1347 * this gets called so that we can store coprocessor state into memory and
1348 * copy the current task into the new thread.
1350 int arch_dup_task_struct(struct task_struct
*dst
, struct task_struct
*src
)
1352 flush_all_to_thread(src
);
1354 * Flush TM state out so we can copy it. __switch_to_tm() does this
1355 * flush but it removes the checkpointed state from the current CPU and
1356 * transitions the CPU out of TM mode. Hence we need to call
1357 * tm_recheckpoint_new_task() (on the same task) to restore the
1358 * checkpointed state back and the TM mode.
1360 __switch_to_tm(src
);
1361 tm_recheckpoint_new_task(src
);
1365 clear_task_ebb(dst
);
1370 static void setup_ksp_vsid(struct task_struct
*p
, unsigned long sp
)
1372 #ifdef CONFIG_PPC_STD_MMU_64
1373 unsigned long sp_vsid
;
1374 unsigned long llp
= mmu_psize_defs
[mmu_linear_psize
].sllp
;
1376 if (radix_enabled())
1379 if (mmu_has_feature(MMU_FTR_1T_SEGMENT
))
1380 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_1T
)
1381 << SLB_VSID_SHIFT_1T
;
1383 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_256M
)
1385 sp_vsid
|= SLB_VSID_KERNEL
| llp
;
1386 p
->thread
.ksp_vsid
= sp_vsid
;
1395 * Copy architecture-specific thread state
1397 int copy_thread(unsigned long clone_flags
, unsigned long usp
,
1398 unsigned long kthread_arg
, struct task_struct
*p
)
1400 struct pt_regs
*childregs
, *kregs
;
1401 extern void ret_from_fork(void);
1402 extern void ret_from_kernel_thread(void);
1404 unsigned long sp
= (unsigned long)task_stack_page(p
) + THREAD_SIZE
;
1405 struct thread_info
*ti
= task_thread_info(p
);
1407 klp_init_thread_info(ti
);
1409 /* Copy registers */
1410 sp
-= sizeof(struct pt_regs
);
1411 childregs
= (struct pt_regs
*) sp
;
1412 if (unlikely(p
->flags
& PF_KTHREAD
)) {
1414 memset(childregs
, 0, sizeof(struct pt_regs
));
1415 childregs
->gpr
[1] = sp
+ sizeof(struct pt_regs
);
1418 childregs
->gpr
[14] = ppc_function_entry((void *)usp
);
1420 clear_tsk_thread_flag(p
, TIF_32BIT
);
1421 childregs
->softe
= 1;
1423 childregs
->gpr
[15] = kthread_arg
;
1424 p
->thread
.regs
= NULL
; /* no user register state */
1425 ti
->flags
|= _TIF_RESTOREALL
;
1426 f
= ret_from_kernel_thread
;
1429 struct pt_regs
*regs
= current_pt_regs();
1430 CHECK_FULL_REGS(regs
);
1433 childregs
->gpr
[1] = usp
;
1434 p
->thread
.regs
= childregs
;
1435 childregs
->gpr
[3] = 0; /* Result from fork() */
1436 if (clone_flags
& CLONE_SETTLS
) {
1438 if (!is_32bit_task())
1439 childregs
->gpr
[13] = childregs
->gpr
[6];
1442 childregs
->gpr
[2] = childregs
->gpr
[6];
1447 childregs
->msr
&= ~(MSR_FP
|MSR_VEC
|MSR_VSX
);
1448 sp
-= STACK_FRAME_OVERHEAD
;
1451 * The way this works is that at some point in the future
1452 * some task will call _switch to switch to the new task.
1453 * That will pop off the stack frame created below and start
1454 * the new task running at ret_from_fork. The new task will
1455 * do some house keeping and then return from the fork or clone
1456 * system call, using the stack frame created above.
1458 ((unsigned long *)sp
)[0] = 0;
1459 sp
-= sizeof(struct pt_regs
);
1460 kregs
= (struct pt_regs
*) sp
;
1461 sp
-= STACK_FRAME_OVERHEAD
;
1464 p
->thread
.ksp_limit
= (unsigned long)task_stack_page(p
) +
1465 _ALIGN_UP(sizeof(struct thread_info
), 16);
1467 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1468 p
->thread
.ptrace_bps
[0] = NULL
;
1471 p
->thread
.fp_save_area
= NULL
;
1472 #ifdef CONFIG_ALTIVEC
1473 p
->thread
.vr_save_area
= NULL
;
1476 setup_ksp_vsid(p
, sp
);
1479 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1480 p
->thread
.dscr_inherit
= current
->thread
.dscr_inherit
;
1481 p
->thread
.dscr
= mfspr(SPRN_DSCR
);
1483 if (cpu_has_feature(CPU_FTR_HAS_PPR
))
1484 p
->thread
.ppr
= INIT_PPR
;
1486 kregs
->nip
= ppc_function_entry(f
);
1491 * Set up a thread for executing a new program
1493 void start_thread(struct pt_regs
*regs
, unsigned long start
, unsigned long sp
)
1496 unsigned long load_addr
= regs
->gpr
[2]; /* saved by ELF_PLAT_INIT */
1500 * If we exec out of a kernel thread then thread.regs will not be
1503 if (!current
->thread
.regs
) {
1504 struct pt_regs
*regs
= task_stack_page(current
) + THREAD_SIZE
;
1505 current
->thread
.regs
= regs
- 1;
1508 memset(regs
->gpr
, 0, sizeof(regs
->gpr
));
1516 * We have just cleared all the nonvolatile GPRs, so make
1517 * FULL_REGS(regs) return true. This is necessary to allow
1518 * ptrace to examine the thread immediately after exec.
1525 regs
->msr
= MSR_USER
;
1527 if (!is_32bit_task()) {
1528 unsigned long entry
;
1530 if (is_elf2_task()) {
1531 /* Look ma, no function descriptors! */
1536 * The latest iteration of the ABI requires that when
1537 * calling a function (at its global entry point),
1538 * the caller must ensure r12 holds the entry point
1539 * address (so that the function can quickly
1540 * establish addressability).
1542 regs
->gpr
[12] = start
;
1543 /* Make sure that's restored on entry to userspace. */
1544 set_thread_flag(TIF_RESTOREALL
);
1548 /* start is a relocated pointer to the function
1549 * descriptor for the elf _start routine. The first
1550 * entry in the function descriptor is the entry
1551 * address of _start and the second entry is the TOC
1552 * value we need to use.
1554 __get_user(entry
, (unsigned long __user
*)start
);
1555 __get_user(toc
, (unsigned long __user
*)start
+1);
1557 /* Check whether the e_entry function descriptor entries
1558 * need to be relocated before we can use them.
1560 if (load_addr
!= 0) {
1567 regs
->msr
= MSR_USER64
;
1571 regs
->msr
= MSR_USER32
;
1575 current
->thread
.used_vsr
= 0;
1577 memset(¤t
->thread
.fp_state
, 0, sizeof(current
->thread
.fp_state
));
1578 current
->thread
.fp_save_area
= NULL
;
1579 #ifdef CONFIG_ALTIVEC
1580 memset(¤t
->thread
.vr_state
, 0, sizeof(current
->thread
.vr_state
));
1581 current
->thread
.vr_state
.vscr
.u
[3] = 0x00010000; /* Java mode disabled */
1582 current
->thread
.vr_save_area
= NULL
;
1583 current
->thread
.vrsave
= 0;
1584 current
->thread
.used_vr
= 0;
1585 #endif /* CONFIG_ALTIVEC */
1587 memset(current
->thread
.evr
, 0, sizeof(current
->thread
.evr
));
1588 current
->thread
.acc
= 0;
1589 current
->thread
.spefscr
= 0;
1590 current
->thread
.used_spe
= 0;
1591 #endif /* CONFIG_SPE */
1592 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1593 if (cpu_has_feature(CPU_FTR_TM
))
1594 regs
->msr
|= MSR_TM
;
1595 current
->thread
.tm_tfhar
= 0;
1596 current
->thread
.tm_texasr
= 0;
1597 current
->thread
.tm_tfiar
= 0;
1598 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1600 EXPORT_SYMBOL(start_thread
);
1602 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1603 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1605 int set_fpexc_mode(struct task_struct
*tsk
, unsigned int val
)
1607 struct pt_regs
*regs
= tsk
->thread
.regs
;
1609 /* This is a bit hairy. If we are an SPE enabled processor
1610 * (have embedded fp) we store the IEEE exception enable flags in
1611 * fpexc_mode. fpexc_mode is also used for setting FP exception
1612 * mode (asyn, precise, disabled) for 'Classic' FP. */
1613 if (val
& PR_FP_EXC_SW_ENABLE
) {
1615 if (cpu_has_feature(CPU_FTR_SPE
)) {
1617 * When the sticky exception bits are set
1618 * directly by userspace, it must call prctl
1619 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1620 * in the existing prctl settings) or
1621 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1622 * the bits being set). <fenv.h> functions
1623 * saving and restoring the whole
1624 * floating-point environment need to do so
1625 * anyway to restore the prctl settings from
1626 * the saved environment.
1628 tsk
->thread
.spefscr_last
= mfspr(SPRN_SPEFSCR
);
1629 tsk
->thread
.fpexc_mode
= val
&
1630 (PR_FP_EXC_SW_ENABLE
| PR_FP_ALL_EXCEPT
);
1640 /* on a CONFIG_SPE this does not hurt us. The bits that
1641 * __pack_fe01 use do not overlap with bits used for
1642 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1643 * on CONFIG_SPE implementations are reserved so writing to
1644 * them does not change anything */
1645 if (val
> PR_FP_EXC_PRECISE
)
1647 tsk
->thread
.fpexc_mode
= __pack_fe01(val
);
1648 if (regs
!= NULL
&& (regs
->msr
& MSR_FP
) != 0)
1649 regs
->msr
= (regs
->msr
& ~(MSR_FE0
|MSR_FE1
))
1650 | tsk
->thread
.fpexc_mode
;
1654 int get_fpexc_mode(struct task_struct
*tsk
, unsigned long adr
)
1658 if (tsk
->thread
.fpexc_mode
& PR_FP_EXC_SW_ENABLE
)
1660 if (cpu_has_feature(CPU_FTR_SPE
)) {
1662 * When the sticky exception bits are set
1663 * directly by userspace, it must call prctl
1664 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1665 * in the existing prctl settings) or
1666 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1667 * the bits being set). <fenv.h> functions
1668 * saving and restoring the whole
1669 * floating-point environment need to do so
1670 * anyway to restore the prctl settings from
1671 * the saved environment.
1673 tsk
->thread
.spefscr_last
= mfspr(SPRN_SPEFSCR
);
1674 val
= tsk
->thread
.fpexc_mode
;
1681 val
= __unpack_fe01(tsk
->thread
.fpexc_mode
);
1682 return put_user(val
, (unsigned int __user
*) adr
);
1685 int set_endian(struct task_struct
*tsk
, unsigned int val
)
1687 struct pt_regs
*regs
= tsk
->thread
.regs
;
1689 if ((val
== PR_ENDIAN_LITTLE
&& !cpu_has_feature(CPU_FTR_REAL_LE
)) ||
1690 (val
== PR_ENDIAN_PPC_LITTLE
&& !cpu_has_feature(CPU_FTR_PPC_LE
)))
1696 if (val
== PR_ENDIAN_BIG
)
1697 regs
->msr
&= ~MSR_LE
;
1698 else if (val
== PR_ENDIAN_LITTLE
|| val
== PR_ENDIAN_PPC_LITTLE
)
1699 regs
->msr
|= MSR_LE
;
1706 int get_endian(struct task_struct
*tsk
, unsigned long adr
)
1708 struct pt_regs
*regs
= tsk
->thread
.regs
;
1711 if (!cpu_has_feature(CPU_FTR_PPC_LE
) &&
1712 !cpu_has_feature(CPU_FTR_REAL_LE
))
1718 if (regs
->msr
& MSR_LE
) {
1719 if (cpu_has_feature(CPU_FTR_REAL_LE
))
1720 val
= PR_ENDIAN_LITTLE
;
1722 val
= PR_ENDIAN_PPC_LITTLE
;
1724 val
= PR_ENDIAN_BIG
;
1726 return put_user(val
, (unsigned int __user
*)adr
);
1729 int set_unalign_ctl(struct task_struct
*tsk
, unsigned int val
)
1731 tsk
->thread
.align_ctl
= val
;
1735 int get_unalign_ctl(struct task_struct
*tsk
, unsigned long adr
)
1737 return put_user(tsk
->thread
.align_ctl
, (unsigned int __user
*)adr
);
1740 static inline int valid_irq_stack(unsigned long sp
, struct task_struct
*p
,
1741 unsigned long nbytes
)
1743 unsigned long stack_page
;
1744 unsigned long cpu
= task_cpu(p
);
1747 * Avoid crashing if the stack has overflowed and corrupted
1748 * task_cpu(p), which is in the thread_info struct.
1750 if (cpu
< NR_CPUS
&& cpu_possible(cpu
)) {
1751 stack_page
= (unsigned long) hardirq_ctx
[cpu
];
1752 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1753 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1756 stack_page
= (unsigned long) softirq_ctx
[cpu
];
1757 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1758 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1764 int validate_sp(unsigned long sp
, struct task_struct
*p
,
1765 unsigned long nbytes
)
1767 unsigned long stack_page
= (unsigned long)task_stack_page(p
);
1769 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1770 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1773 return valid_irq_stack(sp
, p
, nbytes
);
1776 EXPORT_SYMBOL(validate_sp
);
1778 unsigned long get_wchan(struct task_struct
*p
)
1780 unsigned long ip
, sp
;
1783 if (!p
|| p
== current
|| p
->state
== TASK_RUNNING
)
1787 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
1791 sp
= *(unsigned long *)sp
;
1792 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
1795 ip
= ((unsigned long *)sp
)[STACK_FRAME_LR_SAVE
];
1796 if (!in_sched_functions(ip
))
1799 } while (count
++ < 16);
1803 static int kstack_depth_to_print
= CONFIG_PRINT_STACK_DEPTH
;
1805 void show_stack(struct task_struct
*tsk
, unsigned long *stack
)
1807 unsigned long sp
, ip
, lr
, newsp
;
1810 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1811 int curr_frame
= current
->curr_ret_stack
;
1812 extern void return_to_handler(void);
1813 unsigned long rth
= (unsigned long)return_to_handler
;
1816 sp
= (unsigned long) stack
;
1821 sp
= current_stack_pointer();
1823 sp
= tsk
->thread
.ksp
;
1827 printk("Call Trace:\n");
1829 if (!validate_sp(sp
, tsk
, STACK_FRAME_OVERHEAD
))
1832 stack
= (unsigned long *) sp
;
1834 ip
= stack
[STACK_FRAME_LR_SAVE
];
1835 if (!firstframe
|| ip
!= lr
) {
1836 printk("["REG
"] ["REG
"] %pS", sp
, ip
, (void *)ip
);
1837 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1838 if ((ip
== rth
) && curr_frame
>= 0) {
1840 (void *)current
->ret_stack
[curr_frame
].ret
);
1845 printk(" (unreliable)");
1851 * See if this is an exception frame.
1852 * We look for the "regshere" marker in the current frame.
1854 if (validate_sp(sp
, tsk
, STACK_INT_FRAME_SIZE
)
1855 && stack
[STACK_FRAME_MARKER
] == STACK_FRAME_REGS_MARKER
) {
1856 struct pt_regs
*regs
= (struct pt_regs
*)
1857 (sp
+ STACK_FRAME_OVERHEAD
);
1859 printk("--- interrupt: %lx at %pS\n LR = %pS\n",
1860 regs
->trap
, (void *)regs
->nip
, (void *)lr
);
1865 } while (count
++ < kstack_depth_to_print
);
1869 /* Called with hard IRQs off */
1870 void notrace
__ppc64_runlatch_on(void)
1872 struct thread_info
*ti
= current_thread_info();
1875 ctrl
= mfspr(SPRN_CTRLF
);
1876 ctrl
|= CTRL_RUNLATCH
;
1877 mtspr(SPRN_CTRLT
, ctrl
);
1879 ti
->local_flags
|= _TLF_RUNLATCH
;
1882 /* Called with hard IRQs off */
1883 void notrace
__ppc64_runlatch_off(void)
1885 struct thread_info
*ti
= current_thread_info();
1888 ti
->local_flags
&= ~_TLF_RUNLATCH
;
1890 ctrl
= mfspr(SPRN_CTRLF
);
1891 ctrl
&= ~CTRL_RUNLATCH
;
1892 mtspr(SPRN_CTRLT
, ctrl
);
1894 #endif /* CONFIG_PPC64 */
1896 unsigned long arch_align_stack(unsigned long sp
)
1898 if (!(current
->personality
& ADDR_NO_RANDOMIZE
) && randomize_va_space
)
1899 sp
-= get_random_int() & ~PAGE_MASK
;
1903 static inline unsigned long brk_rnd(void)
1905 unsigned long rnd
= 0;
1907 /* 8MB for 32bit, 1GB for 64bit */
1908 if (is_32bit_task())
1909 rnd
= (get_random_long() % (1UL<<(23-PAGE_SHIFT
)));
1911 rnd
= (get_random_long() % (1UL<<(30-PAGE_SHIFT
)));
1913 return rnd
<< PAGE_SHIFT
;
1916 unsigned long arch_randomize_brk(struct mm_struct
*mm
)
1918 unsigned long base
= mm
->brk
;
1921 #ifdef CONFIG_PPC_STD_MMU_64
1923 * If we are using 1TB segments and we are allowed to randomise
1924 * the heap, we can put it above 1TB so it is backed by a 1TB
1925 * segment. Otherwise the heap will be in the bottom 1TB
1926 * which always uses 256MB segments and this may result in a
1927 * performance penalty. We don't need to worry about radix. For
1928 * radix, mmu_highuser_ssize remains unchanged from 256MB.
1930 if (!is_32bit_task() && (mmu_highuser_ssize
== MMU_SEGSIZE_1T
))
1931 base
= max_t(unsigned long, mm
->brk
, 1UL << SID_SHIFT_1T
);
1934 ret
= PAGE_ALIGN(base
+ brk_rnd());