3 * Common boot and setup code.
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
15 #include <linux/export.h>
16 #include <linux/string.h>
17 #include <linux/sched.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/reboot.h>
21 #include <linux/delay.h>
22 #include <linux/initrd.h>
23 #include <linux/seq_file.h>
24 #include <linux/ioport.h>
25 #include <linux/console.h>
26 #include <linux/utsname.h>
27 #include <linux/tty.h>
28 #include <linux/root_dev.h>
29 #include <linux/notifier.h>
30 #include <linux/cpu.h>
31 #include <linux/unistd.h>
32 #include <linux/serial.h>
33 #include <linux/serial_8250.h>
34 #include <linux/bootmem.h>
35 #include <linux/pci.h>
36 #include <linux/lockdep.h>
37 #include <linux/memblock.h>
38 #include <linux/hugetlb.h>
39 #include <linux/memory.h>
40 #include <linux/nmi.h>
43 #include <asm/kdump.h>
45 #include <asm/processor.h>
46 #include <asm/pgtable.h>
49 #include <asm/machdep.h>
52 #include <asm/cputable.h>
53 #include <asm/sections.h>
54 #include <asm/btext.h>
55 #include <asm/nvram.h>
56 #include <asm/setup.h>
58 #include <asm/iommu.h>
59 #include <asm/serial.h>
60 #include <asm/cache.h>
63 #include <asm/firmware.h>
66 #include <asm/kexec.h>
67 #include <asm/mmu_context.h>
68 #include <asm/code-patching.h>
69 #include <asm/kvm_ppc.h>
70 #include <asm/hugetlb.h>
71 #include <asm/epapr_hcalls.h>
72 #include <asm/livepatch.h>
75 #define DBG(fmt...) udbg_printf(fmt)
80 int spinning_secondaries
;
83 /* Pick defaults since we might want to patch instructions
84 * before we've read this from the device tree.
86 struct ppc64_caches ppc64_caches
= {
92 EXPORT_SYMBOL_GPL(ppc64_caches
);
95 * These are used in binfmt_elf.c to put aux entries on the stack
96 * for each elf executable being started.
102 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
103 static void setup_tlb_core_data(void)
107 BUILD_BUG_ON(offsetof(struct tlb_core_data
, lock
) != 0);
109 for_each_possible_cpu(cpu
) {
110 int first
= cpu_first_thread_sibling(cpu
);
113 * If we boot via kdump on a non-primary thread,
114 * make sure we point at the thread that actually
117 if (cpu_first_thread_sibling(boot_cpuid
) == first
)
120 paca
[cpu
].tcd_ptr
= &paca
[first
].tcd
;
123 * If we have threads, we need either tlbsrx.
124 * or e6500 tablewalk mode, or else TLB handlers
125 * will be racy and could produce duplicate entries.
127 if (smt_enabled_at_boot
>= 2 &&
128 !mmu_has_feature(MMU_FTR_USE_TLBRSRV
) &&
129 book3e_htw_mode
!= PPC_HTW_E6500
) {
130 /* Should we panic instead? */
131 WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n",
137 static void setup_tlb_core_data(void)
144 static char *smt_enabled_cmdline
;
146 /* Look for ibm,smt-enabled OF option */
147 static void check_smt_enabled(void)
149 struct device_node
*dn
;
150 const char *smt_option
;
152 /* Default to enabling all threads */
153 smt_enabled_at_boot
= threads_per_core
;
155 /* Allow the command line to overrule the OF option */
156 if (smt_enabled_cmdline
) {
157 if (!strcmp(smt_enabled_cmdline
, "on"))
158 smt_enabled_at_boot
= threads_per_core
;
159 else if (!strcmp(smt_enabled_cmdline
, "off"))
160 smt_enabled_at_boot
= 0;
165 rc
= kstrtoint(smt_enabled_cmdline
, 10, &smt
);
167 smt_enabled_at_boot
=
168 min(threads_per_core
, smt
);
171 dn
= of_find_node_by_path("/options");
173 smt_option
= of_get_property(dn
, "ibm,smt-enabled",
177 if (!strcmp(smt_option
, "on"))
178 smt_enabled_at_boot
= threads_per_core
;
179 else if (!strcmp(smt_option
, "off"))
180 smt_enabled_at_boot
= 0;
188 /* Look for smt-enabled= cmdline option */
189 static int __init
early_smt_enabled(char *p
)
191 smt_enabled_cmdline
= p
;
194 early_param("smt-enabled", early_smt_enabled
);
197 #define check_smt_enabled()
198 #endif /* CONFIG_SMP */
200 /** Fix up paca fields required for the boot cpu */
201 static void fixup_boot_paca(void)
203 /* The boot cpu is started */
204 get_paca()->cpu_start
= 1;
205 /* Allow percpu accesses to work until we setup percpu data */
206 get_paca()->data_offset
= 0;
209 static void cpu_ready_for_interrupts(void)
211 /* Set IR and DR in PACA MSR */
212 get_paca()->kernel_msr
= MSR_KERNEL
;
215 * Enable AIL if supported, and we are in hypervisor mode. If we are
216 * not in hypervisor mode, we enable relocation-on interrupts later
217 * in pSeries_setup_arch() using the H_SET_MODE hcall.
219 if (cpu_has_feature(CPU_FTR_HVMODE
) &&
220 cpu_has_feature(CPU_FTR_ARCH_207S
)) {
221 unsigned long lpcr
= mfspr(SPRN_LPCR
);
222 mtspr(SPRN_LPCR
, lpcr
| LPCR_AIL_3
);
227 * Early initialization entry point. This is called by head.S
228 * with MMU translation disabled. We rely on the "feature" of
229 * the CPU that ignores the top 2 bits of the address in real
230 * mode so we can access kernel globals normally provided we
231 * only toy with things in the RMO region. From here, we do
232 * some early parsing of the device-tree to setup out MEMBLOCK
233 * data structures, and allocate & initialize the hash table
234 * and segment tables so we can start running with translation
237 * It is this function which will call the probe() callback of
238 * the various platform types and copy the matching one to the
239 * global ppc_md structure. Your platform can eventually do
240 * some very early initializations from the probe() routine, but
241 * this is not recommended, be very careful as, for example, the
242 * device-tree is not accessible via normal means at this point.
245 void __init
early_setup(unsigned long dt_ptr
)
247 static __initdata
struct paca_struct boot_paca
;
249 /* -------- printk is _NOT_ safe to use here ! ------- */
251 /* Identify CPU type */
252 identify_cpu(0, mfspr(SPRN_PVR
));
254 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
255 initialise_paca(&boot_paca
, 0);
256 setup_paca(&boot_paca
);
259 /* -------- printk is now safe to use ------- */
261 /* Enable early debugging if any specified (see udbg.h) */
264 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr
);
267 * Do early initialization using the flattened device
268 * tree, such as retrieving the physical memory map or
269 * calculating/retrieving the hash table size.
271 early_init_devtree(__va(dt_ptr
));
273 epapr_paravirt_early_init();
275 /* Now we know the logical id of our boot cpu, setup the paca. */
276 setup_paca(&paca
[boot_cpuid
]);
279 /* Probe the machine type */
282 setup_kdump_trampoline();
284 DBG("Found, Initializing memory management...\n");
286 /* Initialize the hash table or TLB handling */
290 * At this point, we can let interrupts switch to virtual mode
291 * (the MMU has been setup), so adjust the MSR in the PACA to
292 * have IR and DR set and enable AIL if it exists
294 cpu_ready_for_interrupts();
296 /* Reserve large chunks of memory for use by CMA for KVM */
300 * Reserve any gigantic pages requested on the command line.
301 * memblock needs to have been initialized by the time this is
302 * called since this will reserve memory.
304 reserve_hugetlb_gpages();
306 DBG(" <- early_setup()\n");
308 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
310 * This needs to be done *last* (after the above DBG() even)
312 * Right after we return from this function, we turn on the MMU
313 * which means the real-mode access trick that btext does will
314 * no longer work, it needs to switch to using a real MMU
315 * mapping. This call will ensure that it does
318 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
322 void early_setup_secondary(void)
324 /* Mark interrupts enabled in PACA */
325 get_paca()->soft_enabled
= 0;
327 /* Initialize the hash table or TLB handling */
328 early_init_mmu_secondary();
331 * At this point, we can let interrupts switch to virtual mode
332 * (the MMU has been setup), so adjust the MSR in the PACA to
333 * have IR and DR set.
335 cpu_ready_for_interrupts();
338 #endif /* CONFIG_SMP */
340 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
341 static bool use_spinloop(void)
343 if (!IS_ENABLED(CONFIG_PPC_BOOK3E
))
347 * When book3e boots from kexec, the ePAPR spin table does
350 return of_property_read_bool(of_chosen
, "linux,booted-from-kexec");
353 void smp_release_cpus(void)
361 DBG(" -> smp_release_cpus()\n");
363 /* All secondary cpus are spinning on a common spinloop, release them
364 * all now so they can start to spin on their individual paca
365 * spinloops. For non SMP kernels, the secondary cpus never get out
366 * of the common spinloop.
369 ptr
= (unsigned long *)((unsigned long)&__secondary_hold_spinloop
371 *ptr
= ppc_function_entry(generic_secondary_smp_init
);
373 /* And wait a bit for them to catch up */
374 for (i
= 0; i
< 100000; i
++) {
377 if (spinning_secondaries
== 0)
381 DBG("spinning_secondaries = %d\n", spinning_secondaries
);
383 DBG(" <- smp_release_cpus()\n");
385 #endif /* CONFIG_SMP || CONFIG_KEXEC */
388 * Initialize some remaining members of the ppc64_caches and systemcfg
390 * (at least until we get rid of them completely). This is mostly some
391 * cache informations about the CPU that will be used by cache flush
392 * routines and/or provided to userland
394 static void __init
initialize_cache_info(void)
396 struct device_node
*np
;
397 unsigned long num_cpus
= 0;
399 DBG(" -> initialize_cache_info()\n");
401 for_each_node_by_type(np
, "cpu") {
405 * We're assuming *all* of the CPUs have the same
406 * d-cache and i-cache sizes... -Peter
409 const __be32
*sizep
, *lsizep
;
413 lsize
= cur_cpu_spec
->dcache_bsize
;
414 sizep
= of_get_property(np
, "d-cache-size", NULL
);
416 size
= be32_to_cpu(*sizep
);
417 lsizep
= of_get_property(np
, "d-cache-block-size",
419 /* fallback if block size missing */
421 lsizep
= of_get_property(np
,
425 lsize
= be32_to_cpu(*lsizep
);
426 if (sizep
== NULL
|| lsizep
== NULL
)
427 DBG("Argh, can't find dcache properties ! "
428 "sizep: %p, lsizep: %p\n", sizep
, lsizep
);
430 ppc64_caches
.dsize
= size
;
431 ppc64_caches
.dline_size
= lsize
;
432 ppc64_caches
.log_dline_size
= __ilog2(lsize
);
433 ppc64_caches
.dlines_per_page
= PAGE_SIZE
/ lsize
;
436 lsize
= cur_cpu_spec
->icache_bsize
;
437 sizep
= of_get_property(np
, "i-cache-size", NULL
);
439 size
= be32_to_cpu(*sizep
);
440 lsizep
= of_get_property(np
, "i-cache-block-size",
443 lsizep
= of_get_property(np
,
447 lsize
= be32_to_cpu(*lsizep
);
448 if (sizep
== NULL
|| lsizep
== NULL
)
449 DBG("Argh, can't find icache properties ! "
450 "sizep: %p, lsizep: %p\n", sizep
, lsizep
);
452 ppc64_caches
.isize
= size
;
453 ppc64_caches
.iline_size
= lsize
;
454 ppc64_caches
.log_iline_size
= __ilog2(lsize
);
455 ppc64_caches
.ilines_per_page
= PAGE_SIZE
/ lsize
;
459 DBG(" <- initialize_cache_info()\n");
464 * Do some initial setup of the system. The parameters are those which
465 * were passed in from the bootloader.
467 void __init
setup_system(void)
469 DBG(" -> setup_system()\n");
471 /* Apply the CPUs-specific and firmware specific fixups to kernel
472 * text (nop out sections not relevant to this CPU or this firmware)
474 do_feature_fixups(cur_cpu_spec
->cpu_features
,
475 &__start___ftr_fixup
, &__stop___ftr_fixup
);
476 do_feature_fixups(cur_cpu_spec
->mmu_features
,
477 &__start___mmu_ftr_fixup
, &__stop___mmu_ftr_fixup
);
478 do_feature_fixups(powerpc_firmware_features
,
479 &__start___fw_ftr_fixup
, &__stop___fw_ftr_fixup
);
480 do_lwsync_fixups(cur_cpu_spec
->cpu_features
,
481 &__start___lwsync_fixup
, &__stop___lwsync_fixup
);
485 * Unflatten the device-tree passed by prom_init or kexec
487 unflatten_device_tree();
490 * Fill the ppc64_caches & systemcfg structures with informations
491 * retrieved from the device-tree.
493 initialize_cache_info();
495 #ifdef CONFIG_PPC_RTAS
497 * Initialize RTAS if available
500 #endif /* CONFIG_PPC_RTAS */
503 * Check if we have an initrd provided via the device-tree
508 * Do some platform specific early initializations, that includes
509 * setting up the hash table pointers. It also sets up some interrupt-mapping
510 * related options that will be used by finish_device_tree()
512 if (ppc_md
.init_early
)
516 * We can discover serial ports now since the above did setup the
517 * hash table management for us, thus ioremap works. We do that early
518 * so that further code can be debugged
520 find_legacy_serial_ports();
523 * Register early console
525 register_early_udbg_console();
532 smp_setup_cpu_maps();
534 setup_tlb_core_data();
537 * Freescale Book3e parts spin in a loop provided by firmware,
538 * so smp_release_cpus() does nothing for them
540 #if defined(CONFIG_SMP)
541 /* Release secondary cpus out of their spinloops at 0x60 now that
542 * we can map physical -> logical CPU ids
547 pr_info("Starting Linux %s %s\n", init_utsname()->machine
,
548 init_utsname()->version
);
550 pr_info("-----------------------------------------------------\n");
551 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size
);
552 pr_info("phys_mem_size = 0x%llx\n", memblock_phys_mem_size());
554 if (ppc64_caches
.dline_size
!= 0x80)
555 pr_info("dcache_line_size = 0x%x\n", ppc64_caches
.dline_size
);
556 if (ppc64_caches
.iline_size
!= 0x80)
557 pr_info("icache_line_size = 0x%x\n", ppc64_caches
.iline_size
);
559 pr_info("cpu_features = 0x%016lx\n", cur_cpu_spec
->cpu_features
);
560 pr_info(" possible = 0x%016lx\n", CPU_FTRS_POSSIBLE
);
561 pr_info(" always = 0x%016lx\n", CPU_FTRS_ALWAYS
);
562 pr_info("cpu_user_features = 0x%08x 0x%08x\n", cur_cpu_spec
->cpu_user_features
,
563 cur_cpu_spec
->cpu_user_features2
);
564 pr_info("mmu_features = 0x%08x\n", cur_cpu_spec
->mmu_features
);
565 pr_info("firmware_features = 0x%016lx\n", powerpc_firmware_features
);
567 #ifdef CONFIG_PPC_STD_MMU_64
569 pr_info("htab_address = 0x%p\n", htab_address
);
571 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask
);
574 if (PHYSICAL_START
> 0)
575 pr_info("physical_start = 0x%llx\n",
576 (unsigned long long)PHYSICAL_START
);
577 pr_info("-----------------------------------------------------\n");
579 DBG(" <- setup_system()\n");
582 /* This returns the limit below which memory accesses to the linear
583 * mapping are guarnateed not to cause a TLB or SLB miss. This is
584 * used to allocate interrupt or emergency stacks for which our
585 * exception entry path doesn't deal with being interrupted.
587 static u64
safe_stack_limit(void)
589 #ifdef CONFIG_PPC_BOOK3E
590 /* Freescale BookE bolts the entire linear mapping */
591 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E
))
592 return linear_map_top
;
593 /* Other BookE, we assume the first GB is bolted */
596 /* BookS, the first segment is bolted */
597 if (mmu_has_feature(MMU_FTR_1T_SEGMENT
))
598 return 1UL << SID_SHIFT_1T
;
599 return 1UL << SID_SHIFT
;
603 static void __init
irqstack_early_init(void)
605 u64 limit
= safe_stack_limit();
609 * Interrupt stacks must be in the first segment since we
610 * cannot afford to take SLB misses on them.
612 for_each_possible_cpu(i
) {
613 softirq_ctx
[i
] = (struct thread_info
*)
614 __va(memblock_alloc_base(THREAD_SIZE
,
615 THREAD_SIZE
, limit
));
616 hardirq_ctx
[i
] = (struct thread_info
*)
617 __va(memblock_alloc_base(THREAD_SIZE
,
618 THREAD_SIZE
, limit
));
622 #ifdef CONFIG_PPC_BOOK3E
623 static void __init
exc_lvl_early_init(void)
628 for_each_possible_cpu(i
) {
629 sp
= memblock_alloc(THREAD_SIZE
, THREAD_SIZE
);
630 critirq_ctx
[i
] = (struct thread_info
*)__va(sp
);
631 paca
[i
].crit_kstack
= __va(sp
+ THREAD_SIZE
);
633 sp
= memblock_alloc(THREAD_SIZE
, THREAD_SIZE
);
634 dbgirq_ctx
[i
] = (struct thread_info
*)__va(sp
);
635 paca
[i
].dbg_kstack
= __va(sp
+ THREAD_SIZE
);
637 sp
= memblock_alloc(THREAD_SIZE
, THREAD_SIZE
);
638 mcheckirq_ctx
[i
] = (struct thread_info
*)__va(sp
);
639 paca
[i
].mc_kstack
= __va(sp
+ THREAD_SIZE
);
642 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC
))
643 patch_exception(0x040, exc_debug_debug_book3e
);
646 #define exc_lvl_early_init()
650 * Stack space used when we detect a bad kernel stack pointer, and
651 * early in SMP boots before relocation is enabled. Exclusive emergency
652 * stack for machine checks.
654 static void __init
emergency_stack_init(void)
660 * Emergency stacks must be under 256MB, we cannot afford to take
661 * SLB misses on them. The ABI also requires them to be 128-byte
664 * Since we use these as temporary stacks during secondary CPU
665 * bringup, we need to get at them in real mode. This means they
666 * must also be within the RMO region.
668 limit
= min(safe_stack_limit(), ppc64_rma_size
);
670 for_each_possible_cpu(i
) {
671 struct thread_info
*ti
;
672 ti
= __va(memblock_alloc_base(THREAD_SIZE
, THREAD_SIZE
, limit
));
673 klp_init_thread_info(ti
);
674 paca
[i
].emergency_sp
= (void *)ti
+ THREAD_SIZE
;
676 #ifdef CONFIG_PPC_BOOK3S_64
677 /* emergency stack for machine check exception handling. */
678 ti
= __va(memblock_alloc_base(THREAD_SIZE
, THREAD_SIZE
, limit
));
679 klp_init_thread_info(ti
);
680 paca
[i
].mc_emergency_sp
= (void *)ti
+ THREAD_SIZE
;
686 * Called into from start_kernel this initializes memblock, which is used
687 * to manage page allocation until mem_init is called.
689 void __init
setup_arch(char **cmdline_p
)
691 *cmdline_p
= boot_command_line
;
694 * Set cache line size based on type of cpu as a default.
695 * Systems with OF can look in the properties on the cpu node(s)
696 * for a possibly more accurate value.
698 dcache_bsize
= ppc64_caches
.dline_size
;
699 icache_bsize
= ppc64_caches
.iline_size
;
704 klp_init_thread_info(&init_thread_info
);
706 init_mm
.start_code
= (unsigned long)_stext
;
707 init_mm
.end_code
= (unsigned long) _etext
;
708 init_mm
.end_data
= (unsigned long) _edata
;
709 init_mm
.brk
= klimit
;
710 #ifdef CONFIG_PPC_64K_PAGES
711 init_mm
.context
.pte_frag
= NULL
;
713 #ifdef CONFIG_SPAPR_TCE_IOMMU
714 mm_iommu_init(&init_mm
.context
);
716 irqstack_early_init();
717 exc_lvl_early_init();
718 emergency_stack_init();
722 #ifdef CONFIG_DUMMY_CONSOLE
723 conswitchp
= &dummy_con
;
726 if (ppc_md
.setup_arch
)
731 /* Initialize the MMU context management stuff */
734 /* Interrupt code needs to be 64K-aligned */
735 if ((unsigned long)_stext
& 0xffff)
736 panic("Kernelbase not 64K-aligned (0x%lx)!\n",
737 (unsigned long)_stext
);
741 #define PCPU_DYN_SIZE ()
743 static void * __init
pcpu_fc_alloc(unsigned int cpu
, size_t size
, size_t align
)
745 return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu
)), size
, align
,
746 __pa(MAX_DMA_ADDRESS
));
749 static void __init
pcpu_fc_free(void *ptr
, size_t size
)
751 free_bootmem(__pa(ptr
), size
);
754 static int pcpu_cpu_distance(unsigned int from
, unsigned int to
)
756 if (cpu_to_node(from
) == cpu_to_node(to
))
757 return LOCAL_DISTANCE
;
759 return REMOTE_DISTANCE
;
762 unsigned long __per_cpu_offset
[NR_CPUS
] __read_mostly
;
763 EXPORT_SYMBOL(__per_cpu_offset
);
765 void __init
setup_per_cpu_areas(void)
767 const size_t dyn_size
= PERCPU_MODULE_RESERVE
+ PERCPU_DYNAMIC_RESERVE
;
774 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need
775 * to group units. For larger mappings, use 1M atom which
776 * should be large enough to contain a number of units.
778 if (mmu_linear_psize
== MMU_PAGE_4K
)
779 atom_size
= PAGE_SIZE
;
783 rc
= pcpu_embed_first_chunk(0, dyn_size
, atom_size
, pcpu_cpu_distance
,
784 pcpu_fc_alloc
, pcpu_fc_free
);
786 panic("cannot initialize percpu area (err=%d)", rc
);
788 delta
= (unsigned long)pcpu_base_addr
- (unsigned long)__per_cpu_start
;
789 for_each_possible_cpu(cpu
) {
790 __per_cpu_offset
[cpu
] = delta
+ pcpu_unit_offsets
[cpu
];
791 paca
[cpu
].data_offset
= __per_cpu_offset
[cpu
];
796 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
797 unsigned long memory_block_size_bytes(void)
799 if (ppc_md
.memory_block_size
)
800 return ppc_md
.memory_block_size();
802 return MIN_MEMORY_BLOCK_SIZE
;
806 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
807 struct ppc_pci_io ppc_pci_io
;
808 EXPORT_SYMBOL(ppc_pci_io
);
811 #ifdef CONFIG_HARDLOCKUP_DETECTOR
812 u64
hw_nmi_get_sample_period(int watchdog_thresh
)
814 return ppc_proc_freq
* watchdog_thresh
;
818 * The hardlockup detector breaks PMU event based branches and is likely
819 * to get false positives in KVM guests, so disable it by default.
821 static int __init
disable_hardlockup_detector(void)
823 hardlockup_detector_disable();
827 early_initcall(disable_hardlockup_detector
);