projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
powerpc/math-emu: Move the flush FPU state function into do_mathemu
[deliverable/linux.git] / arch / powerpc / kernel / traps.c
1 /*
2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 *
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
12 */
13
14 /*
15 * This file handles the architecture-dependent parts of hardware exceptions
16 */
17
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
21 #include <linux/mm.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/user.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/prctl.h>
30 #include <linux/delay.h>
31 #include <linux/kprobes.h>
32 #include <linux/kexec.h>
33 #include <linux/backlight.h>
34 #include <linux/bug.h>
35 #include <linux/kdebug.h>
36 #include <linux/debugfs.h>
37 #include <linux/ratelimit.h>
38 #include <linux/context_tracking.h>
39
40 #include <asm/emulated_ops.h>
41 #include <asm/pgtable.h>
42 #include <asm/uaccess.h>
43 #include <asm/io.h>
44 #include <asm/machdep.h>
45 #include <asm/rtas.h>
46 #include <asm/pmc.h>
47 #ifdef CONFIG_PPC32
48 #include <asm/reg.h>
49 #endif
50 #ifdef CONFIG_PMAC_BACKLIGHT
51 #include <asm/backlight.h>
52 #endif
53 #ifdef CONFIG_PPC64
54 #include <asm/firmware.h>
55 #include <asm/processor.h>
56 #include <asm/tm.h>
57 #endif
58 #include <asm/kexec.h>
59 #include <asm/ppc-opcode.h>
60 #include <asm/rio.h>
61 #include <asm/fadump.h>
62 #include <asm/switch_to.h>
63 #include <asm/tm.h>
64 #include <asm/debug.h>
65 #include <sysdev/fsl_pci.h>
66
67 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
68 int (*__debugger)(struct pt_regs *regs) __read_mostly;
69 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
70 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
71 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
72 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
73 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
74 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
75
76 EXPORT_SYMBOL(__debugger);
77 EXPORT_SYMBOL(__debugger_ipi);
78 EXPORT_SYMBOL(__debugger_bpt);
79 EXPORT_SYMBOL(__debugger_sstep);
80 EXPORT_SYMBOL(__debugger_iabr_match);
81 EXPORT_SYMBOL(__debugger_break_match);
82 EXPORT_SYMBOL(__debugger_fault_handler);
83 #endif
84
85 /* Transactional Memory trap debug */
86 #ifdef TM_DEBUG_SW
87 #define TM_DEBUG(x...) printk(KERN_INFO x)
88 #else
89 #define TM_DEBUG(x...) do { } while(0)
90 #endif
91
92 /*
93 * Trap & Exception support
94 */
95
96 #ifdef CONFIG_PMAC_BACKLIGHT
97 static void pmac_backlight_unblank(void)
98 {
99 mutex_lock(&pmac_backlight_mutex);
100 if (pmac_backlight) {
101 struct backlight_properties *props;
102
103 props = &pmac_backlight->props;
104 props->brightness = props->max_brightness;
105 props->power = FB_BLANK_UNBLANK;
106 backlight_update_status(pmac_backlight);
107 }
108 mutex_unlock(&pmac_backlight_mutex);
109 }
110 #else
111 static inline void pmac_backlight_unblank(void) { }
112 #endif
113
114 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
115 static int die_owner = -1;
116 static unsigned int die_nest_count;
117 static int die_counter;
118
119 static unsigned __kprobes long oops_begin(struct pt_regs *regs)
120 {
121 int cpu;
122 unsigned long flags;
123
124 if (debugger(regs))
125 return 1;
126
127 oops_enter();
128
129 /* racy, but better than risking deadlock. */
130 raw_local_irq_save(flags);
131 cpu = smp_processor_id();
132 if (!arch_spin_trylock(&die_lock)) {
133 if (cpu == die_owner)
134 /* nested oops. should stop eventually */;
135 else
136 arch_spin_lock(&die_lock);
137 }
138 die_nest_count++;
139 die_owner = cpu;
140 console_verbose();
141 bust_spinlocks(1);
142 if (machine_is(powermac))
143 pmac_backlight_unblank();
144 return flags;
145 }
146
147 static void __kprobes oops_end(unsigned long flags, struct pt_regs *regs,
148 int signr)
149 {
150 bust_spinlocks(0);
151 die_owner = -1;
152 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
153 die_nest_count--;
154 oops_exit();
155 printk("\n");
156 if (!die_nest_count)
157 /* Nest count reaches zero, release the lock. */
158 arch_spin_unlock(&die_lock);
159 raw_local_irq_restore(flags);
160
161 crash_fadump(regs, "die oops");
162
163 /*
164 * A system reset (0x100) is a request to dump, so we always send
165 * it through the crashdump code.
166 */
167 if (kexec_should_crash(current) || (TRAP(regs) == 0x100)) {
168 crash_kexec(regs);
169
170 /*
171 * We aren't the primary crash CPU. We need to send it
172 * to a holding pattern to avoid it ending up in the panic
173 * code.
174 */
175 crash_kexec_secondary(regs);
176 }
177
178 if (!signr)
179 return;
180
181 /*
182 * While our oops output is serialised by a spinlock, output
183 * from panic() called below can race and corrupt it. If we
184 * know we are going to panic, delay for 1 second so we have a
185 * chance to get clean backtraces from all CPUs that are oopsing.
186 */
187 if (in_interrupt() || panic_on_oops || !current->pid ||
188 is_global_init(current)) {
189 mdelay(MSEC_PER_SEC);
190 }
191
192 if (in_interrupt())
193 panic("Fatal exception in interrupt");
194 if (panic_on_oops)
195 panic("Fatal exception");
196 do_exit(signr);
197 }
198
199 static int __kprobes __die(const char *str, struct pt_regs *regs, long err)
200 {
201 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
202 #ifdef CONFIG_PREEMPT
203 printk("PREEMPT ");
204 #endif
205 #ifdef CONFIG_SMP
206 printk("SMP NR_CPUS=%d ", NR_CPUS);
207 #endif
208 #ifdef CONFIG_DEBUG_PAGEALLOC
209 printk("DEBUG_PAGEALLOC ");
210 #endif
211 #ifdef CONFIG_NUMA
212 printk("NUMA ");
213 #endif
214 printk("%s\n", ppc_md.name ? ppc_md.name : "");
215
216 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
217 return 1;
218
219 print_modules();
220 show_regs(regs);
221
222 return 0;
223 }
224
225 void die(const char *str, struct pt_regs *regs, long err)
226 {
227 unsigned long flags = oops_begin(regs);
228
229 if (__die(str, regs, err))
230 err = 0;
231 oops_end(flags, regs, err);
232 }
233
234 void user_single_step_siginfo(struct task_struct *tsk,
235 struct pt_regs *regs, siginfo_t *info)
236 {
237 memset(info, 0, sizeof(*info));
238 info->si_signo = SIGTRAP;
239 info->si_code = TRAP_TRACE;
240 info->si_addr = (void __user *)regs->nip;
241 }
242
243 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
244 {
245 siginfo_t info;
246 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
247 "at %08lx nip %08lx lr %08lx code %x\n";
248 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
249 "at %016lx nip %016lx lr %016lx code %x\n";
250
251 if (!user_mode(regs)) {
252 die("Exception in kernel mode", regs, signr);
253 return;
254 }
255
256 if (show_unhandled_signals && unhandled_signal(current, signr)) {
257 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
258 current->comm, current->pid, signr,
259 addr, regs->nip, regs->link, code);
260 }
261
262 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
263 local_irq_enable();
264
265 current->thread.trap_nr = code;
266 memset(&info, 0, sizeof(info));
267 info.si_signo = signr;
268 info.si_code = code;
269 info.si_addr = (void __user *) addr;
270 force_sig_info(signr, &info, current);
271 }
272
273 #ifdef CONFIG_PPC64
274 void system_reset_exception(struct pt_regs *regs)
275 {
276 /* See if any machine dependent calls */
277 if (ppc_md.system_reset_exception) {
278 if (ppc_md.system_reset_exception(regs))
279 return;
280 }
281
282 die("System Reset", regs, SIGABRT);
283
284 /* Must die if the interrupt is not recoverable */
285 if (!(regs->msr & MSR_RI))
286 panic("Unrecoverable System Reset");
287
288 /* What should we do here? We could issue a shutdown or hard reset. */
289 }
290 #endif
291
292 /*
293 * I/O accesses can cause machine checks on powermacs.
294 * Check if the NIP corresponds to the address of a sync
295 * instruction for which there is an entry in the exception
296 * table.
297 * Note that the 601 only takes a machine check on TEA
298 * (transfer error ack) signal assertion, and does not
299 * set any of the top 16 bits of SRR1.
300 * -- paulus.
301 */
302 static inline int check_io_access(struct pt_regs *regs)
303 {
304 #ifdef CONFIG_PPC32
305 unsigned long msr = regs->msr;
306 const struct exception_table_entry *entry;
307 unsigned int *nip = (unsigned int *)regs->nip;
308
309 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
310 && (entry = search_exception_tables(regs->nip)) != NULL) {
311 /*
312 * Check that it's a sync instruction, or somewhere
313 * in the twi; isync; nop sequence that inb/inw/inl uses.
314 * As the address is in the exception table
315 * we should be able to read the instr there.
316 * For the debug message, we look at the preceding
317 * load or store.
318 */
319 if (*nip == 0x60000000) /* nop */
320 nip -= 2;
321 else if (*nip == 0x4c00012c) /* isync */
322 --nip;
323 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
324 /* sync or twi */
325 unsigned int rb;
326
327 --nip;
328 rb = (*nip >> 11) & 0x1f;
329 printk(KERN_DEBUG "%s bad port %lx at %p\n",
330 (*nip & 0x100)? "OUT to": "IN from",
331 regs->gpr[rb] - _IO_BASE, nip);
332 regs->msr |= MSR_RI;
333 regs->nip = entry->fixup;
334 return 1;
335 }
336 }
337 #endif /* CONFIG_PPC32 */
338 return 0;
339 }
340
341 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
342 /* On 4xx, the reason for the machine check or program exception
343 is in the ESR. */
344 #define get_reason(regs) ((regs)->dsisr)
345 #ifndef CONFIG_FSL_BOOKE
346 #define get_mc_reason(regs) ((regs)->dsisr)
347 #else
348 #define get_mc_reason(regs) (mfspr(SPRN_MCSR))
349 #endif
350 #define REASON_FP ESR_FP
351 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
352 #define REASON_PRIVILEGED ESR_PPR
353 #define REASON_TRAP ESR_PTR
354
355 /* single-step stuff */
356 #define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC)
357 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
358
359 #else
360 /* On non-4xx, the reason for the machine check or program
361 exception is in the MSR. */
362 #define get_reason(regs) ((regs)->msr)
363 #define get_mc_reason(regs) ((regs)->msr)
364 #define REASON_TM 0x200000
365 #define REASON_FP 0x100000
366 #define REASON_ILLEGAL 0x80000
367 #define REASON_PRIVILEGED 0x40000
368 #define REASON_TRAP 0x20000
369
370 #define single_stepping(regs) ((regs)->msr & MSR_SE)
371 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
372 #endif
373
374 #if defined(CONFIG_4xx)
375 int machine_check_4xx(struct pt_regs *regs)
376 {
377 unsigned long reason = get_mc_reason(regs);
378
379 if (reason & ESR_IMCP) {
380 printk("Instruction");
381 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
382 } else
383 printk("Data");
384 printk(" machine check in kernel mode.\n");
385
386 return 0;
387 }
388
389 int machine_check_440A(struct pt_regs *regs)
390 {
391 unsigned long reason = get_mc_reason(regs);
392
393 printk("Machine check in kernel mode.\n");
394 if (reason & ESR_IMCP){
395 printk("Instruction Synchronous Machine Check exception\n");
396 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
397 }
398 else {
399 u32 mcsr = mfspr(SPRN_MCSR);
400 if (mcsr & MCSR_IB)
401 printk("Instruction Read PLB Error\n");
402 if (mcsr & MCSR_DRB)
403 printk("Data Read PLB Error\n");
404 if (mcsr & MCSR_DWB)
405 printk("Data Write PLB Error\n");
406 if (mcsr & MCSR_TLBP)
407 printk("TLB Parity Error\n");
408 if (mcsr & MCSR_ICP){
409 flush_instruction_cache();
410 printk("I-Cache Parity Error\n");
411 }
412 if (mcsr & MCSR_DCSP)
413 printk("D-Cache Search Parity Error\n");
414 if (mcsr & MCSR_DCFP)
415 printk("D-Cache Flush Parity Error\n");
416 if (mcsr & MCSR_IMPE)
417 printk("Machine Check exception is imprecise\n");
418
419 /* Clear MCSR */
420 mtspr(SPRN_MCSR, mcsr);
421 }
422 return 0;
423 }
424
425 int machine_check_47x(struct pt_regs *regs)
426 {
427 unsigned long reason = get_mc_reason(regs);
428 u32 mcsr;
429
430 printk(KERN_ERR "Machine check in kernel mode.\n");
431 if (reason & ESR_IMCP) {
432 printk(KERN_ERR
433 "Instruction Synchronous Machine Check exception\n");
434 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
435 return 0;
436 }
437 mcsr = mfspr(SPRN_MCSR);
438 if (mcsr & MCSR_IB)
439 printk(KERN_ERR "Instruction Read PLB Error\n");
440 if (mcsr & MCSR_DRB)
441 printk(KERN_ERR "Data Read PLB Error\n");
442 if (mcsr & MCSR_DWB)
443 printk(KERN_ERR "Data Write PLB Error\n");
444 if (mcsr & MCSR_TLBP)
445 printk(KERN_ERR "TLB Parity Error\n");
446 if (mcsr & MCSR_ICP) {
447 flush_instruction_cache();
448 printk(KERN_ERR "I-Cache Parity Error\n");
449 }
450 if (mcsr & MCSR_DCSP)
451 printk(KERN_ERR "D-Cache Search Parity Error\n");
452 if (mcsr & PPC47x_MCSR_GPR)
453 printk(KERN_ERR "GPR Parity Error\n");
454 if (mcsr & PPC47x_MCSR_FPR)
455 printk(KERN_ERR "FPR Parity Error\n");
456 if (mcsr & PPC47x_MCSR_IPR)
457 printk(KERN_ERR "Machine Check exception is imprecise\n");
458
459 /* Clear MCSR */
460 mtspr(SPRN_MCSR, mcsr);
461
462 return 0;
463 }
464 #elif defined(CONFIG_E500)
465 int machine_check_e500mc(struct pt_regs *regs)
466 {
467 unsigned long mcsr = mfspr(SPRN_MCSR);
468 unsigned long reason = mcsr;
469 int recoverable = 1;
470
471 if (reason & MCSR_LD) {
472 recoverable = fsl_rio_mcheck_exception(regs);
473 if (recoverable == 1)
474 goto silent_out;
475 }
476
477 printk("Machine check in kernel mode.\n");
478 printk("Caused by (from MCSR=%lx): ", reason);
479
480 if (reason & MCSR_MCP)
481 printk("Machine Check Signal\n");
482
483 if (reason & MCSR_ICPERR) {
484 printk("Instruction Cache Parity Error\n");
485
486 /*
487 * This is recoverable by invalidating the i-cache.
488 */
489 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
490 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
491 ;
492
493 /*
494 * This will generally be accompanied by an instruction
495 * fetch error report -- only treat MCSR_IF as fatal
496 * if it wasn't due to an L1 parity error.
497 */
498 reason &= ~MCSR_IF;
499 }
500
501 if (reason & MCSR_DCPERR_MC) {
502 printk("Data Cache Parity Error\n");
503
504 /*
505 * In write shadow mode we auto-recover from the error, but it
506 * may still get logged and cause a machine check. We should
507 * only treat the non-write shadow case as non-recoverable.
508 */
509 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
510 recoverable = 0;
511 }
512
513 if (reason & MCSR_L2MMU_MHIT) {
514 printk("Hit on multiple TLB entries\n");
515 recoverable = 0;
516 }
517
518 if (reason & MCSR_NMI)
519 printk("Non-maskable interrupt\n");
520
521 if (reason & MCSR_IF) {
522 printk("Instruction Fetch Error Report\n");
523 recoverable = 0;
524 }
525
526 if (reason & MCSR_LD) {
527 printk("Load Error Report\n");
528 recoverable = 0;
529 }
530
531 if (reason & MCSR_ST) {
532 printk("Store Error Report\n");
533 recoverable = 0;
534 }
535
536 if (reason & MCSR_LDG) {
537 printk("Guarded Load Error Report\n");
538 recoverable = 0;
539 }
540
541 if (reason & MCSR_TLBSYNC)
542 printk("Simultaneous tlbsync operations\n");
543
544 if (reason & MCSR_BSL2_ERR) {
545 printk("Level 2 Cache Error\n");
546 recoverable = 0;
547 }
548
549 if (reason & MCSR_MAV) {
550 u64 addr;
551
552 addr = mfspr(SPRN_MCAR);
553 addr |= (u64)mfspr(SPRN_MCARU) << 32;
554
555 printk("Machine Check %s Address: %#llx\n",
556 reason & MCSR_MEA ? "Effective" : "Physical", addr);
557 }
558
559 silent_out:
560 mtspr(SPRN_MCSR, mcsr);
561 return mfspr(SPRN_MCSR) == 0 && recoverable;
562 }
563
564 int machine_check_e500(struct pt_regs *regs)
565 {
566 unsigned long reason = get_mc_reason(regs);
567
568 if (reason & MCSR_BUS_RBERR) {
569 if (fsl_rio_mcheck_exception(regs))
570 return 1;
571 if (fsl_pci_mcheck_exception(regs))
572 return 1;
573 }
574
575 printk("Machine check in kernel mode.\n");
576 printk("Caused by (from MCSR=%lx): ", reason);
577
578 if (reason & MCSR_MCP)
579 printk("Machine Check Signal\n");
580 if (reason & MCSR_ICPERR)
581 printk("Instruction Cache Parity Error\n");
582 if (reason & MCSR_DCP_PERR)
583 printk("Data Cache Push Parity Error\n");
584 if (reason & MCSR_DCPERR)
585 printk("Data Cache Parity Error\n");
586 if (reason & MCSR_BUS_IAERR)
587 printk("Bus - Instruction Address Error\n");
588 if (reason & MCSR_BUS_RAERR)
589 printk("Bus - Read Address Error\n");
590 if (reason & MCSR_BUS_WAERR)
591 printk("Bus - Write Address Error\n");
592 if (reason & MCSR_BUS_IBERR)
593 printk("Bus - Instruction Data Error\n");
594 if (reason & MCSR_BUS_RBERR)
595 printk("Bus - Read Data Bus Error\n");
596 if (reason & MCSR_BUS_WBERR)
597 printk("Bus - Read Data Bus Error\n");
598 if (reason & MCSR_BUS_IPERR)
599 printk("Bus - Instruction Parity Error\n");
600 if (reason & MCSR_BUS_RPERR)
601 printk("Bus - Read Parity Error\n");
602
603 return 0;
604 }
605
606 int machine_check_generic(struct pt_regs *regs)
607 {
608 return 0;
609 }
610 #elif defined(CONFIG_E200)
611 int machine_check_e200(struct pt_regs *regs)
612 {
613 unsigned long reason = get_mc_reason(regs);
614
615 printk("Machine check in kernel mode.\n");
616 printk("Caused by (from MCSR=%lx): ", reason);
617
618 if (reason & MCSR_MCP)
619 printk("Machine Check Signal\n");
620 if (reason & MCSR_CP_PERR)
621 printk("Cache Push Parity Error\n");
622 if (reason & MCSR_CPERR)
623 printk("Cache Parity Error\n");
624 if (reason & MCSR_EXCP_ERR)
625 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
626 if (reason & MCSR_BUS_IRERR)
627 printk("Bus - Read Bus Error on instruction fetch\n");
628 if (reason & MCSR_BUS_DRERR)
629 printk("Bus - Read Bus Error on data load\n");
630 if (reason & MCSR_BUS_WRERR)
631 printk("Bus - Write Bus Error on buffered store or cache line push\n");
632
633 return 0;
634 }
635 #else
636 int machine_check_generic(struct pt_regs *regs)
637 {
638 unsigned long reason = get_mc_reason(regs);
639
640 printk("Machine check in kernel mode.\n");
641 printk("Caused by (from SRR1=%lx): ", reason);
642 switch (reason & 0x601F0000) {
643 case 0x80000:
644 printk("Machine check signal\n");
645 break;
646 case 0: /* for 601 */
647 case 0x40000:
648 case 0x140000: /* 7450 MSS error and TEA */
649 printk("Transfer error ack signal\n");
650 break;
651 case 0x20000:
652 printk("Data parity error signal\n");
653 break;
654 case 0x10000:
655 printk("Address parity error signal\n");
656 break;
657 case 0x20000000:
658 printk("L1 Data Cache error\n");
659 break;
660 case 0x40000000:
661 printk("L1 Instruction Cache error\n");
662 break;
663 case 0x00100000:
664 printk("L2 data cache parity error\n");
665 break;
666 default:
667 printk("Unknown values in msr\n");
668 }
669 return 0;
670 }
671 #endif /* everything else */
672
673 void machine_check_exception(struct pt_regs *regs)
674 {
675 enum ctx_state prev_state = exception_enter();
676 int recover = 0;
677
678 __get_cpu_var(irq_stat).mce_exceptions++;
679
680 /* See if any machine dependent calls. In theory, we would want
681 * to call the CPU first, and call the ppc_md. one if the CPU
682 * one returns a positive number. However there is existing code
683 * that assumes the board gets a first chance, so let's keep it
684 * that way for now and fix things later. --BenH.
685 */
686 if (ppc_md.machine_check_exception)
687 recover = ppc_md.machine_check_exception(regs);
688 else if (cur_cpu_spec->machine_check)
689 recover = cur_cpu_spec->machine_check(regs);
690
691 if (recover > 0)
692 goto bail;
693
694 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
695 /* the qspan pci read routines can cause machine checks -- Cort
696 *
697 * yuck !!! that totally needs to go away ! There are better ways
698 * to deal with that than having a wart in the mcheck handler.
699 * -- BenH
700 */
701 bad_page_fault(regs, regs->dar, SIGBUS);
702 goto bail;
703 #endif
704
705 if (debugger_fault_handler(regs))
706 goto bail;
707
708 if (check_io_access(regs))
709 goto bail;
710
711 die("Machine check", regs, SIGBUS);
712
713 /* Must die if the interrupt is not recoverable */
714 if (!(regs->msr & MSR_RI))
715 panic("Unrecoverable Machine check");
716
717 bail:
718 exception_exit(prev_state);
719 }
720
721 void SMIException(struct pt_regs *regs)
722 {
723 die("System Management Interrupt", regs, SIGABRT);
724 }
725
726 void unknown_exception(struct pt_regs *regs)
727 {
728 enum ctx_state prev_state = exception_enter();
729
730 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
731 regs->nip, regs->msr, regs->trap);
732
733 _exception(SIGTRAP, regs, 0, 0);
734
735 exception_exit(prev_state);
736 }
737
738 void instruction_breakpoint_exception(struct pt_regs *regs)
739 {
740 enum ctx_state prev_state = exception_enter();
741
742 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
743 5, SIGTRAP) == NOTIFY_STOP)
744 goto bail;
745 if (debugger_iabr_match(regs))
746 goto bail;
747 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
748
749 bail:
750 exception_exit(prev_state);
751 }
752
753 void RunModeException(struct pt_regs *regs)
754 {
755 _exception(SIGTRAP, regs, 0, 0);
756 }
757
758 void __kprobes single_step_exception(struct pt_regs *regs)
759 {
760 enum ctx_state prev_state = exception_enter();
761
762 clear_single_step(regs);
763
764 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
765 5, SIGTRAP) == NOTIFY_STOP)
766 goto bail;
767 if (debugger_sstep(regs))
768 goto bail;
769
770 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
771
772 bail:
773 exception_exit(prev_state);
774 }
775
776 /*
777 * After we have successfully emulated an instruction, we have to
778 * check if the instruction was being single-stepped, and if so,
779 * pretend we got a single-step exception. This was pointed out
780 * by Kumar Gala. -- paulus
781 */
782 static void emulate_single_step(struct pt_regs *regs)
783 {
784 if (single_stepping(regs))
785 single_step_exception(regs);
786 }
787
788 static inline int __parse_fpscr(unsigned long fpscr)
789 {
790 int ret = 0;
791
792 /* Invalid operation */
793 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
794 ret = FPE_FLTINV;
795
796 /* Overflow */
797 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
798 ret = FPE_FLTOVF;
799
800 /* Underflow */
801 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
802 ret = FPE_FLTUND;
803
804 /* Divide by zero */
805 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
806 ret = FPE_FLTDIV;
807
808 /* Inexact result */
809 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
810 ret = FPE_FLTRES;
811
812 return ret;
813 }
814
815 static void parse_fpe(struct pt_regs *regs)
816 {
817 int code = 0;
818
819 flush_fp_to_thread(current);
820
821 code = __parse_fpscr(current->thread.fpscr.val);
822
823 _exception(SIGFPE, regs, code, regs->nip);
824 }
825
826 /*
827 * Illegal instruction emulation support. Originally written to
828 * provide the PVR to user applications using the mfspr rd, PVR.
829 * Return non-zero if we can't emulate, or -EFAULT if the associated
830 * memory access caused an access fault. Return zero on success.
831 *
832 * There are a couple of ways to do this, either "decode" the instruction
833 * or directly match lots of bits. In this case, matching lots of
834 * bits is faster and easier.
835 *
836 */
837 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
838 {
839 u8 rT = (instword >> 21) & 0x1f;
840 u8 rA = (instword >> 16) & 0x1f;
841 u8 NB_RB = (instword >> 11) & 0x1f;
842 u32 num_bytes;
843 unsigned long EA;
844 int pos = 0;
845
846 /* Early out if we are an invalid form of lswx */
847 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
848 if ((rT == rA) || (rT == NB_RB))
849 return -EINVAL;
850
851 EA = (rA == 0) ? 0 : regs->gpr[rA];
852
853 switch (instword & PPC_INST_STRING_MASK) {
854 case PPC_INST_LSWX:
855 case PPC_INST_STSWX:
856 EA += NB_RB;
857 num_bytes = regs->xer & 0x7f;
858 break;
859 case PPC_INST_LSWI:
860 case PPC_INST_STSWI:
861 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
862 break;
863 default:
864 return -EINVAL;
865 }
866
867 while (num_bytes != 0)
868 {
869 u8 val;
870 u32 shift = 8 * (3 - (pos & 0x3));
871
872 /* if process is 32-bit, clear upper 32 bits of EA */
873 if ((regs->msr & MSR_64BIT) == 0)
874 EA &= 0xFFFFFFFF;
875
876 switch ((instword & PPC_INST_STRING_MASK)) {
877 case PPC_INST_LSWX:
878 case PPC_INST_LSWI:
879 if (get_user(val, (u8 __user *)EA))
880 return -EFAULT;
881 /* first time updating this reg,
882 * zero it out */
883 if (pos == 0)
884 regs->gpr[rT] = 0;
885 regs->gpr[rT] |= val << shift;
886 break;
887 case PPC_INST_STSWI:
888 case PPC_INST_STSWX:
889 val = regs->gpr[rT] >> shift;
890 if (put_user(val, (u8 __user *)EA))
891 return -EFAULT;
892 break;
893 }
894 /* move EA to next address */
895 EA += 1;
896 num_bytes--;
897
898 /* manage our position within the register */
899 if (++pos == 4) {
900 pos = 0;
901 if (++rT == 32)
902 rT = 0;
903 }
904 }
905
906 return 0;
907 }
908
909 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
910 {
911 u32 ra,rs;
912 unsigned long tmp;
913
914 ra = (instword >> 16) & 0x1f;
915 rs = (instword >> 21) & 0x1f;
916
917 tmp = regs->gpr[rs];
918 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
919 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
920 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
921 regs->gpr[ra] = tmp;
922
923 return 0;
924 }
925
926 static int emulate_isel(struct pt_regs *regs, u32 instword)
927 {
928 u8 rT = (instword >> 21) & 0x1f;
929 u8 rA = (instword >> 16) & 0x1f;
930 u8 rB = (instword >> 11) & 0x1f;
931 u8 BC = (instword >> 6) & 0x1f;
932 u8 bit;
933 unsigned long tmp;
934
935 tmp = (rA == 0) ? 0 : regs->gpr[rA];
936 bit = (regs->ccr >> (31 - BC)) & 0x1;
937
938 regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
939
940 return 0;
941 }
942
943 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
944 static inline bool tm_abort_check(struct pt_regs *regs, int cause)
945 {
946 /* If we're emulating a load/store in an active transaction, we cannot
947 * emulate it as the kernel operates in transaction suspended context.
948 * We need to abort the transaction. This creates a persistent TM
949 * abort so tell the user what caused it with a new code.
950 */
951 if (MSR_TM_TRANSACTIONAL(regs->msr)) {
952 tm_enable();
953 tm_abort(cause);
954 return true;
955 }
956 return false;
957 }
958 #else
959 static inline bool tm_abort_check(struct pt_regs *regs, int reason)
960 {
961 return false;
962 }
963 #endif
964
965 static int emulate_instruction(struct pt_regs *regs)
966 {
967 u32 instword;
968 u32 rd;
969
970 if (!user_mode(regs) || (regs->msr & MSR_LE))
971 return -EINVAL;
972 CHECK_FULL_REGS(regs);
973
974 if (get_user(instword, (u32 __user *)(regs->nip)))
975 return -EFAULT;
976
977 /* Emulate the mfspr rD, PVR. */
978 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
979 PPC_WARN_EMULATED(mfpvr, regs);
980 rd = (instword >> 21) & 0x1f;
981 regs->gpr[rd] = mfspr(SPRN_PVR);
982 return 0;
983 }
984
985 /* Emulating the dcba insn is just a no-op. */
986 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
987 PPC_WARN_EMULATED(dcba, regs);
988 return 0;
989 }
990
991 /* Emulate the mcrxr insn. */
992 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
993 int shift = (instword >> 21) & 0x1c;
994 unsigned long msk = 0xf0000000UL >> shift;
995
996 PPC_WARN_EMULATED(mcrxr, regs);
997 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
998 regs->xer &= ~0xf0000000UL;
999 return 0;
1000 }
1001
1002 /* Emulate load/store string insn. */
1003 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
1004 if (tm_abort_check(regs,
1005 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
1006 return -EINVAL;
1007 PPC_WARN_EMULATED(string, regs);
1008 return emulate_string_inst(regs, instword);
1009 }
1010
1011 /* Emulate the popcntb (Population Count Bytes) instruction. */
1012 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
1013 PPC_WARN_EMULATED(popcntb, regs);
1014 return emulate_popcntb_inst(regs, instword);
1015 }
1016
1017 /* Emulate isel (Integer Select) instruction */
1018 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
1019 PPC_WARN_EMULATED(isel, regs);
1020 return emulate_isel(regs, instword);
1021 }
1022
1023 #ifdef CONFIG_PPC64
1024 /* Emulate the mfspr rD, DSCR. */
1025 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
1026 PPC_INST_MFSPR_DSCR_USER) ||
1027 ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
1028 PPC_INST_MFSPR_DSCR)) &&
1029 cpu_has_feature(CPU_FTR_DSCR)) {
1030 PPC_WARN_EMULATED(mfdscr, regs);
1031 rd = (instword >> 21) & 0x1f;
1032 regs->gpr[rd] = mfspr(SPRN_DSCR);
1033 return 0;
1034 }
1035 /* Emulate the mtspr DSCR, rD. */
1036 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
1037 PPC_INST_MTSPR_DSCR_USER) ||
1038 ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
1039 PPC_INST_MTSPR_DSCR)) &&
1040 cpu_has_feature(CPU_FTR_DSCR)) {
1041 PPC_WARN_EMULATED(mtdscr, regs);
1042 rd = (instword >> 21) & 0x1f;
1043 current->thread.dscr = regs->gpr[rd];
1044 current->thread.dscr_inherit = 1;
1045 mtspr(SPRN_DSCR, current->thread.dscr);
1046 return 0;
1047 }
1048 #endif
1049
1050 return -EINVAL;
1051 }
1052
1053 int is_valid_bugaddr(unsigned long addr)
1054 {
1055 return is_kernel_addr(addr);
1056 }
1057
1058 void __kprobes program_check_exception(struct pt_regs *regs)
1059 {
1060 enum ctx_state prev_state = exception_enter();
1061 unsigned int reason = get_reason(regs);
1062 extern int do_mathemu(struct pt_regs *regs);
1063
1064 /* We can now get here via a FP Unavailable exception if the core
1065 * has no FPU, in that case the reason flags will be 0 */
1066
1067 if (reason & REASON_FP) {
1068 /* IEEE FP exception */
1069 parse_fpe(regs);
1070 goto bail;
1071 }
1072 if (reason & REASON_TRAP) {
1073 /* Debugger is first in line to stop recursive faults in
1074 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1075 if (debugger_bpt(regs))
1076 goto bail;
1077
1078 /* trap exception */
1079 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
1080 == NOTIFY_STOP)
1081 goto bail;
1082
1083 if (!(regs->msr & MSR_PR) && /* not user-mode */
1084 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
1085 regs->nip += 4;
1086 goto bail;
1087 }
1088 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1089 goto bail;
1090 }
1091 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1092 if (reason & REASON_TM) {
1093 /* This is a TM "Bad Thing Exception" program check.
1094 * This occurs when:
1095 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1096 * transition in TM states.
1097 * - A trechkpt is attempted when transactional.
1098 * - A treclaim is attempted when non transactional.
1099 * - A tend is illegally attempted.
1100 * - writing a TM SPR when transactional.
1101 */
1102 if (!user_mode(regs) &&
1103 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
1104 regs->nip += 4;
1105 goto bail;
1106 }
1107 /* If usermode caused this, it's done something illegal and
1108 * gets a SIGILL slap on the wrist. We call it an illegal
1109 * operand to distinguish from the instruction just being bad
1110 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1111 * illegal /placement/ of a valid instruction.
1112 */
1113 if (user_mode(regs)) {
1114 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
1115 goto bail;
1116 } else {
1117 printk(KERN_EMERG "Unexpected TM Bad Thing exception "
1118 "at %lx (msr 0x%x)\n", regs->nip, reason);
1119 die("Unrecoverable exception", regs, SIGABRT);
1120 }
1121 }
1122 #endif
1123
1124 /* We restore the interrupt state now */
1125 if (!arch_irq_disabled_regs(regs))
1126 local_irq_enable();
1127
1128 #ifdef CONFIG_MATH_EMULATION
1129 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1130 * but there seems to be a hardware bug on the 405GP (RevD)
1131 * that means ESR is sometimes set incorrectly - either to
1132 * ESR_DST (!?) or 0. In the process of chasing this with the
1133 * hardware people - not sure if it can happen on any illegal
1134 * instruction or only on FP instructions, whether there is a
1135 * pattern to occurrences etc. -dgibson 31/Mar/2003
1136 */
1137 switch (do_mathemu(regs)) {
1138 case 0:
1139 emulate_single_step(regs);
1140 goto bail;
1141 case 1: {
1142 int code = 0;
1143 code = __parse_fpscr(current->thread.fpscr.val);
1144 _exception(SIGFPE, regs, code, regs->nip);
1145 goto bail;
1146 }
1147 case -EFAULT:
1148 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1149 goto bail;
1150 }
1151 /* fall through on any other errors */
1152 #endif /* CONFIG_MATH_EMULATION */
1153
1154 /* Try to emulate it if we should. */
1155 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
1156 switch (emulate_instruction(regs)) {
1157 case 0:
1158 regs->nip += 4;
1159 emulate_single_step(regs);
1160 goto bail;
1161 case -EFAULT:
1162 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1163 goto bail;
1164 }
1165 }
1166
1167 if (reason & REASON_PRIVILEGED)
1168 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1169 else
1170 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1171
1172 bail:
1173 exception_exit(prev_state);
1174 }
1175
1176 /*
1177 * This occurs when running in hypervisor mode on POWER6 or later
1178 * and an illegal instruction is encountered.
1179 */
1180 void __kprobes emulation_assist_interrupt(struct pt_regs *regs)
1181 {
1182 regs->msr |= REASON_ILLEGAL;
1183 program_check_exception(regs);
1184 }
1185
1186 void alignment_exception(struct pt_regs *regs)
1187 {
1188 enum ctx_state prev_state = exception_enter();
1189 int sig, code, fixed = 0;
1190
1191 /* We restore the interrupt state now */
1192 if (!arch_irq_disabled_regs(regs))
1193 local_irq_enable();
1194
1195 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT))
1196 goto bail;
1197
1198 /* we don't implement logging of alignment exceptions */
1199 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1200 fixed = fix_alignment(regs);
1201
1202 if (fixed == 1) {
1203 regs->nip += 4; /* skip over emulated instruction */
1204 emulate_single_step(regs);
1205 goto bail;
1206 }
1207
1208 /* Operand address was bad */
1209 if (fixed == -EFAULT) {
1210 sig = SIGSEGV;
1211 code = SEGV_ACCERR;
1212 } else {
1213 sig = SIGBUS;
1214 code = BUS_ADRALN;
1215 }
1216 if (user_mode(regs))
1217 _exception(sig, regs, code, regs->dar);
1218 else
1219 bad_page_fault(regs, regs->dar, sig);
1220
1221 bail:
1222 exception_exit(prev_state);
1223 }
1224
1225 void StackOverflow(struct pt_regs *regs)
1226 {
1227 printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
1228 current, regs->gpr[1]);
1229 debugger(regs);
1230 show_regs(regs);
1231 panic("kernel stack overflow");
1232 }
1233
1234 void nonrecoverable_exception(struct pt_regs *regs)
1235 {
1236 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
1237 regs->nip, regs->msr);
1238 debugger(regs);
1239 die("nonrecoverable exception", regs, SIGKILL);
1240 }
1241
1242 void trace_syscall(struct pt_regs *regs)
1243 {
1244 printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld %s\n",
1245 current, task_pid_nr(current), regs->nip, regs->link, regs->gpr[0],
1246 regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
1247 }
1248
1249 void kernel_fp_unavailable_exception(struct pt_regs *regs)
1250 {
1251 enum ctx_state prev_state = exception_enter();
1252
1253 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1254 "%lx at %lx\n", regs->trap, regs->nip);
1255 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1256
1257 exception_exit(prev_state);
1258 }
1259
1260 void altivec_unavailable_exception(struct pt_regs *regs)
1261 {
1262 enum ctx_state prev_state = exception_enter();
1263
1264 if (user_mode(regs)) {
1265 /* A user program has executed an altivec instruction,
1266 but this kernel doesn't support altivec. */
1267 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1268 goto bail;
1269 }
1270
1271 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1272 "%lx at %lx\n", regs->trap, regs->nip);
1273 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1274
1275 bail:
1276 exception_exit(prev_state);
1277 }
1278
1279 void vsx_unavailable_exception(struct pt_regs *regs)
1280 {
1281 if (user_mode(regs)) {
1282 /* A user program has executed an vsx instruction,
1283 but this kernel doesn't support vsx. */
1284 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1285 return;
1286 }
1287
1288 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1289 "%lx at %lx\n", regs->trap, regs->nip);
1290 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1291 }
1292
1293 void facility_unavailable_exception(struct pt_regs *regs)
1294 {
1295 static char *facility_strings[] = {
1296 "FPU",
1297 "VMX/VSX",
1298 "DSCR",
1299 "PMU SPRs",
1300 "BHRB",
1301 "TM",
1302 "AT",
1303 "EBB",
1304 "TAR",
1305 };
1306 char *facility, *prefix;
1307 u64 value;
1308
1309 if (regs->trap == 0xf60) {
1310 value = mfspr(SPRN_FSCR);
1311 prefix = "";
1312 } else {
1313 value = mfspr(SPRN_HFSCR);
1314 prefix = "Hypervisor ";
1315 }
1316
1317 value = value >> 56;
1318
1319 /* We restore the interrupt state now */
1320 if (!arch_irq_disabled_regs(regs))
1321 local_irq_enable();
1322
1323 if (value < ARRAY_SIZE(facility_strings))
1324 facility = facility_strings[value];
1325 else
1326 facility = "unknown";
1327
1328 pr_err("%sFacility '%s' unavailable, exception at 0x%lx, MSR=%lx\n",
1329 prefix, facility, regs->nip, regs->msr);
1330
1331 if (user_mode(regs)) {
1332 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1333 return;
1334 }
1335
1336 die("Unexpected facility unavailable exception", regs, SIGABRT);
1337 }
1338
1339 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1340
1341 extern void do_load_up_fpu(struct pt_regs *regs);
1342
1343 void fp_unavailable_tm(struct pt_regs *regs)
1344 {
1345 /* Note: This does not handle any kind of FP laziness. */
1346
1347 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1348 regs->nip, regs->msr);
1349 tm_enable();
1350
1351 /* We can only have got here if the task started using FP after
1352 * beginning the transaction. So, the transactional regs are just a
1353 * copy of the checkpointed ones. But, we still need to recheckpoint
1354 * as we're enabling FP for the process; it will return, abort the
1355 * transaction, and probably retry but now with FP enabled. So the
1356 * checkpointed FP registers need to be loaded.
1357 */
1358 tm_reclaim(&current->thread, current->thread.regs->msr,
1359 TM_CAUSE_FAC_UNAV);
1360 /* Reclaim didn't save out any FPRs to transact_fprs. */
1361
1362 /* Enable FP for the task: */
1363 regs->msr |= (MSR_FP | current->thread.fpexc_mode);
1364
1365 /* This loads and recheckpoints the FP registers from
1366 * thread.fpr[]. They will remain in registers after the
1367 * checkpoint so we don't need to reload them after.
1368 */
1369 tm_recheckpoint(&current->thread, regs->msr);
1370 }
1371
1372 #ifdef CONFIG_ALTIVEC
1373 extern void do_load_up_altivec(struct pt_regs *regs);
1374
1375 void altivec_unavailable_tm(struct pt_regs *regs)
1376 {
1377 /* See the comments in fp_unavailable_tm(). This function operates
1378 * the same way.
1379 */
1380
1381 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1382 "MSR=%lx\n",
1383 regs->nip, regs->msr);
1384 tm_enable();
1385 tm_reclaim(&current->thread, current->thread.regs->msr,
1386 TM_CAUSE_FAC_UNAV);
1387 regs->msr |= MSR_VEC;
1388 tm_recheckpoint(&current->thread, regs->msr);
1389 current->thread.used_vr = 1;
1390 }
1391 #endif
1392
1393 #ifdef CONFIG_VSX
1394 void vsx_unavailable_tm(struct pt_regs *regs)
1395 {
1396 /* See the comments in fp_unavailable_tm(). This works similarly,
1397 * though we're loading both FP and VEC registers in here.
1398 *
1399 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1400 * regs. Either way, set MSR_VSX.
1401 */
1402
1403 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1404 "MSR=%lx\n",
1405 regs->nip, regs->msr);
1406
1407 tm_enable();
1408 /* This reclaims FP and/or VR regs if they're already enabled */
1409 tm_reclaim(&current->thread, current->thread.regs->msr,
1410 TM_CAUSE_FAC_UNAV);
1411
1412 regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode |
1413 MSR_VSX;
1414 /* This loads & recheckpoints FP and VRs. */
1415 tm_recheckpoint(&current->thread, regs->msr);
1416 current->thread.used_vsr = 1;
1417 }
1418 #endif
1419 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1420
1421 void performance_monitor_exception(struct pt_regs *regs)
1422 {
1423 __get_cpu_var(irq_stat).pmu_irqs++;
1424
1425 perf_irq(regs);
1426 }
1427
1428 #ifdef CONFIG_8xx
1429 void SoftwareEmulation(struct pt_regs *regs)
1430 {
1431 extern int do_mathemu(struct pt_regs *);
1432 #if defined(CONFIG_MATH_EMULATION)
1433 int errcode;
1434 #endif
1435
1436 CHECK_FULL_REGS(regs);
1437
1438 if (!user_mode(regs)) {
1439 debugger(regs);
1440 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
1441 }
1442
1443 #ifdef CONFIG_MATH_EMULATION
1444 errcode = do_mathemu(regs);
1445 if (errcode >= 0)
1446 PPC_WARN_EMULATED(math, regs);
1447
1448 switch (errcode) {
1449 case 0:
1450 emulate_single_step(regs);
1451 return;
1452 case 1: {
1453 int code = 0;
1454 code = __parse_fpscr(current->thread.fpscr.val);
1455 _exception(SIGFPE, regs, code, regs->nip);
1456 return;
1457 }
1458 case -EFAULT:
1459 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1460 return;
1461 default:
1462 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1463 return;
1464 }
1465 #else
1466 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1467 #endif
1468 }
1469 #endif /* CONFIG_8xx */
1470
1471 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1472 static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1473 {
1474 int changed = 0;
1475 /*
1476 * Determine the cause of the debug event, clear the
1477 * event flags and send a trap to the handler. Torez
1478 */
1479 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1480 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1481 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1482 current->thread.dbcr2 &= ~DBCR2_DAC12MODE;
1483 #endif
1484 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
1485 5);
1486 changed |= 0x01;
1487 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
1488 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1489 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
1490 6);
1491 changed |= 0x01;
1492 } else if (debug_status & DBSR_IAC1) {
1493 current->thread.dbcr0 &= ~DBCR0_IAC1;
1494 dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1495 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
1496 1);
1497 changed |= 0x01;
1498 } else if (debug_status & DBSR_IAC2) {
1499 current->thread.dbcr0 &= ~DBCR0_IAC2;
1500 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
1501 2);
1502 changed |= 0x01;
1503 } else if (debug_status & DBSR_IAC3) {
1504 current->thread.dbcr0 &= ~DBCR0_IAC3;
1505 dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1506 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
1507 3);
1508 changed |= 0x01;
1509 } else if (debug_status & DBSR_IAC4) {
1510 current->thread.dbcr0 &= ~DBCR0_IAC4;
1511 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
1512 4);
1513 changed |= 0x01;
1514 }
1515 /*
1516 * At the point this routine was called, the MSR(DE) was turned off.
1517 * Check all other debug flags and see if that bit needs to be turned
1518 * back on or not.
1519 */
1520 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1))
1521 regs->msr |= MSR_DE;
1522 else
1523 /* Make sure the IDM flag is off */
1524 current->thread.dbcr0 &= ~DBCR0_IDM;
1525
1526 if (changed & 0x01)
1527 mtspr(SPRN_DBCR0, current->thread.dbcr0);
1528 }
1529
1530 void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
1531 {
1532 current->thread.dbsr = debug_status;
1533
1534 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1535 * on server, it stops on the target of the branch. In order to simulate
1536 * the server behaviour, we thus restart right away with a single step
1537 * instead of stopping here when hitting a BT
1538 */
1539 if (debug_status & DBSR_BT) {
1540 regs->msr &= ~MSR_DE;
1541
1542 /* Disable BT */
1543 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1544 /* Clear the BT event */
1545 mtspr(SPRN_DBSR, DBSR_BT);
1546
1547 /* Do the single step trick only when coming from userspace */
1548 if (user_mode(regs)) {
1549 current->thread.dbcr0 &= ~DBCR0_BT;
1550 current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1551 regs->msr |= MSR_DE;
1552 return;
1553 }
1554
1555 if (notify_die(DIE_SSTEP, "block_step", regs, 5,
1556 5, SIGTRAP) == NOTIFY_STOP) {
1557 return;
1558 }
1559 if (debugger_sstep(regs))
1560 return;
1561 } else if (debug_status & DBSR_IC) { /* Instruction complete */
1562 regs->msr &= ~MSR_DE;
1563
1564 /* Disable instruction completion */
1565 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
1566 /* Clear the instruction completion event */
1567 mtspr(SPRN_DBSR, DBSR_IC);
1568
1569 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1570 5, SIGTRAP) == NOTIFY_STOP) {
1571 return;
1572 }
1573
1574 if (debugger_sstep(regs))
1575 return;
1576
1577 if (user_mode(regs)) {
1578 current->thread.dbcr0 &= ~DBCR0_IC;
1579 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0,
1580 current->thread.dbcr1))
1581 regs->msr |= MSR_DE;
1582 else
1583 /* Make sure the IDM bit is off */
1584 current->thread.dbcr0 &= ~DBCR0_IDM;
1585 }
1586
1587 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1588 } else
1589 handle_debug(regs, debug_status);
1590 }
1591 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1592
1593 #if !defined(CONFIG_TAU_INT)
1594 void TAUException(struct pt_regs *regs)
1595 {
1596 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1597 regs->nip, regs->msr, regs->trap, print_tainted());
1598 }
1599 #endif /* CONFIG_INT_TAU */
1600
1601 #ifdef CONFIG_ALTIVEC
1602 void altivec_assist_exception(struct pt_regs *regs)
1603 {
1604 int err;
1605
1606 if (!user_mode(regs)) {
1607 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
1608 " at %lx\n", regs->nip);
1609 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
1610 }
1611
1612 flush_altivec_to_thread(current);
1613
1614 PPC_WARN_EMULATED(altivec, regs);
1615 err = emulate_altivec(regs);
1616 if (err == 0) {
1617 regs->nip += 4; /* skip emulated instruction */
1618 emulate_single_step(regs);
1619 return;
1620 }
1621
1622 if (err == -EFAULT) {
1623 /* got an error reading the instruction */
1624 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1625 } else {
1626 /* didn't recognize the instruction */
1627 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1628 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
1629 "in %s at %lx\n", current->comm, regs->nip);
1630 current->thread.vscr.u[3] |= 0x10000;
1631 }
1632 }
1633 #endif /* CONFIG_ALTIVEC */
1634
1635 #ifdef CONFIG_VSX
1636 void vsx_assist_exception(struct pt_regs *regs)
1637 {
1638 if (!user_mode(regs)) {
1639 printk(KERN_EMERG "VSX assist exception in kernel mode"
1640 " at %lx\n", regs->nip);
1641 die("Kernel VSX assist exception", regs, SIGILL);
1642 }
1643
1644 flush_vsx_to_thread(current);
1645 printk(KERN_INFO "VSX assist not supported at %lx\n", regs->nip);
1646 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1647 }
1648 #endif /* CONFIG_VSX */
1649
1650 #ifdef CONFIG_FSL_BOOKE
1651 void CacheLockingException(struct pt_regs *regs, unsigned long address,
1652 unsigned long error_code)
1653 {
1654 /* We treat cache locking instructions from the user
1655 * as priv ops, in the future we could try to do
1656 * something smarter
1657 */
1658 if (error_code & (ESR_DLK|ESR_ILK))
1659 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1660 return;
1661 }
1662 #endif /* CONFIG_FSL_BOOKE */
1663
1664 #ifdef CONFIG_SPE
1665 void SPEFloatingPointException(struct pt_regs *regs)
1666 {
1667 extern int do_spe_mathemu(struct pt_regs *regs);
1668 unsigned long spefscr;
1669 int fpexc_mode;
1670 int code = 0;
1671 int err;
1672
1673 flush_spe_to_thread(current);
1674
1675 spefscr = current->thread.spefscr;
1676 fpexc_mode = current->thread.fpexc_mode;
1677
1678 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1679 code = FPE_FLTOVF;
1680 }
1681 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1682 code = FPE_FLTUND;
1683 }
1684 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1685 code = FPE_FLTDIV;
1686 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1687 code = FPE_FLTINV;
1688 }
1689 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1690 code = FPE_FLTRES;
1691
1692 err = do_spe_mathemu(regs);
1693 if (err == 0) {
1694 regs->nip += 4; /* skip emulated instruction */
1695 emulate_single_step(regs);
1696 return;
1697 }
1698
1699 if (err == -EFAULT) {
1700 /* got an error reading the instruction */
1701 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1702 } else if (err == -EINVAL) {
1703 /* didn't recognize the instruction */
1704 printk(KERN_ERR "unrecognized spe instruction "
1705 "in %s at %lx\n", current->comm, regs->nip);
1706 } else {
1707 _exception(SIGFPE, regs, code, regs->nip);
1708 }
1709
1710 return;
1711 }
1712
1713 void SPEFloatingPointRoundException(struct pt_regs *regs)
1714 {
1715 extern int speround_handler(struct pt_regs *regs);
1716 int err;
1717
1718 preempt_disable();
1719 if (regs->msr & MSR_SPE)
1720 giveup_spe(current);
1721 preempt_enable();
1722
1723 regs->nip -= 4;
1724 err = speround_handler(regs);
1725 if (err == 0) {
1726 regs->nip += 4; /* skip emulated instruction */
1727 emulate_single_step(regs);
1728 return;
1729 }
1730
1731 if (err == -EFAULT) {
1732 /* got an error reading the instruction */
1733 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1734 } else if (err == -EINVAL) {
1735 /* didn't recognize the instruction */
1736 printk(KERN_ERR "unrecognized spe instruction "
1737 "in %s at %lx\n", current->comm, regs->nip);
1738 } else {
1739 _exception(SIGFPE, regs, 0, regs->nip);
1740 return;
1741 }
1742 }
1743 #endif
1744
1745 /*
1746 * We enter here if we get an unrecoverable exception, that is, one
1747 * that happened at a point where the RI (recoverable interrupt) bit
1748 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1749 * we therefore lost state by taking this exception.
1750 */
1751 void unrecoverable_exception(struct pt_regs *regs)
1752 {
1753 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1754 regs->trap, regs->nip);
1755 die("Unrecoverable exception", regs, SIGABRT);
1756 }
1757
1758 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
1759 /*
1760 * Default handler for a Watchdog exception,
1761 * spins until a reboot occurs
1762 */
1763 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1764 {
1765 /* Generic WatchdogHandler, implement your own */
1766 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1767 return;
1768 }
1769
1770 void WatchdogException(struct pt_regs *regs)
1771 {
1772 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1773 WatchdogHandler(regs);
1774 }
1775 #endif
1776
1777 /*
1778 * We enter here if we discover during exception entry that we are
1779 * running in supervisor mode with a userspace value in the stack pointer.
1780 */
1781 void kernel_bad_stack(struct pt_regs *regs)
1782 {
1783 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1784 regs->gpr[1], regs->nip);
1785 die("Bad kernel stack pointer", regs, SIGABRT);
1786 }
1787
1788 void __init trap_init(void)
1789 {
1790 }
1791
1792
1793 #ifdef CONFIG_PPC_EMULATED_STATS
1794
1795 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
1796
1797 struct ppc_emulated ppc_emulated = {
1798 #ifdef CONFIG_ALTIVEC
1799 WARN_EMULATED_SETUP(altivec),
1800 #endif
1801 WARN_EMULATED_SETUP(dcba),
1802 WARN_EMULATED_SETUP(dcbz),
1803 WARN_EMULATED_SETUP(fp_pair),
1804 WARN_EMULATED_SETUP(isel),
1805 WARN_EMULATED_SETUP(mcrxr),
1806 WARN_EMULATED_SETUP(mfpvr),
1807 WARN_EMULATED_SETUP(multiple),
1808 WARN_EMULATED_SETUP(popcntb),
1809 WARN_EMULATED_SETUP(spe),
1810 WARN_EMULATED_SETUP(string),
1811 WARN_EMULATED_SETUP(unaligned),
1812 #ifdef CONFIG_MATH_EMULATION
1813 WARN_EMULATED_SETUP(math),
1814 #endif
1815 #ifdef CONFIG_VSX
1816 WARN_EMULATED_SETUP(vsx),
1817 #endif
1818 #ifdef CONFIG_PPC64
1819 WARN_EMULATED_SETUP(mfdscr),
1820 WARN_EMULATED_SETUP(mtdscr),
1821 #endif
1822 };
1823
1824 u32 ppc_warn_emulated;
1825
1826 void ppc_warn_emulated_print(const char *type)
1827 {
1828 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
1829 type);
1830 }
1831
1832 static int __init ppc_warn_emulated_init(void)
1833 {
1834 struct dentry *dir, *d;
1835 unsigned int i;
1836 struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
1837
1838 if (!powerpc_debugfs_root)
1839 return -ENODEV;
1840
1841 dir = debugfs_create_dir("emulated_instructions",
1842 powerpc_debugfs_root);
1843 if (!dir)
1844 return -ENOMEM;
1845
1846 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir,
1847 &ppc_warn_emulated);
1848 if (!d)
1849 goto fail;
1850
1851 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
1852 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir,
1853 (u32 *)&entries[i].val.counter);
1854 if (!d)
1855 goto fail;
1856 }
1857
1858 return 0;
1859
1860 fail:
1861 debugfs_remove_recursive(dir);
1862 return -ENOMEM;
1863 }
1864
1865 device_initcall(ppc_warn_emulated_init);
1866
1867 #endif /* CONFIG_PPC_EMULATED_STATS */
Linux kernel - Deliverables
This page took 0.068557 seconds and 5 git commands to generate.