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powerpc: Fix regression of per-CPU DSCR setting
[deliverable/linux.git] / arch / powerpc / kvm / book3s_hv_rmhandlers.S
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
12 *
13 * Derived from book3s_rmhandlers.S and other files, which are:
14 *
15 * Copyright SUSE Linux Products GmbH 2009
16 *
17 * Authors: Alexander Graf <agraf@suse.de>
18 */
19
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
22 #include <asm/reg.h>
23 #include <asm/mmu.h>
24 #include <asm/page.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/mmu-hash64.h>
31 #include <asm/tm.h>
32
33 #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
34
35 #ifdef __LITTLE_ENDIAN__
36 #error Need to fix lppaca and SLB shadow accesses in little endian mode
37 #endif
38
39 /* Values in HSTATE_NAPPING(r13) */
40 #define NAPPING_CEDE 1
41 #define NAPPING_NOVCPU 2
42
43 /*
44 * Call kvmppc_hv_entry in real mode.
45 * Must be called with interrupts hard-disabled.
46 *
47 * Input Registers:
48 *
49 * LR = return address to continue at after eventually re-enabling MMU
50 */
51 _GLOBAL(kvmppc_hv_entry_trampoline)
52 mflr r0
53 std r0, PPC_LR_STKOFF(r1)
54 stdu r1, -112(r1)
55 mfmsr r10
56 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
57 li r0,MSR_RI
58 andc r0,r10,r0
59 li r6,MSR_IR | MSR_DR
60 andc r6,r10,r6
61 mtmsrd r0,1 /* clear RI in MSR */
62 mtsrr0 r5
63 mtsrr1 r6
64 RFI
65
66 kvmppc_call_hv_entry:
67 ld r4, HSTATE_KVM_VCPU(r13)
68 bl kvmppc_hv_entry
69
70 /* Back from guest - restore host state and return to caller */
71
72 BEGIN_FTR_SECTION
73 /* Restore host DABR and DABRX */
74 ld r5,HSTATE_DABR(r13)
75 li r6,7
76 mtspr SPRN_DABR,r5
77 mtspr SPRN_DABRX,r6
78 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
79
80 /* Restore SPRG3 */
81 ld r3,PACA_SPRG_VDSO(r13)
82 mtspr SPRN_SPRG_VDSO_WRITE,r3
83
84 /* Reload the host's PMU registers */
85 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
86 lbz r4, LPPACA_PMCINUSE(r3)
87 cmpwi r4, 0
88 beq 23f /* skip if not */
89 lwz r3, HSTATE_PMC(r13)
90 lwz r4, HSTATE_PMC + 4(r13)
91 lwz r5, HSTATE_PMC + 8(r13)
92 lwz r6, HSTATE_PMC + 12(r13)
93 lwz r8, HSTATE_PMC + 16(r13)
94 lwz r9, HSTATE_PMC + 20(r13)
95 BEGIN_FTR_SECTION
96 lwz r10, HSTATE_PMC + 24(r13)
97 lwz r11, HSTATE_PMC + 28(r13)
98 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
99 mtspr SPRN_PMC1, r3
100 mtspr SPRN_PMC2, r4
101 mtspr SPRN_PMC3, r5
102 mtspr SPRN_PMC4, r6
103 mtspr SPRN_PMC5, r8
104 mtspr SPRN_PMC6, r9
105 BEGIN_FTR_SECTION
106 mtspr SPRN_PMC7, r10
107 mtspr SPRN_PMC8, r11
108 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
109 ld r3, HSTATE_MMCR(r13)
110 ld r4, HSTATE_MMCR + 8(r13)
111 ld r5, HSTATE_MMCR + 16(r13)
112 ld r6, HSTATE_MMCR + 24(r13)
113 ld r7, HSTATE_MMCR + 32(r13)
114 mtspr SPRN_MMCR1, r4
115 mtspr SPRN_MMCRA, r5
116 mtspr SPRN_SIAR, r6
117 mtspr SPRN_SDAR, r7
118 BEGIN_FTR_SECTION
119 ld r8, HSTATE_MMCR + 40(r13)
120 ld r9, HSTATE_MMCR + 48(r13)
121 mtspr SPRN_MMCR2, r8
122 mtspr SPRN_SIER, r9
123 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
124 mtspr SPRN_MMCR0, r3
125 isync
126 23:
127
128 /*
129 * Reload DEC. HDEC interrupts were disabled when
130 * we reloaded the host's LPCR value.
131 */
132 ld r3, HSTATE_DECEXP(r13)
133 mftb r4
134 subf r4, r4, r3
135 mtspr SPRN_DEC, r4
136
137 /*
138 * For external and machine check interrupts, we need
139 * to call the Linux handler to process the interrupt.
140 * We do that by jumping to absolute address 0x500 for
141 * external interrupts, or the machine_check_fwnmi label
142 * for machine checks (since firmware might have patched
143 * the vector area at 0x200). The [h]rfid at the end of the
144 * handler will return to the book3s_hv_interrupts.S code.
145 * For other interrupts we do the rfid to get back
146 * to the book3s_hv_interrupts.S code here.
147 */
148 ld r8, 112+PPC_LR_STKOFF(r1)
149 addi r1, r1, 112
150 ld r7, HSTATE_HOST_MSR(r13)
151
152 cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
153 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
154 BEGIN_FTR_SECTION
155 beq 11f
156 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
157
158 /* RFI into the highmem handler, or branch to interrupt handler */
159 mfmsr r6
160 li r0, MSR_RI
161 andc r6, r6, r0
162 mtmsrd r6, 1 /* Clear RI in MSR */
163 mtsrr0 r8
164 mtsrr1 r7
165 beqa 0x500 /* external interrupt (PPC970) */
166 beq cr1, 13f /* machine check */
167 RFI
168
169 /* On POWER7, we have external interrupts set to use HSRR0/1 */
170 11: mtspr SPRN_HSRR0, r8
171 mtspr SPRN_HSRR1, r7
172 ba 0x500
173
174 13: b machine_check_fwnmi
175
176 kvmppc_primary_no_guest:
177 /* We handle this much like a ceded vcpu */
178 /* set our bit in napping_threads */
179 ld r5, HSTATE_KVM_VCORE(r13)
180 lbz r7, HSTATE_PTID(r13)
181 li r0, 1
182 sld r0, r0, r7
183 addi r6, r5, VCORE_NAPPING_THREADS
184 1: lwarx r3, 0, r6
185 or r3, r3, r0
186 stwcx. r3, 0, r6
187 bne 1b
188 /* order napping_threads update vs testing entry_exit_count */
189 isync
190 li r12, 0
191 lwz r7, VCORE_ENTRY_EXIT(r5)
192 cmpwi r7, 0x100
193 bge kvm_novcpu_exit /* another thread already exiting */
194 li r3, NAPPING_NOVCPU
195 stb r3, HSTATE_NAPPING(r13)
196 li r3, 1
197 stb r3, HSTATE_HWTHREAD_REQ(r13)
198
199 b kvm_do_nap
200
201 kvm_novcpu_wakeup:
202 ld r1, HSTATE_HOST_R1(r13)
203 ld r5, HSTATE_KVM_VCORE(r13)
204 li r0, 0
205 stb r0, HSTATE_NAPPING(r13)
206 stb r0, HSTATE_HWTHREAD_REQ(r13)
207
208 /* check the wake reason */
209 bl kvmppc_check_wake_reason
210
211 /* see if any other thread is already exiting */
212 lwz r0, VCORE_ENTRY_EXIT(r5)
213 cmpwi r0, 0x100
214 bge kvm_novcpu_exit
215
216 /* clear our bit in napping_threads */
217 lbz r7, HSTATE_PTID(r13)
218 li r0, 1
219 sld r0, r0, r7
220 addi r6, r5, VCORE_NAPPING_THREADS
221 4: lwarx r7, 0, r6
222 andc r7, r7, r0
223 stwcx. r7, 0, r6
224 bne 4b
225
226 /* See if the wake reason means we need to exit */
227 cmpdi r3, 0
228 bge kvm_novcpu_exit
229
230 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
231 ld r4, HSTATE_KVM_VCPU(r13)
232 cmpdi r4, 0
233 bne kvmppc_got_guest
234
235 kvm_novcpu_exit:
236 b hdec_soon
237
238 /*
239 * We come in here when wakened from nap mode.
240 * Relocation is off and most register values are lost.
241 * r13 points to the PACA.
242 */
243 .globl kvm_start_guest
244 kvm_start_guest:
245
246 /* Set runlatch bit the minute you wake up from nap */
247 mfspr r1, SPRN_CTRLF
248 ori r1, r1, 1
249 mtspr SPRN_CTRLT, r1
250
251 ld r2,PACATOC(r13)
252
253 li r0,KVM_HWTHREAD_IN_KVM
254 stb r0,HSTATE_HWTHREAD_STATE(r13)
255
256 /* NV GPR values from power7_idle() will no longer be valid */
257 li r0,1
258 stb r0,PACA_NAPSTATELOST(r13)
259
260 /* were we napping due to cede? */
261 lbz r0,HSTATE_NAPPING(r13)
262 cmpwi r0,NAPPING_CEDE
263 beq kvm_end_cede
264 cmpwi r0,NAPPING_NOVCPU
265 beq kvm_novcpu_wakeup
266
267 ld r1,PACAEMERGSP(r13)
268 subi r1,r1,STACK_FRAME_OVERHEAD
269
270 /*
271 * We weren't napping due to cede, so this must be a secondary
272 * thread being woken up to run a guest, or being woken up due
273 * to a stray IPI. (Or due to some machine check or hypervisor
274 * maintenance interrupt while the core is in KVM.)
275 */
276
277 /* Check the wake reason in SRR1 to see why we got here */
278 bl kvmppc_check_wake_reason
279 cmpdi r3, 0
280 bge kvm_no_guest
281
282 /* get vcpu pointer, NULL if we have no vcpu to run */
283 ld r4,HSTATE_KVM_VCPU(r13)
284 cmpdi r4,0
285 /* if we have no vcpu to run, go back to sleep */
286 beq kvm_no_guest
287
288 /* Set HSTATE_DSCR(r13) to something sensible */
289 ld r6, PACA_DSCR(r13)
290 std r6, HSTATE_DSCR(r13)
291
292 bl kvmppc_hv_entry
293
294 /* Back from the guest, go back to nap */
295 /* Clear our vcpu pointer so we don't come back in early */
296 li r0, 0
297 std r0, HSTATE_KVM_VCPU(r13)
298 /*
299 * Make sure we clear HSTATE_KVM_VCPU(r13) before incrementing
300 * the nap_count, because once the increment to nap_count is
301 * visible we could be given another vcpu.
302 */
303 lwsync
304
305 /* increment the nap count and then go to nap mode */
306 ld r4, HSTATE_KVM_VCORE(r13)
307 addi r4, r4, VCORE_NAP_COUNT
308 51: lwarx r3, 0, r4
309 addi r3, r3, 1
310 stwcx. r3, 0, r4
311 bne 51b
312
313 kvm_no_guest:
314 li r0, KVM_HWTHREAD_IN_NAP
315 stb r0, HSTATE_HWTHREAD_STATE(r13)
316 kvm_do_nap:
317 /* Clear the runlatch bit before napping */
318 mfspr r2, SPRN_CTRLF
319 clrrdi r2, r2, 1
320 mtspr SPRN_CTRLT, r2
321
322 li r3, LPCR_PECE0
323 mfspr r4, SPRN_LPCR
324 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
325 mtspr SPRN_LPCR, r4
326 isync
327 std r0, HSTATE_SCRATCH0(r13)
328 ptesync
329 ld r0, HSTATE_SCRATCH0(r13)
330 1: cmpd r0, r0
331 bne 1b
332 nap
333 b .
334
335 /******************************************************************************
336 * *
337 * Entry code *
338 * *
339 *****************************************************************************/
340
341 .global kvmppc_hv_entry
342 kvmppc_hv_entry:
343
344 /* Required state:
345 *
346 * R4 = vcpu pointer (or NULL)
347 * MSR = ~IR|DR
348 * R13 = PACA
349 * R1 = host R1
350 * all other volatile GPRS = free
351 */
352 mflr r0
353 std r0, PPC_LR_STKOFF(r1)
354 stdu r1, -112(r1)
355
356 /* Save R1 in the PACA */
357 std r1, HSTATE_HOST_R1(r13)
358
359 li r6, KVM_GUEST_MODE_HOST_HV
360 stb r6, HSTATE_IN_GUEST(r13)
361
362 /* Clear out SLB */
363 li r6,0
364 slbmte r6,r6
365 slbia
366 ptesync
367
368 BEGIN_FTR_SECTION
369 b 30f
370 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
371 /*
372 * POWER7 host -> guest partition switch code.
373 * We don't have to lock against concurrent tlbies,
374 * but we do have to coordinate across hardware threads.
375 */
376 /* Increment entry count iff exit count is zero. */
377 ld r5,HSTATE_KVM_VCORE(r13)
378 addi r9,r5,VCORE_ENTRY_EXIT
379 21: lwarx r3,0,r9
380 cmpwi r3,0x100 /* any threads starting to exit? */
381 bge secondary_too_late /* if so we're too late to the party */
382 addi r3,r3,1
383 stwcx. r3,0,r9
384 bne 21b
385
386 /* Primary thread switches to guest partition. */
387 ld r9,VCORE_KVM(r5) /* pointer to struct kvm */
388 lbz r6,HSTATE_PTID(r13)
389 cmpwi r6,0
390 bne 20f
391 ld r6,KVM_SDR1(r9)
392 lwz r7,KVM_LPID(r9)
393 li r0,LPID_RSVD /* switch to reserved LPID */
394 mtspr SPRN_LPID,r0
395 ptesync
396 mtspr SPRN_SDR1,r6 /* switch to partition page table */
397 mtspr SPRN_LPID,r7
398 isync
399
400 /* See if we need to flush the TLB */
401 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
402 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
403 srdi r6,r6,6 /* doubleword number */
404 sldi r6,r6,3 /* address offset */
405 add r6,r6,r9
406 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
407 li r0,1
408 sld r0,r0,r7
409 ld r7,0(r6)
410 and. r7,r7,r0
411 beq 22f
412 23: ldarx r7,0,r6 /* if set, clear the bit */
413 andc r7,r7,r0
414 stdcx. r7,0,r6
415 bne 23b
416 /* Flush the TLB of any entries for this LPID */
417 /* use arch 2.07S as a proxy for POWER8 */
418 BEGIN_FTR_SECTION
419 li r6,512 /* POWER8 has 512 sets */
420 FTR_SECTION_ELSE
421 li r6,128 /* POWER7 has 128 sets */
422 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
423 mtctr r6
424 li r7,0x800 /* IS field = 0b10 */
425 ptesync
426 28: tlbiel r7
427 addi r7,r7,0x1000
428 bdnz 28b
429 ptesync
430
431 /* Add timebase offset onto timebase */
432 22: ld r8,VCORE_TB_OFFSET(r5)
433 cmpdi r8,0
434 beq 37f
435 mftb r6 /* current host timebase */
436 add r8,r8,r6
437 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
438 mftb r7 /* check if lower 24 bits overflowed */
439 clrldi r6,r6,40
440 clrldi r7,r7,40
441 cmpld r7,r6
442 bge 37f
443 addis r8,r8,0x100 /* if so, increment upper 40 bits */
444 mtspr SPRN_TBU40,r8
445
446 /* Load guest PCR value to select appropriate compat mode */
447 37: ld r7, VCORE_PCR(r5)
448 cmpdi r7, 0
449 beq 38f
450 mtspr SPRN_PCR, r7
451 38:
452
453 BEGIN_FTR_SECTION
454 /* DPDES is shared between threads */
455 ld r8, VCORE_DPDES(r5)
456 mtspr SPRN_DPDES, r8
457 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
458
459 li r0,1
460 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
461 b 10f
462
463 /* Secondary threads wait for primary to have done partition switch */
464 20: lbz r0,VCORE_IN_GUEST(r5)
465 cmpwi r0,0
466 beq 20b
467
468 /* Set LPCR and RMOR. */
469 10: ld r8,VCORE_LPCR(r5)
470 mtspr SPRN_LPCR,r8
471 ld r8,KVM_RMOR(r9)
472 mtspr SPRN_RMOR,r8
473 isync
474
475 /* Check if HDEC expires soon */
476 mfspr r3,SPRN_HDEC
477 cmpwi r3,512 /* 1 microsecond */
478 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
479 blt hdec_soon
480 b 31f
481
482 /*
483 * PPC970 host -> guest partition switch code.
484 * We have to lock against concurrent tlbies,
485 * using native_tlbie_lock to lock against host tlbies
486 * and kvm->arch.tlbie_lock to lock against guest tlbies.
487 * We also have to invalidate the TLB since its
488 * entries aren't tagged with the LPID.
489 */
490 30: ld r5,HSTATE_KVM_VCORE(r13)
491 ld r9,VCORE_KVM(r5) /* pointer to struct kvm */
492
493 /* first take native_tlbie_lock */
494 .section ".toc","aw"
495 toc_tlbie_lock:
496 .tc native_tlbie_lock[TC],native_tlbie_lock
497 .previous
498 ld r3,toc_tlbie_lock@toc(2)
499 #ifdef __BIG_ENDIAN__
500 lwz r8,PACA_LOCK_TOKEN(r13)
501 #else
502 lwz r8,PACAPACAINDEX(r13)
503 #endif
504 24: lwarx r0,0,r3
505 cmpwi r0,0
506 bne 24b
507 stwcx. r8,0,r3
508 bne 24b
509 isync
510
511 ld r5,HSTATE_KVM_VCORE(r13)
512 ld r7,VCORE_LPCR(r5) /* use vcore->lpcr to store HID4 */
513 li r0,0x18f
514 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
515 or r0,r7,r0
516 ptesync
517 sync
518 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
519 isync
520 li r0,0
521 stw r0,0(r3) /* drop native_tlbie_lock */
522
523 /* invalidate the whole TLB */
524 li r0,256
525 mtctr r0
526 li r6,0
527 25: tlbiel r6
528 addi r6,r6,0x1000
529 bdnz 25b
530 ptesync
531
532 /* Take the guest's tlbie_lock */
533 addi r3,r9,KVM_TLBIE_LOCK
534 24: lwarx r0,0,r3
535 cmpwi r0,0
536 bne 24b
537 stwcx. r8,0,r3
538 bne 24b
539 isync
540 ld r6,KVM_SDR1(r9)
541 mtspr SPRN_SDR1,r6 /* switch to partition page table */
542
543 /* Set up HID4 with the guest's LPID etc. */
544 sync
545 mtspr SPRN_HID4,r7
546 isync
547
548 /* drop the guest's tlbie_lock */
549 li r0,0
550 stw r0,0(r3)
551
552 /* Check if HDEC expires soon */
553 mfspr r3,SPRN_HDEC
554 cmpwi r3,10
555 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
556 blt hdec_soon
557
558 /* Enable HDEC interrupts */
559 mfspr r0,SPRN_HID0
560 li r3,1
561 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
562 sync
563 mtspr SPRN_HID0,r0
564 mfspr r0,SPRN_HID0
565 mfspr r0,SPRN_HID0
566 mfspr r0,SPRN_HID0
567 mfspr r0,SPRN_HID0
568 mfspr r0,SPRN_HID0
569 mfspr r0,SPRN_HID0
570 31:
571 /* Do we have a guest vcpu to run? */
572 cmpdi r4, 0
573 beq kvmppc_primary_no_guest
574 kvmppc_got_guest:
575
576 /* Load up guest SLB entries */
577 lwz r5,VCPU_SLB_MAX(r4)
578 cmpwi r5,0
579 beq 9f
580 mtctr r5
581 addi r6,r4,VCPU_SLB
582 1: ld r8,VCPU_SLB_E(r6)
583 ld r9,VCPU_SLB_V(r6)
584 slbmte r9,r8
585 addi r6,r6,VCPU_SLB_SIZE
586 bdnz 1b
587 9:
588 /* Increment yield count if they have a VPA */
589 ld r3, VCPU_VPA(r4)
590 cmpdi r3, 0
591 beq 25f
592 lwz r5, LPPACA_YIELDCOUNT(r3)
593 addi r5, r5, 1
594 stw r5, LPPACA_YIELDCOUNT(r3)
595 li r6, 1
596 stb r6, VCPU_VPA_DIRTY(r4)
597 25:
598
599 BEGIN_FTR_SECTION
600 /* Save purr/spurr */
601 mfspr r5,SPRN_PURR
602 mfspr r6,SPRN_SPURR
603 std r5,HSTATE_PURR(r13)
604 std r6,HSTATE_SPURR(r13)
605 ld r7,VCPU_PURR(r4)
606 ld r8,VCPU_SPURR(r4)
607 mtspr SPRN_PURR,r7
608 mtspr SPRN_SPURR,r8
609 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
610
611 BEGIN_FTR_SECTION
612 /* Set partition DABR */
613 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
614 lwz r5,VCPU_DABRX(r4)
615 ld r6,VCPU_DABR(r4)
616 mtspr SPRN_DABRX,r5
617 mtspr SPRN_DABR,r6
618 BEGIN_FTR_SECTION_NESTED(89)
619 isync
620 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_206, CPU_FTR_ARCH_206, 89)
621 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
622
623 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
624 BEGIN_FTR_SECTION
625 b skip_tm
626 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
627
628 /* Turn on TM/FP/VSX/VMX so we can restore them. */
629 mfmsr r5
630 li r6, MSR_TM >> 32
631 sldi r6, r6, 32
632 or r5, r5, r6
633 ori r5, r5, MSR_FP
634 oris r5, r5, (MSR_VEC | MSR_VSX)@h
635 mtmsrd r5
636
637 /*
638 * The user may change these outside of a transaction, so they must
639 * always be context switched.
640 */
641 ld r5, VCPU_TFHAR(r4)
642 ld r6, VCPU_TFIAR(r4)
643 ld r7, VCPU_TEXASR(r4)
644 mtspr SPRN_TFHAR, r5
645 mtspr SPRN_TFIAR, r6
646 mtspr SPRN_TEXASR, r7
647
648 ld r5, VCPU_MSR(r4)
649 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
650 beq skip_tm /* TM not active in guest */
651
652 /* Make sure the failure summary is set, otherwise we'll program check
653 * when we trechkpt. It's possible that this might have been not set
654 * on a kvmppc_set_one_reg() call but we shouldn't let this crash the
655 * host.
656 */
657 oris r7, r7, (TEXASR_FS)@h
658 mtspr SPRN_TEXASR, r7
659
660 /*
661 * We need to load up the checkpointed state for the guest.
662 * We need to do this early as it will blow away any GPRs, VSRs and
663 * some SPRs.
664 */
665
666 mr r31, r4
667 addi r3, r31, VCPU_FPRS_TM
668 bl .load_fp_state
669 addi r3, r31, VCPU_VRS_TM
670 bl .load_vr_state
671 mr r4, r31
672 lwz r7, VCPU_VRSAVE_TM(r4)
673 mtspr SPRN_VRSAVE, r7
674
675 ld r5, VCPU_LR_TM(r4)
676 lwz r6, VCPU_CR_TM(r4)
677 ld r7, VCPU_CTR_TM(r4)
678 ld r8, VCPU_AMR_TM(r4)
679 ld r9, VCPU_TAR_TM(r4)
680 mtlr r5
681 mtcr r6
682 mtctr r7
683 mtspr SPRN_AMR, r8
684 mtspr SPRN_TAR, r9
685
686 /*
687 * Load up PPR and DSCR values but don't put them in the actual SPRs
688 * till the last moment to avoid running with userspace PPR and DSCR for
689 * too long.
690 */
691 ld r29, VCPU_DSCR_TM(r4)
692 ld r30, VCPU_PPR_TM(r4)
693
694 std r2, PACATMSCRATCH(r13) /* Save TOC */
695
696 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
697 li r5, 0
698 mtmsrd r5, 1
699
700 /* Load GPRs r0-r28 */
701 reg = 0
702 .rept 29
703 ld reg, VCPU_GPRS_TM(reg)(r31)
704 reg = reg + 1
705 .endr
706
707 mtspr SPRN_DSCR, r29
708 mtspr SPRN_PPR, r30
709
710 /* Load final GPRs */
711 ld 29, VCPU_GPRS_TM(29)(r31)
712 ld 30, VCPU_GPRS_TM(30)(r31)
713 ld 31, VCPU_GPRS_TM(31)(r31)
714
715 /* TM checkpointed state is now setup. All GPRs are now volatile. */
716 TRECHKPT
717
718 /* Now let's get back the state we need. */
719 HMT_MEDIUM
720 GET_PACA(r13)
721 ld r29, HSTATE_DSCR(r13)
722 mtspr SPRN_DSCR, r29
723 ld r4, HSTATE_KVM_VCPU(r13)
724 ld r1, HSTATE_HOST_R1(r13)
725 ld r2, PACATMSCRATCH(r13)
726
727 /* Set the MSR RI since we have our registers back. */
728 li r5, MSR_RI
729 mtmsrd r5, 1
730 skip_tm:
731 #endif
732
733 /* Load guest PMU registers */
734 /* R4 is live here (vcpu pointer) */
735 li r3, 1
736 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
737 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
738 isync
739 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
740 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
741 lwz r6, VCPU_PMC + 8(r4)
742 lwz r7, VCPU_PMC + 12(r4)
743 lwz r8, VCPU_PMC + 16(r4)
744 lwz r9, VCPU_PMC + 20(r4)
745 BEGIN_FTR_SECTION
746 lwz r10, VCPU_PMC + 24(r4)
747 lwz r11, VCPU_PMC + 28(r4)
748 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
749 mtspr SPRN_PMC1, r3
750 mtspr SPRN_PMC2, r5
751 mtspr SPRN_PMC3, r6
752 mtspr SPRN_PMC4, r7
753 mtspr SPRN_PMC5, r8
754 mtspr SPRN_PMC6, r9
755 BEGIN_FTR_SECTION
756 mtspr SPRN_PMC7, r10
757 mtspr SPRN_PMC8, r11
758 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
759 ld r3, VCPU_MMCR(r4)
760 ld r5, VCPU_MMCR + 8(r4)
761 ld r6, VCPU_MMCR + 16(r4)
762 ld r7, VCPU_SIAR(r4)
763 ld r8, VCPU_SDAR(r4)
764 mtspr SPRN_MMCR1, r5
765 mtspr SPRN_MMCRA, r6
766 mtspr SPRN_SIAR, r7
767 mtspr SPRN_SDAR, r8
768 BEGIN_FTR_SECTION
769 ld r5, VCPU_MMCR + 24(r4)
770 ld r6, VCPU_SIER(r4)
771 lwz r7, VCPU_PMC + 24(r4)
772 lwz r8, VCPU_PMC + 28(r4)
773 ld r9, VCPU_MMCR + 32(r4)
774 mtspr SPRN_MMCR2, r5
775 mtspr SPRN_SIER, r6
776 mtspr SPRN_SPMC1, r7
777 mtspr SPRN_SPMC2, r8
778 mtspr SPRN_MMCRS, r9
779 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
780 mtspr SPRN_MMCR0, r3
781 isync
782
783 /* Load up FP, VMX and VSX registers */
784 bl kvmppc_load_fp
785
786 ld r14, VCPU_GPR(R14)(r4)
787 ld r15, VCPU_GPR(R15)(r4)
788 ld r16, VCPU_GPR(R16)(r4)
789 ld r17, VCPU_GPR(R17)(r4)
790 ld r18, VCPU_GPR(R18)(r4)
791 ld r19, VCPU_GPR(R19)(r4)
792 ld r20, VCPU_GPR(R20)(r4)
793 ld r21, VCPU_GPR(R21)(r4)
794 ld r22, VCPU_GPR(R22)(r4)
795 ld r23, VCPU_GPR(R23)(r4)
796 ld r24, VCPU_GPR(R24)(r4)
797 ld r25, VCPU_GPR(R25)(r4)
798 ld r26, VCPU_GPR(R26)(r4)
799 ld r27, VCPU_GPR(R27)(r4)
800 ld r28, VCPU_GPR(R28)(r4)
801 ld r29, VCPU_GPR(R29)(r4)
802 ld r30, VCPU_GPR(R30)(r4)
803 ld r31, VCPU_GPR(R31)(r4)
804
805 BEGIN_FTR_SECTION
806 /* Switch DSCR to guest value */
807 ld r5, VCPU_DSCR(r4)
808 mtspr SPRN_DSCR, r5
809 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
810
811 BEGIN_FTR_SECTION
812 /* Skip next section on POWER7 or PPC970 */
813 b 8f
814 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
815 /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */
816 mfmsr r8
817 li r0, 1
818 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
819 mtmsrd r8
820
821 /* Load up POWER8-specific registers */
822 ld r5, VCPU_IAMR(r4)
823 lwz r6, VCPU_PSPB(r4)
824 ld r7, VCPU_FSCR(r4)
825 mtspr SPRN_IAMR, r5
826 mtspr SPRN_PSPB, r6
827 mtspr SPRN_FSCR, r7
828 ld r5, VCPU_DAWR(r4)
829 ld r6, VCPU_DAWRX(r4)
830 ld r7, VCPU_CIABR(r4)
831 ld r8, VCPU_TAR(r4)
832 mtspr SPRN_DAWR, r5
833 mtspr SPRN_DAWRX, r6
834 mtspr SPRN_CIABR, r7
835 mtspr SPRN_TAR, r8
836 ld r5, VCPU_IC(r4)
837 ld r6, VCPU_VTB(r4)
838 mtspr SPRN_IC, r5
839 mtspr SPRN_VTB, r6
840 ld r8, VCPU_EBBHR(r4)
841 mtspr SPRN_EBBHR, r8
842 ld r5, VCPU_EBBRR(r4)
843 ld r6, VCPU_BESCR(r4)
844 ld r7, VCPU_CSIGR(r4)
845 ld r8, VCPU_TACR(r4)
846 mtspr SPRN_EBBRR, r5
847 mtspr SPRN_BESCR, r6
848 mtspr SPRN_CSIGR, r7
849 mtspr SPRN_TACR, r8
850 ld r5, VCPU_TCSCR(r4)
851 ld r6, VCPU_ACOP(r4)
852 lwz r7, VCPU_GUEST_PID(r4)
853 ld r8, VCPU_WORT(r4)
854 mtspr SPRN_TCSCR, r5
855 mtspr SPRN_ACOP, r6
856 mtspr SPRN_PID, r7
857 mtspr SPRN_WORT, r8
858 8:
859
860 /*
861 * Set the decrementer to the guest decrementer.
862 */
863 ld r8,VCPU_DEC_EXPIRES(r4)
864 /* r8 is a host timebase value here, convert to guest TB */
865 ld r5,HSTATE_KVM_VCORE(r13)
866 ld r6,VCORE_TB_OFFSET(r5)
867 add r8,r8,r6
868 mftb r7
869 subf r3,r7,r8
870 mtspr SPRN_DEC,r3
871 stw r3,VCPU_DEC(r4)
872
873 ld r5, VCPU_SPRG0(r4)
874 ld r6, VCPU_SPRG1(r4)
875 ld r7, VCPU_SPRG2(r4)
876 ld r8, VCPU_SPRG3(r4)
877 mtspr SPRN_SPRG0, r5
878 mtspr SPRN_SPRG1, r6
879 mtspr SPRN_SPRG2, r7
880 mtspr SPRN_SPRG3, r8
881
882 /* Load up DAR and DSISR */
883 ld r5, VCPU_DAR(r4)
884 lwz r6, VCPU_DSISR(r4)
885 mtspr SPRN_DAR, r5
886 mtspr SPRN_DSISR, r6
887
888 BEGIN_FTR_SECTION
889 /* Restore AMR and UAMOR, set AMOR to all 1s */
890 ld r5,VCPU_AMR(r4)
891 ld r6,VCPU_UAMOR(r4)
892 li r7,-1
893 mtspr SPRN_AMR,r5
894 mtspr SPRN_UAMOR,r6
895 mtspr SPRN_AMOR,r7
896 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
897
898 /* Restore state of CTRL run bit; assume 1 on entry */
899 lwz r5,VCPU_CTRL(r4)
900 andi. r5,r5,1
901 bne 4f
902 mfspr r6,SPRN_CTRLF
903 clrrdi r6,r6,1
904 mtspr SPRN_CTRLT,r6
905 4:
906 ld r6, VCPU_CTR(r4)
907 lwz r7, VCPU_XER(r4)
908
909 mtctr r6
910 mtxer r7
911
912 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
913 ld r10, VCPU_PC(r4)
914 ld r11, VCPU_MSR(r4)
915 ld r6, VCPU_SRR0(r4)
916 ld r7, VCPU_SRR1(r4)
917 mtspr SPRN_SRR0, r6
918 mtspr SPRN_SRR1, r7
919
920 deliver_guest_interrupt:
921 /* r11 = vcpu->arch.msr & ~MSR_HV */
922 rldicl r11, r11, 63 - MSR_HV_LG, 1
923 rotldi r11, r11, 1 + MSR_HV_LG
924 ori r11, r11, MSR_ME
925
926 /* Check if we can deliver an external or decrementer interrupt now */
927 ld r0, VCPU_PENDING_EXC(r4)
928 rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
929 cmpdi cr1, r0, 0
930 andi. r8, r11, MSR_EE
931 BEGIN_FTR_SECTION
932 mfspr r8, SPRN_LPCR
933 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
934 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
935 mtspr SPRN_LPCR, r8
936 isync
937 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
938 beq 5f
939 li r0, BOOK3S_INTERRUPT_EXTERNAL
940 bne cr1, 12f
941 mfspr r0, SPRN_DEC
942 cmpwi r0, 0
943 li r0, BOOK3S_INTERRUPT_DECREMENTER
944 bge 5f
945
946 12: mtspr SPRN_SRR0, r10
947 mr r10,r0
948 mtspr SPRN_SRR1, r11
949 mr r9, r4
950 bl kvmppc_msr_interrupt
951 5:
952
953 /*
954 * Required state:
955 * R4 = vcpu
956 * R10: value for HSRR0
957 * R11: value for HSRR1
958 * R13 = PACA
959 */
960 fast_guest_return:
961 li r0,0
962 stb r0,VCPU_CEDED(r4) /* cancel cede */
963 mtspr SPRN_HSRR0,r10
964 mtspr SPRN_HSRR1,r11
965
966 /* Activate guest mode, so faults get handled by KVM */
967 li r9, KVM_GUEST_MODE_GUEST_HV
968 stb r9, HSTATE_IN_GUEST(r13)
969
970 /* Enter guest */
971
972 BEGIN_FTR_SECTION
973 ld r5, VCPU_CFAR(r4)
974 mtspr SPRN_CFAR, r5
975 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
976 BEGIN_FTR_SECTION
977 ld r0, VCPU_PPR(r4)
978 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
979
980 ld r5, VCPU_LR(r4)
981 lwz r6, VCPU_CR(r4)
982 mtlr r5
983 mtcr r6
984
985 ld r1, VCPU_GPR(R1)(r4)
986 ld r2, VCPU_GPR(R2)(r4)
987 ld r3, VCPU_GPR(R3)(r4)
988 ld r5, VCPU_GPR(R5)(r4)
989 ld r6, VCPU_GPR(R6)(r4)
990 ld r7, VCPU_GPR(R7)(r4)
991 ld r8, VCPU_GPR(R8)(r4)
992 ld r9, VCPU_GPR(R9)(r4)
993 ld r10, VCPU_GPR(R10)(r4)
994 ld r11, VCPU_GPR(R11)(r4)
995 ld r12, VCPU_GPR(R12)(r4)
996 ld r13, VCPU_GPR(R13)(r4)
997
998 BEGIN_FTR_SECTION
999 mtspr SPRN_PPR, r0
1000 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1001 ld r0, VCPU_GPR(R0)(r4)
1002 ld r4, VCPU_GPR(R4)(r4)
1003
1004 hrfid
1005 b .
1006
1007 /******************************************************************************
1008 * *
1009 * Exit code *
1010 * *
1011 *****************************************************************************/
1012
1013 /*
1014 * We come here from the first-level interrupt handlers.
1015 */
1016 .globl kvmppc_interrupt_hv
1017 kvmppc_interrupt_hv:
1018 /*
1019 * Register contents:
1020 * R12 = interrupt vector
1021 * R13 = PACA
1022 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
1023 * guest R13 saved in SPRN_SCRATCH0
1024 */
1025 std r9, HSTATE_SCRATCH2(r13)
1026
1027 lbz r9, HSTATE_IN_GUEST(r13)
1028 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1029 beq kvmppc_bad_host_intr
1030 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1031 cmpwi r9, KVM_GUEST_MODE_GUEST
1032 ld r9, HSTATE_SCRATCH2(r13)
1033 beq kvmppc_interrupt_pr
1034 #endif
1035 /* We're now back in the host but in guest MMU context */
1036 li r9, KVM_GUEST_MODE_HOST_HV
1037 stb r9, HSTATE_IN_GUEST(r13)
1038
1039 ld r9, HSTATE_KVM_VCPU(r13)
1040
1041 /* Save registers */
1042
1043 std r0, VCPU_GPR(R0)(r9)
1044 std r1, VCPU_GPR(R1)(r9)
1045 std r2, VCPU_GPR(R2)(r9)
1046 std r3, VCPU_GPR(R3)(r9)
1047 std r4, VCPU_GPR(R4)(r9)
1048 std r5, VCPU_GPR(R5)(r9)
1049 std r6, VCPU_GPR(R6)(r9)
1050 std r7, VCPU_GPR(R7)(r9)
1051 std r8, VCPU_GPR(R8)(r9)
1052 ld r0, HSTATE_SCRATCH2(r13)
1053 std r0, VCPU_GPR(R9)(r9)
1054 std r10, VCPU_GPR(R10)(r9)
1055 std r11, VCPU_GPR(R11)(r9)
1056 ld r3, HSTATE_SCRATCH0(r13)
1057 lwz r4, HSTATE_SCRATCH1(r13)
1058 std r3, VCPU_GPR(R12)(r9)
1059 stw r4, VCPU_CR(r9)
1060 BEGIN_FTR_SECTION
1061 ld r3, HSTATE_CFAR(r13)
1062 std r3, VCPU_CFAR(r9)
1063 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1064 BEGIN_FTR_SECTION
1065 ld r4, HSTATE_PPR(r13)
1066 std r4, VCPU_PPR(r9)
1067 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1068
1069 /* Restore R1/R2 so we can handle faults */
1070 ld r1, HSTATE_HOST_R1(r13)
1071 ld r2, PACATOC(r13)
1072
1073 mfspr r10, SPRN_SRR0
1074 mfspr r11, SPRN_SRR1
1075 std r10, VCPU_SRR0(r9)
1076 std r11, VCPU_SRR1(r9)
1077 andi. r0, r12, 2 /* need to read HSRR0/1? */
1078 beq 1f
1079 mfspr r10, SPRN_HSRR0
1080 mfspr r11, SPRN_HSRR1
1081 clrrdi r12, r12, 2
1082 1: std r10, VCPU_PC(r9)
1083 std r11, VCPU_MSR(r9)
1084
1085 GET_SCRATCH0(r3)
1086 mflr r4
1087 std r3, VCPU_GPR(R13)(r9)
1088 std r4, VCPU_LR(r9)
1089
1090 stw r12,VCPU_TRAP(r9)
1091
1092 /* Save HEIR (HV emulation assist reg) in last_inst
1093 if this is an HEI (HV emulation interrupt, e40) */
1094 li r3,KVM_INST_FETCH_FAILED
1095 BEGIN_FTR_SECTION
1096 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1097 bne 11f
1098 mfspr r3,SPRN_HEIR
1099 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1100 11: stw r3,VCPU_LAST_INST(r9)
1101
1102 /* these are volatile across C function calls */
1103 mfctr r3
1104 mfxer r4
1105 std r3, VCPU_CTR(r9)
1106 stw r4, VCPU_XER(r9)
1107
1108 BEGIN_FTR_SECTION
1109 /* If this is a page table miss then see if it's theirs or ours */
1110 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1111 beq kvmppc_hdsi
1112 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1113 beq kvmppc_hisi
1114 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1115
1116 /* See if this is a leftover HDEC interrupt */
1117 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1118 bne 2f
1119 mfspr r3,SPRN_HDEC
1120 cmpwi r3,0
1121 bge ignore_hdec
1122 2:
1123 /* See if this is an hcall we can handle in real mode */
1124 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1125 beq hcall_try_real_mode
1126
1127 /* Only handle external interrupts here on arch 206 and later */
1128 BEGIN_FTR_SECTION
1129 b ext_interrupt_to_host
1130 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1131
1132 /* External interrupt ? */
1133 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1134 bne+ ext_interrupt_to_host
1135
1136 /* External interrupt, first check for host_ipi. If this is
1137 * set, we know the host wants us out so let's do it now
1138 */
1139 bl kvmppc_read_intr
1140 cmpdi r3, 0
1141 bgt ext_interrupt_to_host
1142
1143 /* Check if any CPU is heading out to the host, if so head out too */
1144 ld r5, HSTATE_KVM_VCORE(r13)
1145 lwz r0, VCORE_ENTRY_EXIT(r5)
1146 cmpwi r0, 0x100
1147 bge ext_interrupt_to_host
1148
1149 /* Return to guest after delivering any pending interrupt */
1150 mr r4, r9
1151 b deliver_guest_interrupt
1152
1153 ext_interrupt_to_host:
1154
1155 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1156 /* Save more register state */
1157 mfdar r6
1158 mfdsisr r7
1159 std r6, VCPU_DAR(r9)
1160 stw r7, VCPU_DSISR(r9)
1161 BEGIN_FTR_SECTION
1162 /* don't overwrite fault_dar/fault_dsisr if HDSI */
1163 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
1164 beq 6f
1165 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1166 std r6, VCPU_FAULT_DAR(r9)
1167 stw r7, VCPU_FAULT_DSISR(r9)
1168
1169 /* See if it is a machine check */
1170 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1171 beq machine_check_realmode
1172 mc_cont:
1173
1174 /* Save guest CTRL register, set runlatch to 1 */
1175 6: mfspr r6,SPRN_CTRLF
1176 stw r6,VCPU_CTRL(r9)
1177 andi. r0,r6,1
1178 bne 4f
1179 ori r6,r6,1
1180 mtspr SPRN_CTRLT,r6
1181 4:
1182 /* Read the guest SLB and save it away */
1183 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1184 mtctr r0
1185 li r6,0
1186 addi r7,r9,VCPU_SLB
1187 li r5,0
1188 1: slbmfee r8,r6
1189 andis. r0,r8,SLB_ESID_V@h
1190 beq 2f
1191 add r8,r8,r6 /* put index in */
1192 slbmfev r3,r6
1193 std r8,VCPU_SLB_E(r7)
1194 std r3,VCPU_SLB_V(r7)
1195 addi r7,r7,VCPU_SLB_SIZE
1196 addi r5,r5,1
1197 2: addi r6,r6,1
1198 bdnz 1b
1199 stw r5,VCPU_SLB_MAX(r9)
1200
1201 /*
1202 * Save the guest PURR/SPURR
1203 */
1204 BEGIN_FTR_SECTION
1205 mfspr r5,SPRN_PURR
1206 mfspr r6,SPRN_SPURR
1207 ld r7,VCPU_PURR(r9)
1208 ld r8,VCPU_SPURR(r9)
1209 std r5,VCPU_PURR(r9)
1210 std r6,VCPU_SPURR(r9)
1211 subf r5,r7,r5
1212 subf r6,r8,r6
1213
1214 /*
1215 * Restore host PURR/SPURR and add guest times
1216 * so that the time in the guest gets accounted.
1217 */
1218 ld r3,HSTATE_PURR(r13)
1219 ld r4,HSTATE_SPURR(r13)
1220 add r3,r3,r5
1221 add r4,r4,r6
1222 mtspr SPRN_PURR,r3
1223 mtspr SPRN_SPURR,r4
1224 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
1225
1226 /* Save DEC */
1227 mfspr r5,SPRN_DEC
1228 mftb r6
1229 extsw r5,r5
1230 add r5,r5,r6
1231 /* r5 is a guest timebase value here, convert to host TB */
1232 ld r3,HSTATE_KVM_VCORE(r13)
1233 ld r4,VCORE_TB_OFFSET(r3)
1234 subf r5,r4,r5
1235 std r5,VCPU_DEC_EXPIRES(r9)
1236
1237 BEGIN_FTR_SECTION
1238 b 8f
1239 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1240 /* Save POWER8-specific registers */
1241 mfspr r5, SPRN_IAMR
1242 mfspr r6, SPRN_PSPB
1243 mfspr r7, SPRN_FSCR
1244 std r5, VCPU_IAMR(r9)
1245 stw r6, VCPU_PSPB(r9)
1246 std r7, VCPU_FSCR(r9)
1247 mfspr r5, SPRN_IC
1248 mfspr r6, SPRN_VTB
1249 mfspr r7, SPRN_TAR
1250 std r5, VCPU_IC(r9)
1251 std r6, VCPU_VTB(r9)
1252 std r7, VCPU_TAR(r9)
1253 mfspr r8, SPRN_EBBHR
1254 std r8, VCPU_EBBHR(r9)
1255 mfspr r5, SPRN_EBBRR
1256 mfspr r6, SPRN_BESCR
1257 mfspr r7, SPRN_CSIGR
1258 mfspr r8, SPRN_TACR
1259 std r5, VCPU_EBBRR(r9)
1260 std r6, VCPU_BESCR(r9)
1261 std r7, VCPU_CSIGR(r9)
1262 std r8, VCPU_TACR(r9)
1263 mfspr r5, SPRN_TCSCR
1264 mfspr r6, SPRN_ACOP
1265 mfspr r7, SPRN_PID
1266 mfspr r8, SPRN_WORT
1267 std r5, VCPU_TCSCR(r9)
1268 std r6, VCPU_ACOP(r9)
1269 stw r7, VCPU_GUEST_PID(r9)
1270 std r8, VCPU_WORT(r9)
1271 8:
1272
1273 /* Save and reset AMR and UAMOR before turning on the MMU */
1274 BEGIN_FTR_SECTION
1275 mfspr r5,SPRN_AMR
1276 mfspr r6,SPRN_UAMOR
1277 std r5,VCPU_AMR(r9)
1278 std r6,VCPU_UAMOR(r9)
1279 li r6,0
1280 mtspr SPRN_AMR,r6
1281 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1282
1283 /* Switch DSCR back to host value */
1284 BEGIN_FTR_SECTION
1285 mfspr r8, SPRN_DSCR
1286 ld r7, HSTATE_DSCR(r13)
1287 std r8, VCPU_DSCR(r9)
1288 mtspr SPRN_DSCR, r7
1289 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1290
1291 /* Save non-volatile GPRs */
1292 std r14, VCPU_GPR(R14)(r9)
1293 std r15, VCPU_GPR(R15)(r9)
1294 std r16, VCPU_GPR(R16)(r9)
1295 std r17, VCPU_GPR(R17)(r9)
1296 std r18, VCPU_GPR(R18)(r9)
1297 std r19, VCPU_GPR(R19)(r9)
1298 std r20, VCPU_GPR(R20)(r9)
1299 std r21, VCPU_GPR(R21)(r9)
1300 std r22, VCPU_GPR(R22)(r9)
1301 std r23, VCPU_GPR(R23)(r9)
1302 std r24, VCPU_GPR(R24)(r9)
1303 std r25, VCPU_GPR(R25)(r9)
1304 std r26, VCPU_GPR(R26)(r9)
1305 std r27, VCPU_GPR(R27)(r9)
1306 std r28, VCPU_GPR(R28)(r9)
1307 std r29, VCPU_GPR(R29)(r9)
1308 std r30, VCPU_GPR(R30)(r9)
1309 std r31, VCPU_GPR(R31)(r9)
1310
1311 /* Save SPRGs */
1312 mfspr r3, SPRN_SPRG0
1313 mfspr r4, SPRN_SPRG1
1314 mfspr r5, SPRN_SPRG2
1315 mfspr r6, SPRN_SPRG3
1316 std r3, VCPU_SPRG0(r9)
1317 std r4, VCPU_SPRG1(r9)
1318 std r5, VCPU_SPRG2(r9)
1319 std r6, VCPU_SPRG3(r9)
1320
1321 /* save FP state */
1322 mr r3, r9
1323 bl kvmppc_save_fp
1324
1325 /* Increment yield count if they have a VPA */
1326 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1327 cmpdi r8, 0
1328 beq 25f
1329 lwz r3, LPPACA_YIELDCOUNT(r8)
1330 addi r3, r3, 1
1331 stw r3, LPPACA_YIELDCOUNT(r8)
1332 li r3, 1
1333 stb r3, VCPU_VPA_DIRTY(r9)
1334 25:
1335 /* Save PMU registers if requested */
1336 /* r8 and cr0.eq are live here */
1337 li r3, 1
1338 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1339 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1340 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1341 mfspr r6, SPRN_MMCRA
1342 BEGIN_FTR_SECTION
1343 /* On P7, clear MMCRA in order to disable SDAR updates */
1344 li r7, 0
1345 mtspr SPRN_MMCRA, r7
1346 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1347 isync
1348 beq 21f /* if no VPA, save PMU stuff anyway */
1349 lbz r7, LPPACA_PMCINUSE(r8)
1350 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1351 bne 21f
1352 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1353 b 22f
1354 21: mfspr r5, SPRN_MMCR1
1355 mfspr r7, SPRN_SIAR
1356 mfspr r8, SPRN_SDAR
1357 std r4, VCPU_MMCR(r9)
1358 std r5, VCPU_MMCR + 8(r9)
1359 std r6, VCPU_MMCR + 16(r9)
1360 std r7, VCPU_SIAR(r9)
1361 std r8, VCPU_SDAR(r9)
1362 mfspr r3, SPRN_PMC1
1363 mfspr r4, SPRN_PMC2
1364 mfspr r5, SPRN_PMC3
1365 mfspr r6, SPRN_PMC4
1366 mfspr r7, SPRN_PMC5
1367 mfspr r8, SPRN_PMC6
1368 BEGIN_FTR_SECTION
1369 mfspr r10, SPRN_PMC7
1370 mfspr r11, SPRN_PMC8
1371 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1372 stw r3, VCPU_PMC(r9)
1373 stw r4, VCPU_PMC + 4(r9)
1374 stw r5, VCPU_PMC + 8(r9)
1375 stw r6, VCPU_PMC + 12(r9)
1376 stw r7, VCPU_PMC + 16(r9)
1377 stw r8, VCPU_PMC + 20(r9)
1378 BEGIN_FTR_SECTION
1379 stw r10, VCPU_PMC + 24(r9)
1380 stw r11, VCPU_PMC + 28(r9)
1381 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1382 BEGIN_FTR_SECTION
1383 mfspr r4, SPRN_MMCR2
1384 mfspr r5, SPRN_SIER
1385 mfspr r6, SPRN_SPMC1
1386 mfspr r7, SPRN_SPMC2
1387 mfspr r8, SPRN_MMCRS
1388 std r4, VCPU_MMCR + 24(r9)
1389 std r5, VCPU_SIER(r9)
1390 stw r6, VCPU_PMC + 24(r9)
1391 stw r7, VCPU_PMC + 28(r9)
1392 std r8, VCPU_MMCR + 32(r9)
1393 lis r4, 0x8000
1394 mtspr SPRN_MMCRS, r4
1395 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1396 22:
1397 /* Clear out SLB */
1398 li r5,0
1399 slbmte r5,r5
1400 slbia
1401 ptesync
1402
1403 hdec_soon: /* r12 = trap, r13 = paca */
1404 BEGIN_FTR_SECTION
1405 b 32f
1406 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1407 /*
1408 * POWER7 guest -> host partition switch code.
1409 * We don't have to lock against tlbies but we do
1410 * have to coordinate the hardware threads.
1411 */
1412 /* Increment the threads-exiting-guest count in the 0xff00
1413 bits of vcore->entry_exit_count */
1414 ld r5,HSTATE_KVM_VCORE(r13)
1415 addi r6,r5,VCORE_ENTRY_EXIT
1416 41: lwarx r3,0,r6
1417 addi r0,r3,0x100
1418 stwcx. r0,0,r6
1419 bne 41b
1420 isync /* order stwcx. vs. reading napping_threads */
1421
1422 /*
1423 * At this point we have an interrupt that we have to pass
1424 * up to the kernel or qemu; we can't handle it in real mode.
1425 * Thus we have to do a partition switch, so we have to
1426 * collect the other threads, if we are the first thread
1427 * to take an interrupt. To do this, we set the HDEC to 0,
1428 * which causes an HDEC interrupt in all threads within 2ns
1429 * because the HDEC register is shared between all 4 threads.
1430 * However, we don't need to bother if this is an HDEC
1431 * interrupt, since the other threads will already be on their
1432 * way here in that case.
1433 */
1434 cmpwi r3,0x100 /* Are we the first here? */
1435 bge 43f
1436 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1437 beq 40f
1438 li r0,0
1439 mtspr SPRN_HDEC,r0
1440 40:
1441 /*
1442 * Send an IPI to any napping threads, since an HDEC interrupt
1443 * doesn't wake CPUs up from nap.
1444 */
1445 lwz r3,VCORE_NAPPING_THREADS(r5)
1446 lbz r4,HSTATE_PTID(r13)
1447 li r0,1
1448 sld r0,r0,r4
1449 andc. r3,r3,r0 /* no sense IPI'ing ourselves */
1450 beq 43f
1451 /* Order entry/exit update vs. IPIs */
1452 sync
1453 mulli r4,r4,PACA_SIZE /* get paca for thread 0 */
1454 subf r6,r4,r13
1455 42: andi. r0,r3,1
1456 beq 44f
1457 ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */
1458 li r0,IPI_PRIORITY
1459 li r7,XICS_MFRR
1460 stbcix r0,r7,r8 /* trigger the IPI */
1461 44: srdi. r3,r3,1
1462 addi r6,r6,PACA_SIZE
1463 bne 42b
1464
1465 secondary_too_late:
1466 /* Secondary threads wait for primary to do partition switch */
1467 43: ld r5,HSTATE_KVM_VCORE(r13)
1468 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1469 lbz r3,HSTATE_PTID(r13)
1470 cmpwi r3,0
1471 beq 15f
1472 HMT_LOW
1473 13: lbz r3,VCORE_IN_GUEST(r5)
1474 cmpwi r3,0
1475 bne 13b
1476 HMT_MEDIUM
1477 b 16f
1478
1479 /* Primary thread waits for all the secondaries to exit guest */
1480 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1481 srwi r0,r3,8
1482 clrldi r3,r3,56
1483 cmpw r3,r0
1484 bne 15b
1485 isync
1486
1487 /* Primary thread switches back to host partition */
1488 ld r6,KVM_HOST_SDR1(r4)
1489 lwz r7,KVM_HOST_LPID(r4)
1490 li r8,LPID_RSVD /* switch to reserved LPID */
1491 mtspr SPRN_LPID,r8
1492 ptesync
1493 mtspr SPRN_SDR1,r6 /* switch to partition page table */
1494 mtspr SPRN_LPID,r7
1495 isync
1496
1497 BEGIN_FTR_SECTION
1498 /* DPDES is shared between threads */
1499 mfspr r7, SPRN_DPDES
1500 std r7, VCORE_DPDES(r5)
1501 /* clear DPDES so we don't get guest doorbells in the host */
1502 li r8, 0
1503 mtspr SPRN_DPDES, r8
1504 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1505
1506 /* Subtract timebase offset from timebase */
1507 ld r8,VCORE_TB_OFFSET(r5)
1508 cmpdi r8,0
1509 beq 17f
1510 mftb r6 /* current guest timebase */
1511 subf r8,r8,r6
1512 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1513 mftb r7 /* check if lower 24 bits overflowed */
1514 clrldi r6,r6,40
1515 clrldi r7,r7,40
1516 cmpld r7,r6
1517 bge 17f
1518 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1519 mtspr SPRN_TBU40,r8
1520
1521 /* Reset PCR */
1522 17: ld r0, VCORE_PCR(r5)
1523 cmpdi r0, 0
1524 beq 18f
1525 li r0, 0
1526 mtspr SPRN_PCR, r0
1527 18:
1528 /* Signal secondary CPUs to continue */
1529 stb r0,VCORE_IN_GUEST(r5)
1530 lis r8,0x7fff /* MAX_INT@h */
1531 mtspr SPRN_HDEC,r8
1532
1533 16: ld r8,KVM_HOST_LPCR(r4)
1534 mtspr SPRN_LPCR,r8
1535 isync
1536 b 33f
1537
1538 /*
1539 * PPC970 guest -> host partition switch code.
1540 * We have to lock against concurrent tlbies, and
1541 * we have to flush the whole TLB.
1542 */
1543 32: ld r5,HSTATE_KVM_VCORE(r13)
1544 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1545
1546 /* Take the guest's tlbie_lock */
1547 #ifdef __BIG_ENDIAN__
1548 lwz r8,PACA_LOCK_TOKEN(r13)
1549 #else
1550 lwz r8,PACAPACAINDEX(r13)
1551 #endif
1552 addi r3,r4,KVM_TLBIE_LOCK
1553 24: lwarx r0,0,r3
1554 cmpwi r0,0
1555 bne 24b
1556 stwcx. r8,0,r3
1557 bne 24b
1558 isync
1559
1560 ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */
1561 li r0,0x18f
1562 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
1563 or r0,r7,r0
1564 ptesync
1565 sync
1566 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
1567 isync
1568 li r0,0
1569 stw r0,0(r3) /* drop guest tlbie_lock */
1570
1571 /* invalidate the whole TLB */
1572 li r0,256
1573 mtctr r0
1574 li r6,0
1575 25: tlbiel r6
1576 addi r6,r6,0x1000
1577 bdnz 25b
1578 ptesync
1579
1580 /* take native_tlbie_lock */
1581 ld r3,toc_tlbie_lock@toc(2)
1582 24: lwarx r0,0,r3
1583 cmpwi r0,0
1584 bne 24b
1585 stwcx. r8,0,r3
1586 bne 24b
1587 isync
1588
1589 ld r6,KVM_HOST_SDR1(r4)
1590 mtspr SPRN_SDR1,r6 /* switch to host page table */
1591
1592 /* Set up host HID4 value */
1593 sync
1594 mtspr SPRN_HID4,r7
1595 isync
1596 li r0,0
1597 stw r0,0(r3) /* drop native_tlbie_lock */
1598
1599 lis r8,0x7fff /* MAX_INT@h */
1600 mtspr SPRN_HDEC,r8
1601
1602 /* Disable HDEC interrupts */
1603 mfspr r0,SPRN_HID0
1604 li r3,0
1605 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
1606 sync
1607 mtspr SPRN_HID0,r0
1608 mfspr r0,SPRN_HID0
1609 mfspr r0,SPRN_HID0
1610 mfspr r0,SPRN_HID0
1611 mfspr r0,SPRN_HID0
1612 mfspr r0,SPRN_HID0
1613 mfspr r0,SPRN_HID0
1614
1615 /* load host SLB entries */
1616 33: ld r8,PACA_SLBSHADOWPTR(r13)
1617
1618 .rept SLB_NUM_BOLTED
1619 ld r5,SLBSHADOW_SAVEAREA(r8)
1620 ld r6,SLBSHADOW_SAVEAREA+8(r8)
1621 andis. r7,r5,SLB_ESID_V@h
1622 beq 1f
1623 slbmte r6,r5
1624 1: addi r8,r8,16
1625 .endr
1626
1627 /* Unset guest mode */
1628 li r0, KVM_GUEST_MODE_NONE
1629 stb r0, HSTATE_IN_GUEST(r13)
1630
1631 ld r0, 112+PPC_LR_STKOFF(r1)
1632 addi r1, r1, 112
1633 mtlr r0
1634 blr
1635
1636 /*
1637 * Check whether an HDSI is an HPTE not found fault or something else.
1638 * If it is an HPTE not found fault that is due to the guest accessing
1639 * a page that they have mapped but which we have paged out, then
1640 * we continue on with the guest exit path. In all other cases,
1641 * reflect the HDSI to the guest as a DSI.
1642 */
1643 kvmppc_hdsi:
1644 mfspr r4, SPRN_HDAR
1645 mfspr r6, SPRN_HDSISR
1646 /* HPTE not found fault or protection fault? */
1647 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1648 beq 1f /* if not, send it to the guest */
1649 andi. r0, r11, MSR_DR /* data relocation enabled? */
1650 beq 3f
1651 clrrdi r0, r4, 28
1652 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1653 bne 1f /* if no SLB entry found */
1654 4: std r4, VCPU_FAULT_DAR(r9)
1655 stw r6, VCPU_FAULT_DSISR(r9)
1656
1657 /* Search the hash table. */
1658 mr r3, r9 /* vcpu pointer */
1659 li r7, 1 /* data fault */
1660 bl kvmppc_hpte_hv_fault
1661 ld r9, HSTATE_KVM_VCPU(r13)
1662 ld r10, VCPU_PC(r9)
1663 ld r11, VCPU_MSR(r9)
1664 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1665 cmpdi r3, 0 /* retry the instruction */
1666 beq 6f
1667 cmpdi r3, -1 /* handle in kernel mode */
1668 beq guest_exit_cont
1669 cmpdi r3, -2 /* MMIO emulation; need instr word */
1670 beq 2f
1671
1672 /* Synthesize a DSI for the guest */
1673 ld r4, VCPU_FAULT_DAR(r9)
1674 mr r6, r3
1675 1: mtspr SPRN_DAR, r4
1676 mtspr SPRN_DSISR, r6
1677 mtspr SPRN_SRR0, r10
1678 mtspr SPRN_SRR1, r11
1679 li r10, BOOK3S_INTERRUPT_DATA_STORAGE
1680 bl kvmppc_msr_interrupt
1681 fast_interrupt_c_return:
1682 6: ld r7, VCPU_CTR(r9)
1683 lwz r8, VCPU_XER(r9)
1684 mtctr r7
1685 mtxer r8
1686 mr r4, r9
1687 b fast_guest_return
1688
1689 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1690 ld r5, KVM_VRMA_SLB_V(r5)
1691 b 4b
1692
1693 /* If this is for emulated MMIO, load the instruction word */
1694 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1695
1696 /* Set guest mode to 'jump over instruction' so if lwz faults
1697 * we'll just continue at the next IP. */
1698 li r0, KVM_GUEST_MODE_SKIP
1699 stb r0, HSTATE_IN_GUEST(r13)
1700
1701 /* Do the access with MSR:DR enabled */
1702 mfmsr r3
1703 ori r4, r3, MSR_DR /* Enable paging for data */
1704 mtmsrd r4
1705 lwz r8, 0(r10)
1706 mtmsrd r3
1707
1708 /* Store the result */
1709 stw r8, VCPU_LAST_INST(r9)
1710
1711 /* Unset guest mode. */
1712 li r0, KVM_GUEST_MODE_HOST_HV
1713 stb r0, HSTATE_IN_GUEST(r13)
1714 b guest_exit_cont
1715
1716 /*
1717 * Similarly for an HISI, reflect it to the guest as an ISI unless
1718 * it is an HPTE not found fault for a page that we have paged out.
1719 */
1720 kvmppc_hisi:
1721 andis. r0, r11, SRR1_ISI_NOPT@h
1722 beq 1f
1723 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1724 beq 3f
1725 clrrdi r0, r10, 28
1726 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1727 bne 1f /* if no SLB entry found */
1728 4:
1729 /* Search the hash table. */
1730 mr r3, r9 /* vcpu pointer */
1731 mr r4, r10
1732 mr r6, r11
1733 li r7, 0 /* instruction fault */
1734 bl kvmppc_hpte_hv_fault
1735 ld r9, HSTATE_KVM_VCPU(r13)
1736 ld r10, VCPU_PC(r9)
1737 ld r11, VCPU_MSR(r9)
1738 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1739 cmpdi r3, 0 /* retry the instruction */
1740 beq fast_interrupt_c_return
1741 cmpdi r3, -1 /* handle in kernel mode */
1742 beq guest_exit_cont
1743
1744 /* Synthesize an ISI for the guest */
1745 mr r11, r3
1746 1: mtspr SPRN_SRR0, r10
1747 mtspr SPRN_SRR1, r11
1748 li r10, BOOK3S_INTERRUPT_INST_STORAGE
1749 bl kvmppc_msr_interrupt
1750 b fast_interrupt_c_return
1751
1752 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1753 ld r5, KVM_VRMA_SLB_V(r6)
1754 b 4b
1755
1756 /*
1757 * Try to handle an hcall in real mode.
1758 * Returns to the guest if we handle it, or continues on up to
1759 * the kernel if we can't (i.e. if we don't have a handler for
1760 * it, or if the handler returns H_TOO_HARD).
1761 */
1762 .globl hcall_try_real_mode
1763 hcall_try_real_mode:
1764 ld r3,VCPU_GPR(R3)(r9)
1765 andi. r0,r11,MSR_PR
1766 /* sc 1 from userspace - reflect to guest syscall */
1767 bne sc_1_fast_return
1768 clrrdi r3,r3,2
1769 cmpldi r3,hcall_real_table_end - hcall_real_table
1770 bge guest_exit_cont
1771 LOAD_REG_ADDR(r4, hcall_real_table)
1772 lwax r3,r3,r4
1773 cmpwi r3,0
1774 beq guest_exit_cont
1775 add r3,r3,r4
1776 mtctr r3
1777 mr r3,r9 /* get vcpu pointer */
1778 ld r4,VCPU_GPR(R4)(r9)
1779 bctrl
1780 cmpdi r3,H_TOO_HARD
1781 beq hcall_real_fallback
1782 ld r4,HSTATE_KVM_VCPU(r13)
1783 std r3,VCPU_GPR(R3)(r4)
1784 ld r10,VCPU_PC(r4)
1785 ld r11,VCPU_MSR(r4)
1786 b fast_guest_return
1787
1788 sc_1_fast_return:
1789 mtspr SPRN_SRR0,r10
1790 mtspr SPRN_SRR1,r11
1791 li r10, BOOK3S_INTERRUPT_SYSCALL
1792 bl kvmppc_msr_interrupt
1793 mr r4,r9
1794 b fast_guest_return
1795
1796 /* We've attempted a real mode hcall, but it's punted it back
1797 * to userspace. We need to restore some clobbered volatiles
1798 * before resuming the pass-it-to-qemu path */
1799 hcall_real_fallback:
1800 li r12,BOOK3S_INTERRUPT_SYSCALL
1801 ld r9, HSTATE_KVM_VCPU(r13)
1802
1803 b guest_exit_cont
1804
1805 .globl hcall_real_table
1806 hcall_real_table:
1807 .long 0 /* 0 - unused */
1808 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
1809 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
1810 .long DOTSYM(kvmppc_h_read) - hcall_real_table
1811 .long 0 /* 0x10 - H_CLEAR_MOD */
1812 .long 0 /* 0x14 - H_CLEAR_REF */
1813 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
1814 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
1815 .long DOTSYM(kvmppc_h_put_tce) - hcall_real_table
1816 .long 0 /* 0x24 - H_SET_SPRG0 */
1817 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
1818 .long 0 /* 0x2c */
1819 .long 0 /* 0x30 */
1820 .long 0 /* 0x34 */
1821 .long 0 /* 0x38 */
1822 .long 0 /* 0x3c */
1823 .long 0 /* 0x40 */
1824 .long 0 /* 0x44 */
1825 .long 0 /* 0x48 */
1826 .long 0 /* 0x4c */
1827 .long 0 /* 0x50 */
1828 .long 0 /* 0x54 */
1829 .long 0 /* 0x58 */
1830 .long 0 /* 0x5c */
1831 .long 0 /* 0x60 */
1832 #ifdef CONFIG_KVM_XICS
1833 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
1834 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
1835 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
1836 .long 0 /* 0x70 - H_IPOLL */
1837 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
1838 #else
1839 .long 0 /* 0x64 - H_EOI */
1840 .long 0 /* 0x68 - H_CPPR */
1841 .long 0 /* 0x6c - H_IPI */
1842 .long 0 /* 0x70 - H_IPOLL */
1843 .long 0 /* 0x74 - H_XIRR */
1844 #endif
1845 .long 0 /* 0x78 */
1846 .long 0 /* 0x7c */
1847 .long 0 /* 0x80 */
1848 .long 0 /* 0x84 */
1849 .long 0 /* 0x88 */
1850 .long 0 /* 0x8c */
1851 .long 0 /* 0x90 */
1852 .long 0 /* 0x94 */
1853 .long 0 /* 0x98 */
1854 .long 0 /* 0x9c */
1855 .long 0 /* 0xa0 */
1856 .long 0 /* 0xa4 */
1857 .long 0 /* 0xa8 */
1858 .long 0 /* 0xac */
1859 .long 0 /* 0xb0 */
1860 .long 0 /* 0xb4 */
1861 .long 0 /* 0xb8 */
1862 .long 0 /* 0xbc */
1863 .long 0 /* 0xc0 */
1864 .long 0 /* 0xc4 */
1865 .long 0 /* 0xc8 */
1866 .long 0 /* 0xcc */
1867 .long 0 /* 0xd0 */
1868 .long 0 /* 0xd4 */
1869 .long 0 /* 0xd8 */
1870 .long 0 /* 0xdc */
1871 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
1872 .long 0 /* 0xe4 */
1873 .long 0 /* 0xe8 */
1874 .long 0 /* 0xec */
1875 .long 0 /* 0xf0 */
1876 .long 0 /* 0xf4 */
1877 .long 0 /* 0xf8 */
1878 .long 0 /* 0xfc */
1879 .long 0 /* 0x100 */
1880 .long 0 /* 0x104 */
1881 .long 0 /* 0x108 */
1882 .long 0 /* 0x10c */
1883 .long 0 /* 0x110 */
1884 .long 0 /* 0x114 */
1885 .long 0 /* 0x118 */
1886 .long 0 /* 0x11c */
1887 .long 0 /* 0x120 */
1888 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
1889 .long 0 /* 0x128 */
1890 .long 0 /* 0x12c */
1891 .long 0 /* 0x130 */
1892 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
1893 hcall_real_table_end:
1894
1895 ignore_hdec:
1896 mr r4,r9
1897 b fast_guest_return
1898
1899 _GLOBAL(kvmppc_h_set_xdabr)
1900 andi. r0, r5, DABRX_USER | DABRX_KERNEL
1901 beq 6f
1902 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
1903 andc. r0, r5, r0
1904 beq 3f
1905 6: li r3, H_PARAMETER
1906 blr
1907
1908 _GLOBAL(kvmppc_h_set_dabr)
1909 li r5, DABRX_USER | DABRX_KERNEL
1910 3:
1911 BEGIN_FTR_SECTION
1912 b 2f
1913 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1914 std r4,VCPU_DABR(r3)
1915 stw r5, VCPU_DABRX(r3)
1916 mtspr SPRN_DABRX, r5
1917 /* Work around P7 bug where DABR can get corrupted on mtspr */
1918 1: mtspr SPRN_DABR,r4
1919 mfspr r5, SPRN_DABR
1920 cmpd r4, r5
1921 bne 1b
1922 isync
1923 li r3,0
1924 blr
1925
1926 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
1927 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
1928 rlwimi r5, r4, 1, DAWRX_WT
1929 clrrdi r4, r4, 3
1930 std r4, VCPU_DAWR(r3)
1931 std r5, VCPU_DAWRX(r3)
1932 mtspr SPRN_DAWR, r4
1933 mtspr SPRN_DAWRX, r5
1934 li r3, 0
1935 blr
1936
1937 _GLOBAL(kvmppc_h_cede)
1938 ori r11,r11,MSR_EE
1939 std r11,VCPU_MSR(r3)
1940 li r0,1
1941 stb r0,VCPU_CEDED(r3)
1942 sync /* order setting ceded vs. testing prodded */
1943 lbz r5,VCPU_PRODDED(r3)
1944 cmpwi r5,0
1945 bne kvm_cede_prodded
1946 li r0,0 /* set trap to 0 to say hcall is handled */
1947 stw r0,VCPU_TRAP(r3)
1948 li r0,H_SUCCESS
1949 std r0,VCPU_GPR(R3)(r3)
1950 BEGIN_FTR_SECTION
1951 b kvm_cede_exit /* just send it up to host on 970 */
1952 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1953
1954 /*
1955 * Set our bit in the bitmask of napping threads unless all the
1956 * other threads are already napping, in which case we send this
1957 * up to the host.
1958 */
1959 ld r5,HSTATE_KVM_VCORE(r13)
1960 lbz r6,HSTATE_PTID(r13)
1961 lwz r8,VCORE_ENTRY_EXIT(r5)
1962 clrldi r8,r8,56
1963 li r0,1
1964 sld r0,r0,r6
1965 addi r6,r5,VCORE_NAPPING_THREADS
1966 31: lwarx r4,0,r6
1967 or r4,r4,r0
1968 PPC_POPCNTW(R7,R4)
1969 cmpw r7,r8
1970 bge kvm_cede_exit
1971 stwcx. r4,0,r6
1972 bne 31b
1973 /* order napping_threads update vs testing entry_exit_count */
1974 isync
1975 li r0,NAPPING_CEDE
1976 stb r0,HSTATE_NAPPING(r13)
1977 lwz r7,VCORE_ENTRY_EXIT(r5)
1978 cmpwi r7,0x100
1979 bge 33f /* another thread already exiting */
1980
1981 /*
1982 * Although not specifically required by the architecture, POWER7
1983 * preserves the following registers in nap mode, even if an SMT mode
1984 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
1985 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
1986 */
1987 /* Save non-volatile GPRs */
1988 std r14, VCPU_GPR(R14)(r3)
1989 std r15, VCPU_GPR(R15)(r3)
1990 std r16, VCPU_GPR(R16)(r3)
1991 std r17, VCPU_GPR(R17)(r3)
1992 std r18, VCPU_GPR(R18)(r3)
1993 std r19, VCPU_GPR(R19)(r3)
1994 std r20, VCPU_GPR(R20)(r3)
1995 std r21, VCPU_GPR(R21)(r3)
1996 std r22, VCPU_GPR(R22)(r3)
1997 std r23, VCPU_GPR(R23)(r3)
1998 std r24, VCPU_GPR(R24)(r3)
1999 std r25, VCPU_GPR(R25)(r3)
2000 std r26, VCPU_GPR(R26)(r3)
2001 std r27, VCPU_GPR(R27)(r3)
2002 std r28, VCPU_GPR(R28)(r3)
2003 std r29, VCPU_GPR(R29)(r3)
2004 std r30, VCPU_GPR(R30)(r3)
2005 std r31, VCPU_GPR(R31)(r3)
2006
2007 /* save FP state */
2008 bl kvmppc_save_fp
2009
2010 /*
2011 * Take a nap until a decrementer or external or doobell interrupt
2012 * occurs, with PECE1, PECE0 and PECEDP set in LPCR. Also clear the
2013 * runlatch bit before napping.
2014 */
2015 mfspr r2, SPRN_CTRLF
2016 clrrdi r2, r2, 1
2017 mtspr SPRN_CTRLT, r2
2018
2019 li r0,1
2020 stb r0,HSTATE_HWTHREAD_REQ(r13)
2021 mfspr r5,SPRN_LPCR
2022 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2023 BEGIN_FTR_SECTION
2024 oris r5,r5,LPCR_PECEDP@h
2025 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2026 mtspr SPRN_LPCR,r5
2027 isync
2028 li r0, 0
2029 std r0, HSTATE_SCRATCH0(r13)
2030 ptesync
2031 ld r0, HSTATE_SCRATCH0(r13)
2032 1: cmpd r0, r0
2033 bne 1b
2034 nap
2035 b .
2036
2037 33: mr r4, r3
2038 li r3, 0
2039 li r12, 0
2040 b 34f
2041
2042 kvm_end_cede:
2043 /* get vcpu pointer */
2044 ld r4, HSTATE_KVM_VCPU(r13)
2045
2046 /* Woken by external or decrementer interrupt */
2047 ld r1, HSTATE_HOST_R1(r13)
2048
2049 /* load up FP state */
2050 bl kvmppc_load_fp
2051
2052 /* Load NV GPRS */
2053 ld r14, VCPU_GPR(R14)(r4)
2054 ld r15, VCPU_GPR(R15)(r4)
2055 ld r16, VCPU_GPR(R16)(r4)
2056 ld r17, VCPU_GPR(R17)(r4)
2057 ld r18, VCPU_GPR(R18)(r4)
2058 ld r19, VCPU_GPR(R19)(r4)
2059 ld r20, VCPU_GPR(R20)(r4)
2060 ld r21, VCPU_GPR(R21)(r4)
2061 ld r22, VCPU_GPR(R22)(r4)
2062 ld r23, VCPU_GPR(R23)(r4)
2063 ld r24, VCPU_GPR(R24)(r4)
2064 ld r25, VCPU_GPR(R25)(r4)
2065 ld r26, VCPU_GPR(R26)(r4)
2066 ld r27, VCPU_GPR(R27)(r4)
2067 ld r28, VCPU_GPR(R28)(r4)
2068 ld r29, VCPU_GPR(R29)(r4)
2069 ld r30, VCPU_GPR(R30)(r4)
2070 ld r31, VCPU_GPR(R31)(r4)
2071
2072 /* Check the wake reason in SRR1 to see why we got here */
2073 bl kvmppc_check_wake_reason
2074
2075 /* clear our bit in vcore->napping_threads */
2076 34: ld r5,HSTATE_KVM_VCORE(r13)
2077 lbz r7,HSTATE_PTID(r13)
2078 li r0,1
2079 sld r0,r0,r7
2080 addi r6,r5,VCORE_NAPPING_THREADS
2081 32: lwarx r7,0,r6
2082 andc r7,r7,r0
2083 stwcx. r7,0,r6
2084 bne 32b
2085 li r0,0
2086 stb r0,HSTATE_NAPPING(r13)
2087
2088 /* See if the wake reason means we need to exit */
2089 stw r12, VCPU_TRAP(r4)
2090 mr r9, r4
2091 cmpdi r3, 0
2092 bgt guest_exit_cont
2093
2094 /* see if any other thread is already exiting */
2095 lwz r0,VCORE_ENTRY_EXIT(r5)
2096 cmpwi r0,0x100
2097 bge guest_exit_cont
2098
2099 b kvmppc_cede_reentry /* if not go back to guest */
2100
2101 /* cede when already previously prodded case */
2102 kvm_cede_prodded:
2103 li r0,0
2104 stb r0,VCPU_PRODDED(r3)
2105 sync /* order testing prodded vs. clearing ceded */
2106 stb r0,VCPU_CEDED(r3)
2107 li r3,H_SUCCESS
2108 blr
2109
2110 /* we've ceded but we want to give control to the host */
2111 kvm_cede_exit:
2112 b hcall_real_fallback
2113
2114 /* Try to handle a machine check in real mode */
2115 machine_check_realmode:
2116 mr r3, r9 /* get vcpu pointer */
2117 bl kvmppc_realmode_machine_check
2118 nop
2119 cmpdi r3, 0 /* continue exiting from guest? */
2120 ld r9, HSTATE_KVM_VCPU(r13)
2121 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2122 beq mc_cont
2123 /* If not, deliver a machine check. SRR0/1 are already set */
2124 li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
2125 bl kvmppc_msr_interrupt
2126 b fast_interrupt_c_return
2127
2128 /*
2129 * Check the reason we woke from nap, and take appropriate action.
2130 * Returns:
2131 * 0 if nothing needs to be done
2132 * 1 if something happened that needs to be handled by the host
2133 * -1 if there was a guest wakeup (IPI)
2134 *
2135 * Also sets r12 to the interrupt vector for any interrupt that needs
2136 * to be handled now by the host (0x500 for external interrupt), or zero.
2137 */
2138 kvmppc_check_wake_reason:
2139 mfspr r6, SPRN_SRR1
2140 BEGIN_FTR_SECTION
2141 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2142 FTR_SECTION_ELSE
2143 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2144 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2145 cmpwi r6, 8 /* was it an external interrupt? */
2146 li r12, BOOK3S_INTERRUPT_EXTERNAL
2147 beq kvmppc_read_intr /* if so, see what it was */
2148 li r3, 0
2149 li r12, 0
2150 cmpwi r6, 6 /* was it the decrementer? */
2151 beq 0f
2152 BEGIN_FTR_SECTION
2153 cmpwi r6, 5 /* privileged doorbell? */
2154 beq 0f
2155 cmpwi r6, 3 /* hypervisor doorbell? */
2156 beq 3f
2157 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2158 li r3, 1 /* anything else, return 1 */
2159 0: blr
2160
2161 /* hypervisor doorbell */
2162 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2163 li r3, 1
2164 blr
2165
2166 /*
2167 * Determine what sort of external interrupt is pending (if any).
2168 * Returns:
2169 * 0 if no interrupt is pending
2170 * 1 if an interrupt is pending that needs to be handled by the host
2171 * -1 if there was a guest wakeup IPI (which has now been cleared)
2172 */
2173 kvmppc_read_intr:
2174 /* see if a host IPI is pending */
2175 li r3, 1
2176 lbz r0, HSTATE_HOST_IPI(r13)
2177 cmpwi r0, 0
2178 bne 1f
2179
2180 /* Now read the interrupt from the ICP */
2181 ld r6, HSTATE_XICS_PHYS(r13)
2182 li r7, XICS_XIRR
2183 cmpdi r6, 0
2184 beq- 1f
2185 lwzcix r0, r6, r7
2186 rlwinm. r3, r0, 0, 0xffffff
2187 sync
2188 beq 1f /* if nothing pending in the ICP */
2189
2190 /* We found something in the ICP...
2191 *
2192 * If it's not an IPI, stash it in the PACA and return to
2193 * the host, we don't (yet) handle directing real external
2194 * interrupts directly to the guest
2195 */
2196 cmpwi r3, XICS_IPI /* if there is, is it an IPI? */
2197 bne 42f
2198
2199 /* It's an IPI, clear the MFRR and EOI it */
2200 li r3, 0xff
2201 li r8, XICS_MFRR
2202 stbcix r3, r6, r8 /* clear the IPI */
2203 stwcix r0, r6, r7 /* EOI it */
2204 sync
2205
2206 /* We need to re-check host IPI now in case it got set in the
2207 * meantime. If it's clear, we bounce the interrupt to the
2208 * guest
2209 */
2210 lbz r0, HSTATE_HOST_IPI(r13)
2211 cmpwi r0, 0
2212 bne- 43f
2213
2214 /* OK, it's an IPI for us */
2215 li r3, -1
2216 1: blr
2217
2218 42: /* It's not an IPI and it's for the host, stash it in the PACA
2219 * before exit, it will be picked up by the host ICP driver
2220 */
2221 stw r0, HSTATE_SAVED_XIRR(r13)
2222 li r3, 1
2223 b 1b
2224
2225 43: /* We raced with the host, we need to resend that IPI, bummer */
2226 li r0, IPI_PRIORITY
2227 stbcix r0, r6, r8 /* set the IPI */
2228 sync
2229 li r3, 1
2230 b 1b
2231
2232 /*
2233 * Save away FP, VMX and VSX registers.
2234 * r3 = vcpu pointer
2235 * N.B. r30 and r31 are volatile across this function,
2236 * thus it is not callable from C.
2237 */
2238 kvmppc_save_fp:
2239 mflr r30
2240 mr r31,r3
2241 mfmsr r5
2242 ori r8,r5,MSR_FP
2243 #ifdef CONFIG_ALTIVEC
2244 BEGIN_FTR_SECTION
2245 oris r8,r8,MSR_VEC@h
2246 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2247 #endif
2248 #ifdef CONFIG_VSX
2249 BEGIN_FTR_SECTION
2250 oris r8,r8,MSR_VSX@h
2251 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2252 #endif
2253 mtmsrd r8
2254 isync
2255 addi r3,r3,VCPU_FPRS
2256 bl .store_fp_state
2257 #ifdef CONFIG_ALTIVEC
2258 BEGIN_FTR_SECTION
2259 addi r3,r31,VCPU_VRS
2260 bl .store_vr_state
2261 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2262 #endif
2263 mfspr r6,SPRN_VRSAVE
2264 stw r6,VCPU_VRSAVE(r31)
2265 mtlr r30
2266 blr
2267
2268 /*
2269 * Load up FP, VMX and VSX registers
2270 * r4 = vcpu pointer
2271 * N.B. r30 and r31 are volatile across this function,
2272 * thus it is not callable from C.
2273 */
2274 kvmppc_load_fp:
2275 mflr r30
2276 mr r31,r4
2277 mfmsr r9
2278 ori r8,r9,MSR_FP
2279 #ifdef CONFIG_ALTIVEC
2280 BEGIN_FTR_SECTION
2281 oris r8,r8,MSR_VEC@h
2282 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2283 #endif
2284 #ifdef CONFIG_VSX
2285 BEGIN_FTR_SECTION
2286 oris r8,r8,MSR_VSX@h
2287 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2288 #endif
2289 mtmsrd r8
2290 isync
2291 addi r3,r4,VCPU_FPRS
2292 bl .load_fp_state
2293 #ifdef CONFIG_ALTIVEC
2294 BEGIN_FTR_SECTION
2295 addi r3,r31,VCPU_VRS
2296 bl .load_vr_state
2297 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2298 #endif
2299 lwz r7,VCPU_VRSAVE(r31)
2300 mtspr SPRN_VRSAVE,r7
2301 mtlr r30
2302 mr r4,r31
2303 blr
2304
2305 /*
2306 * We come here if we get any exception or interrupt while we are
2307 * executing host real mode code while in guest MMU context.
2308 * For now just spin, but we should do something better.
2309 */
2310 kvmppc_bad_host_intr:
2311 b .
2312
2313 /*
2314 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
2315 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
2316 * r11 has the guest MSR value (in/out)
2317 * r9 has a vcpu pointer (in)
2318 * r0 is used as a scratch register
2319 */
2320 kvmppc_msr_interrupt:
2321 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
2322 cmpwi r0, 2 /* Check if we are in transactional state.. */
2323 ld r11, VCPU_INTR_MSR(r9)
2324 bne 1f
2325 /* ... if transactional, change to suspended */
2326 li r0, 1
2327 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
2328 blr
Linux kernel - Deliverables
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