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Merge tag 'iio-fixes-for-3.14a' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / arch / powerpc / mm / hash_low_64.S
1 /*
2 * ppc64 MMU hashtable management routines
3 *
4 * (c) Copyright IBM Corp. 2003, 2005
5 *
6 * Maintained by: Benjamin Herrenschmidt
7 * <benh@kernel.crashing.org>
8 *
9 * This file is covered by the GNU Public Licence v2 as
10 * described in the kernel's COPYING file.
11 */
12
13 #include <asm/reg.h>
14 #include <asm/pgtable.h>
15 #include <asm/mmu.h>
16 #include <asm/page.h>
17 #include <asm/types.h>
18 #include <asm/ppc_asm.h>
19 #include <asm/asm-offsets.h>
20 #include <asm/cputable.h>
21
22 .text
23
24 /*
25 * Stackframe:
26 *
27 * +-> Back chain (SP + 256)
28 * | General register save area (SP + 112)
29 * | Parameter save area (SP + 48)
30 * | TOC save area (SP + 40)
31 * | link editor doubleword (SP + 32)
32 * | compiler doubleword (SP + 24)
33 * | LR save area (SP + 16)
34 * | CR save area (SP + 8)
35 * SP ---> +-- Back chain (SP + 0)
36 */
37
38 #ifndef CONFIG_PPC_64K_PAGES
39
40 /*****************************************************************************
41 * *
42 * 4K SW & 4K HW pages implementation *
43 * *
44 *****************************************************************************/
45
46
47 /*
48 * _hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,
49 * pte_t *ptep, unsigned long trap, int local, int ssize)
50 *
51 * Adds a 4K page to the hash table in a segment of 4K pages only
52 */
53
54 _GLOBAL(__hash_page_4K)
55 mflr r0
56 std r0,16(r1)
57 stdu r1,-STACKFRAMESIZE(r1)
58 /* Save all params that we need after a function call */
59 std r6,STK_PARAM(R6)(r1)
60 std r8,STK_PARAM(R8)(r1)
61 std r9,STK_PARAM(R9)(r1)
62
63 /* Save non-volatile registers.
64 * r31 will hold "old PTE"
65 * r30 is "new PTE"
66 * r29 is vpn
67 * r28 is a hash value
68 * r27 is hashtab mask (maybe dynamic patched instead ?)
69 */
70 std r27,STK_REG(R27)(r1)
71 std r28,STK_REG(R28)(r1)
72 std r29,STK_REG(R29)(r1)
73 std r30,STK_REG(R30)(r1)
74 std r31,STK_REG(R31)(r1)
75
76 /* Step 1:
77 *
78 * Check permissions, atomically mark the linux PTE busy
79 * and hashed.
80 */
81 1:
82 ldarx r31,0,r6
83 /* Check access rights (access & ~(pte_val(*ptep))) */
84 andc. r0,r4,r31
85 bne- htab_wrong_access
86 /* Check if PTE is busy */
87 andi. r0,r31,_PAGE_BUSY
88 /* If so, just bail out and refault if needed. Someone else
89 * is changing this PTE anyway and might hash it.
90 */
91 bne- htab_bail_ok
92
93 /* Prepare new PTE value (turn access RW into DIRTY, then
94 * add BUSY,HASHPTE and ACCESSED)
95 */
96 rlwinm r30,r4,32-9+7,31-7,31-7 /* _PAGE_RW -> _PAGE_DIRTY */
97 or r30,r30,r31
98 ori r30,r30,_PAGE_BUSY | _PAGE_ACCESSED | _PAGE_HASHPTE
99 /* Write the linux PTE atomically (setting busy) */
100 stdcx. r30,0,r6
101 bne- 1b
102 isync
103
104 /* Step 2:
105 *
106 * Insert/Update the HPTE in the hash table. At this point,
107 * r4 (access) is re-useable, we use it for the new HPTE flags
108 */
109
110 BEGIN_FTR_SECTION
111 cmpdi r9,0 /* check segment size */
112 bne 3f
113 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
114 /* Calc vpn and put it in r29 */
115 sldi r29,r5,SID_SHIFT - VPN_SHIFT
116 rldicl r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT - VPN_SHIFT)
117 or r29,r28,r29
118 /*
119 * Calculate hash value for primary slot and store it in r28
120 * r3 = va, r5 = vsid
121 * r0 = (va >> 12) & ((1ul << (28 - 12)) -1)
122 */
123 rldicl r0,r3,64-12,48
124 xor r28,r5,r0 /* hash */
125 b 4f
126
127 3: /* Calc vpn and put it in r29 */
128 sldi r29,r5,SID_SHIFT_1T - VPN_SHIFT
129 rldicl r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT_1T - VPN_SHIFT)
130 or r29,r28,r29
131
132 /*
133 * calculate hash value for primary slot and
134 * store it in r28 for 1T segment
135 * r3 = va, r5 = vsid
136 */
137 sldi r28,r5,25 /* vsid << 25 */
138 /* r0 = (va >> 12) & ((1ul << (40 - 12)) -1) */
139 rldicl r0,r3,64-12,36
140 xor r28,r28,r5 /* vsid ^ ( vsid << 25) */
141 xor r28,r28,r0 /* hash */
142
143 /* Convert linux PTE bits into HW equivalents */
144 4: andi. r3,r30,0x1fe /* Get basic set of flags */
145 xori r3,r3,HPTE_R_N /* _PAGE_EXEC -> NOEXEC */
146 rlwinm r0,r30,32-9+1,30,30 /* _PAGE_RW -> _PAGE_USER (r0) */
147 rlwinm r4,r30,32-7+1,30,30 /* _PAGE_DIRTY -> _PAGE_USER (r4) */
148 and r0,r0,r4 /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
149 andc r0,r30,r0 /* r0 = pte & ~r0 */
150 rlwimi r3,r0,32-1,31,31 /* Insert result into PP lsb */
151 /*
152 * Always add "C" bit for perf. Memory coherence is always enabled
153 */
154 ori r3,r3,HPTE_R_C | HPTE_R_M
155
156 /* We eventually do the icache sync here (maybe inline that
157 * code rather than call a C function...)
158 */
159 BEGIN_FTR_SECTION
160 mr r4,r30
161 mr r5,r7
162 bl .hash_page_do_lazy_icache
163 END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)
164
165 /* At this point, r3 contains new PP bits, save them in
166 * place of "access" in the param area (sic)
167 */
168 std r3,STK_PARAM(R4)(r1)
169
170 /* Get htab_hash_mask */
171 ld r4,htab_hash_mask@got(2)
172 ld r27,0(r4) /* htab_hash_mask -> r27 */
173
174 /* Check if we may already be in the hashtable, in this case, we
175 * go to out-of-line code to try to modify the HPTE
176 */
177 andi. r0,r31,_PAGE_HASHPTE
178 bne htab_modify_pte
179
180 htab_insert_pte:
181 /* Clear hpte bits in new pte (we also clear BUSY btw) and
182 * add _PAGE_HASHPTE
183 */
184 lis r0,_PAGE_HPTEFLAGS@h
185 ori r0,r0,_PAGE_HPTEFLAGS@l
186 andc r30,r30,r0
187 ori r30,r30,_PAGE_HASHPTE
188
189 /* physical address r5 */
190 rldicl r5,r31,64-PTE_RPN_SHIFT,PTE_RPN_SHIFT
191 sldi r5,r5,PAGE_SHIFT
192
193 /* Calculate primary group hash */
194 and r0,r28,r27
195 rldicr r3,r0,3,63-3 /* r3 = (hash & mask) << 3 */
196
197 /* Call ppc_md.hpte_insert */
198 ld r6,STK_PARAM(R4)(r1) /* Retrieve new pp bits */
199 mr r4,r29 /* Retrieve vpn */
200 li r7,0 /* !bolted, !secondary */
201 li r8,MMU_PAGE_4K /* page size */
202 li r9,MMU_PAGE_4K /* actual page size */
203 ld r10,STK_PARAM(R9)(r1) /* segment size */
204 _GLOBAL(htab_call_hpte_insert1)
205 bl . /* Patched by htab_finish_init() */
206 cmpdi 0,r3,0
207 bge htab_pte_insert_ok /* Insertion successful */
208 cmpdi 0,r3,-2 /* Critical failure */
209 beq- htab_pte_insert_failure
210
211 /* Now try secondary slot */
212
213 /* physical address r5 */
214 rldicl r5,r31,64-PTE_RPN_SHIFT,PTE_RPN_SHIFT
215 sldi r5,r5,PAGE_SHIFT
216
217 /* Calculate secondary group hash */
218 andc r0,r27,r28
219 rldicr r3,r0,3,63-3 /* r0 = (~hash & mask) << 3 */
220
221 /* Call ppc_md.hpte_insert */
222 ld r6,STK_PARAM(R4)(r1) /* Retrieve new pp bits */
223 mr r4,r29 /* Retrieve vpn */
224 li r7,HPTE_V_SECONDARY /* !bolted, secondary */
225 li r8,MMU_PAGE_4K /* page size */
226 li r9,MMU_PAGE_4K /* actual page size */
227 ld r10,STK_PARAM(R9)(r1) /* segment size */
228 _GLOBAL(htab_call_hpte_insert2)
229 bl . /* Patched by htab_finish_init() */
230 cmpdi 0,r3,0
231 bge+ htab_pte_insert_ok /* Insertion successful */
232 cmpdi 0,r3,-2 /* Critical failure */
233 beq- htab_pte_insert_failure
234
235 /* Both are full, we need to evict something */
236 mftb r0
237 /* Pick a random group based on TB */
238 andi. r0,r0,1
239 mr r5,r28
240 bne 2f
241 not r5,r5
242 2: and r0,r5,r27
243 rldicr r3,r0,3,63-3 /* r0 = (hash & mask) << 3 */
244 /* Call ppc_md.hpte_remove */
245 _GLOBAL(htab_call_hpte_remove)
246 bl . /* Patched by htab_finish_init() */
247
248 /* Try all again */
249 b htab_insert_pte
250
251 htab_bail_ok:
252 li r3,0
253 b htab_bail
254
255 htab_pte_insert_ok:
256 /* Insert slot number & secondary bit in PTE */
257 rldimi r30,r3,12,63-15
258
259 /* Write out the PTE with a normal write
260 * (maybe add eieio may be good still ?)
261 */
262 htab_write_out_pte:
263 ld r6,STK_PARAM(R6)(r1)
264 std r30,0(r6)
265 li r3, 0
266 htab_bail:
267 ld r27,STK_REG(R27)(r1)
268 ld r28,STK_REG(R28)(r1)
269 ld r29,STK_REG(R29)(r1)
270 ld r30,STK_REG(R30)(r1)
271 ld r31,STK_REG(R31)(r1)
272 addi r1,r1,STACKFRAMESIZE
273 ld r0,16(r1)
274 mtlr r0
275 blr
276
277 htab_modify_pte:
278 /* Keep PP bits in r4 and slot idx from the PTE around in r3 */
279 mr r4,r3
280 rlwinm r3,r31,32-12,29,31
281
282 /* Secondary group ? if yes, get a inverted hash value */
283 mr r5,r28
284 andi. r0,r31,_PAGE_SECONDARY
285 beq 1f
286 not r5,r5
287 1:
288 /* Calculate proper slot value for ppc_md.hpte_updatepp */
289 and r0,r5,r27
290 rldicr r0,r0,3,63-3 /* r0 = (hash & mask) << 3 */
291 add r3,r0,r3 /* add slot idx */
292
293 /* Call ppc_md.hpte_updatepp */
294 mr r5,r29 /* vpn */
295 li r6,MMU_PAGE_4K /* base page size */
296 li r7,MMU_PAGE_4K /* actual page size */
297 ld r8,STK_PARAM(R9)(r1) /* segment size */
298 ld r9,STK_PARAM(R8)(r1) /* get "local" param */
299 _GLOBAL(htab_call_hpte_updatepp)
300 bl . /* Patched by htab_finish_init() */
301
302 /* if we failed because typically the HPTE wasn't really here
303 * we try an insertion.
304 */
305 cmpdi 0,r3,-1
306 beq- htab_insert_pte
307
308 /* Clear the BUSY bit and Write out the PTE */
309 li r0,_PAGE_BUSY
310 andc r30,r30,r0
311 b htab_write_out_pte
312
313 htab_wrong_access:
314 /* Bail out clearing reservation */
315 stdcx. r31,0,r6
316 li r3,1
317 b htab_bail
318
319 htab_pte_insert_failure:
320 /* Bail out restoring old PTE */
321 ld r6,STK_PARAM(R6)(r1)
322 std r31,0(r6)
323 li r3,-1
324 b htab_bail
325
326
327 #else /* CONFIG_PPC_64K_PAGES */
328
329
330 /*****************************************************************************
331 * *
332 * 64K SW & 4K or 64K HW in a 4K segment pages implementation *
333 * *
334 *****************************************************************************/
335
336 /* _hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,
337 * pte_t *ptep, unsigned long trap, int local, int ssize,
338 * int subpg_prot)
339 */
340
341 /*
342 * For now, we do NOT implement Admixed pages
343 */
344 _GLOBAL(__hash_page_4K)
345 mflr r0
346 std r0,16(r1)
347 stdu r1,-STACKFRAMESIZE(r1)
348 /* Save all params that we need after a function call */
349 std r6,STK_PARAM(R6)(r1)
350 std r8,STK_PARAM(R8)(r1)
351 std r9,STK_PARAM(R9)(r1)
352
353 /* Save non-volatile registers.
354 * r31 will hold "old PTE"
355 * r30 is "new PTE"
356 * r29 is vpn
357 * r28 is a hash value
358 * r27 is hashtab mask (maybe dynamic patched instead ?)
359 * r26 is the hidx mask
360 * r25 is the index in combo page
361 */
362 std r25,STK_REG(R25)(r1)
363 std r26,STK_REG(R26)(r1)
364 std r27,STK_REG(R27)(r1)
365 std r28,STK_REG(R28)(r1)
366 std r29,STK_REG(R29)(r1)
367 std r30,STK_REG(R30)(r1)
368 std r31,STK_REG(R31)(r1)
369
370 /* Step 1:
371 *
372 * Check permissions, atomically mark the linux PTE busy
373 * and hashed.
374 */
375 1:
376 ldarx r31,0,r6
377 /* Check access rights (access & ~(pte_val(*ptep))) */
378 andc. r0,r4,r31
379 bne- htab_wrong_access
380 /* Check if PTE is busy */
381 andi. r0,r31,_PAGE_BUSY
382 /* If so, just bail out and refault if needed. Someone else
383 * is changing this PTE anyway and might hash it.
384 */
385 bne- htab_bail_ok
386 /* Prepare new PTE value (turn access RW into DIRTY, then
387 * add BUSY and ACCESSED)
388 */
389 rlwinm r30,r4,32-9+7,31-7,31-7 /* _PAGE_RW -> _PAGE_DIRTY */
390 or r30,r30,r31
391 ori r30,r30,_PAGE_BUSY | _PAGE_ACCESSED
392 oris r30,r30,_PAGE_COMBO@h
393 /* Write the linux PTE atomically (setting busy) */
394 stdcx. r30,0,r6
395 bne- 1b
396 isync
397
398 /* Step 2:
399 *
400 * Insert/Update the HPTE in the hash table. At this point,
401 * r4 (access) is re-useable, we use it for the new HPTE flags
402 */
403
404 /* Load the hidx index */
405 rldicl r25,r3,64-12,60
406
407 BEGIN_FTR_SECTION
408 cmpdi r9,0 /* check segment size */
409 bne 3f
410 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
411 /* Calc vpn and put it in r29 */
412 sldi r29,r5,SID_SHIFT - VPN_SHIFT
413 /*
414 * clrldi r3,r3,64 - SID_SHIFT --> ea & 0xfffffff
415 * srdi r28,r3,VPN_SHIFT
416 */
417 rldicl r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT - VPN_SHIFT)
418 or r29,r28,r29
419 /*
420 * Calculate hash value for primary slot and store it in r28
421 * r3 = va, r5 = vsid
422 * r0 = (va >> 12) & ((1ul << (28 - 12)) -1)
423 */
424 rldicl r0,r3,64-12,48
425 xor r28,r5,r0 /* hash */
426 b 4f
427
428 3: /* Calc vpn and put it in r29 */
429 sldi r29,r5,SID_SHIFT_1T - VPN_SHIFT
430 /*
431 * clrldi r3,r3,64 - SID_SHIFT_1T --> ea & 0xffffffffff
432 * srdi r28,r3,VPN_SHIFT
433 */
434 rldicl r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT_1T - VPN_SHIFT)
435 or r29,r28,r29
436
437 /*
438 * Calculate hash value for primary slot and
439 * store it in r28 for 1T segment
440 * r3 = va, r5 = vsid
441 */
442 sldi r28,r5,25 /* vsid << 25 */
443 /* r0 = (va >> 12) & ((1ul << (40 - 12)) -1) */
444 rldicl r0,r3,64-12,36
445 xor r28,r28,r5 /* vsid ^ ( vsid << 25) */
446 xor r28,r28,r0 /* hash */
447
448 /* Convert linux PTE bits into HW equivalents */
449 4:
450 #ifdef CONFIG_PPC_SUBPAGE_PROT
451 andc r10,r30,r10
452 andi. r3,r10,0x1fe /* Get basic set of flags */
453 rlwinm r0,r10,32-9+1,30,30 /* _PAGE_RW -> _PAGE_USER (r0) */
454 #else
455 andi. r3,r30,0x1fe /* Get basic set of flags */
456 rlwinm r0,r30,32-9+1,30,30 /* _PAGE_RW -> _PAGE_USER (r0) */
457 #endif
458 xori r3,r3,HPTE_R_N /* _PAGE_EXEC -> NOEXEC */
459 rlwinm r4,r30,32-7+1,30,30 /* _PAGE_DIRTY -> _PAGE_USER (r4) */
460 and r0,r0,r4 /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
461 andc r0,r3,r0 /* r0 = pte & ~r0 */
462 rlwimi r3,r0,32-1,31,31 /* Insert result into PP lsb */
463 /*
464 * Always add "C" bit for perf. Memory coherence is always enabled
465 */
466 ori r3,r3,HPTE_R_C | HPTE_R_M
467
468 /* We eventually do the icache sync here (maybe inline that
469 * code rather than call a C function...)
470 */
471 BEGIN_FTR_SECTION
472 mr r4,r30
473 mr r5,r7
474 bl .hash_page_do_lazy_icache
475 END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)
476
477 /* At this point, r3 contains new PP bits, save them in
478 * place of "access" in the param area (sic)
479 */
480 std r3,STK_PARAM(R4)(r1)
481
482 /* Get htab_hash_mask */
483 ld r4,htab_hash_mask@got(2)
484 ld r27,0(r4) /* htab_hash_mask -> r27 */
485
486 /* Check if we may already be in the hashtable, in this case, we
487 * go to out-of-line code to try to modify the HPTE. We look for
488 * the bit at (1 >> (index + 32))
489 */
490 rldicl. r0,r31,64-12,48
491 li r26,0 /* Default hidx */
492 beq htab_insert_pte
493
494 /*
495 * Check if the pte was already inserted into the hash table
496 * as a 64k HW page, and invalidate the 64k HPTE if so.
497 */
498 andis. r0,r31,_PAGE_COMBO@h
499 beq htab_inval_old_hpte
500
501 ld r6,STK_PARAM(R6)(r1)
502 ori r26,r6,PTE_PAGE_HIDX_OFFSET /* Load the hidx mask. */
503 ld r26,0(r26)
504 addi r5,r25,36 /* Check actual HPTE_SUB bit, this */
505 rldcr. r0,r31,r5,0 /* must match pgtable.h definition */
506 bne htab_modify_pte
507
508 htab_insert_pte:
509 /* real page number in r5, PTE RPN value + index */
510 andis. r0,r31,_PAGE_4K_PFN@h
511 srdi r5,r31,PTE_RPN_SHIFT
512 bne- htab_special_pfn
513 sldi r5,r5,PAGE_SHIFT-HW_PAGE_SHIFT
514 add r5,r5,r25
515 htab_special_pfn:
516 sldi r5,r5,HW_PAGE_SHIFT
517
518 /* Calculate primary group hash */
519 and r0,r28,r27
520 rldicr r3,r0,3,63-3 /* r0 = (hash & mask) << 3 */
521
522 /* Call ppc_md.hpte_insert */
523 ld r6,STK_PARAM(R4)(r1) /* Retrieve new pp bits */
524 mr r4,r29 /* Retrieve vpn */
525 li r7,0 /* !bolted, !secondary */
526 li r8,MMU_PAGE_4K /* page size */
527 li r9,MMU_PAGE_4K /* actual page size */
528 ld r10,STK_PARAM(R9)(r1) /* segment size */
529 _GLOBAL(htab_call_hpte_insert1)
530 bl . /* patched by htab_finish_init() */
531 cmpdi 0,r3,0
532 bge htab_pte_insert_ok /* Insertion successful */
533 cmpdi 0,r3,-2 /* Critical failure */
534 beq- htab_pte_insert_failure
535
536 /* Now try secondary slot */
537
538 /* real page number in r5, PTE RPN value + index */
539 andis. r0,r31,_PAGE_4K_PFN@h
540 srdi r5,r31,PTE_RPN_SHIFT
541 bne- 3f
542 sldi r5,r5,PAGE_SHIFT-HW_PAGE_SHIFT
543 add r5,r5,r25
544 3: sldi r5,r5,HW_PAGE_SHIFT
545
546 /* Calculate secondary group hash */
547 andc r0,r27,r28
548 rldicr r3,r0,3,63-3 /* r0 = (~hash & mask) << 3 */
549
550 /* Call ppc_md.hpte_insert */
551 ld r6,STK_PARAM(R4)(r1) /* Retrieve new pp bits */
552 mr r4,r29 /* Retrieve vpn */
553 li r7,HPTE_V_SECONDARY /* !bolted, secondary */
554 li r8,MMU_PAGE_4K /* page size */
555 li r9,MMU_PAGE_4K /* actual page size */
556 ld r10,STK_PARAM(R9)(r1) /* segment size */
557 _GLOBAL(htab_call_hpte_insert2)
558 bl . /* patched by htab_finish_init() */
559 cmpdi 0,r3,0
560 bge+ htab_pte_insert_ok /* Insertion successful */
561 cmpdi 0,r3,-2 /* Critical failure */
562 beq- htab_pte_insert_failure
563
564 /* Both are full, we need to evict something */
565 mftb r0
566 /* Pick a random group based on TB */
567 andi. r0,r0,1
568 mr r5,r28
569 bne 2f
570 not r5,r5
571 2: and r0,r5,r27
572 rldicr r3,r0,3,63-3 /* r0 = (hash & mask) << 3 */
573 /* Call ppc_md.hpte_remove */
574 _GLOBAL(htab_call_hpte_remove)
575 bl . /* patched by htab_finish_init() */
576
577 /* Try all again */
578 b htab_insert_pte
579
580 /*
581 * Call out to C code to invalidate an 64k HW HPTE that is
582 * useless now that the segment has been switched to 4k pages.
583 */
584 htab_inval_old_hpte:
585 mr r3,r29 /* vpn */
586 mr r4,r31 /* PTE.pte */
587 li r5,0 /* PTE.hidx */
588 li r6,MMU_PAGE_64K /* psize */
589 ld r7,STK_PARAM(R9)(r1) /* ssize */
590 ld r8,STK_PARAM(R8)(r1) /* local */
591 bl .flush_hash_page
592 /* Clear out _PAGE_HPTE_SUB bits in the new linux PTE */
593 lis r0,_PAGE_HPTE_SUB@h
594 ori r0,r0,_PAGE_HPTE_SUB@l
595 andc r30,r30,r0
596 b htab_insert_pte
597
598 htab_bail_ok:
599 li r3,0
600 b htab_bail
601
602 htab_pte_insert_ok:
603 /* Insert slot number & secondary bit in PTE second half,
604 * clear _PAGE_BUSY and set approriate HPTE slot bit
605 */
606 ld r6,STK_PARAM(R6)(r1)
607 li r0,_PAGE_BUSY
608 andc r30,r30,r0
609 /* HPTE SUB bit */
610 li r0,1
611 subfic r5,r25,27 /* Must match bit position in */
612 sld r0,r0,r5 /* pgtable.h */
613 or r30,r30,r0
614 /* hindx */
615 sldi r5,r25,2
616 sld r3,r3,r5
617 li r4,0xf
618 sld r4,r4,r5
619 andc r26,r26,r4
620 or r26,r26,r3
621 ori r5,r6,PTE_PAGE_HIDX_OFFSET
622 std r26,0(r5)
623 lwsync
624 std r30,0(r6)
625 li r3, 0
626 htab_bail:
627 ld r25,STK_REG(R25)(r1)
628 ld r26,STK_REG(R26)(r1)
629 ld r27,STK_REG(R27)(r1)
630 ld r28,STK_REG(R28)(r1)
631 ld r29,STK_REG(R29)(r1)
632 ld r30,STK_REG(R30)(r1)
633 ld r31,STK_REG(R31)(r1)
634 addi r1,r1,STACKFRAMESIZE
635 ld r0,16(r1)
636 mtlr r0
637 blr
638
639 htab_modify_pte:
640 /* Keep PP bits in r4 and slot idx from the PTE around in r3 */
641 mr r4,r3
642 sldi r5,r25,2
643 srd r3,r26,r5
644
645 /* Secondary group ? if yes, get a inverted hash value */
646 mr r5,r28
647 andi. r0,r3,0x8 /* page secondary ? */
648 beq 1f
649 not r5,r5
650 1: andi. r3,r3,0x7 /* extract idx alone */
651
652 /* Calculate proper slot value for ppc_md.hpte_updatepp */
653 and r0,r5,r27
654 rldicr r0,r0,3,63-3 /* r0 = (hash & mask) << 3 */
655 add r3,r0,r3 /* add slot idx */
656
657 /* Call ppc_md.hpte_updatepp */
658 mr r5,r29 /* vpn */
659 li r6,MMU_PAGE_4K /* base page size */
660 li r7,MMU_PAGE_4K /* actual page size */
661 ld r8,STK_PARAM(R9)(r1) /* segment size */
662 ld r9,STK_PARAM(R8)(r1) /* get "local" param */
663 _GLOBAL(htab_call_hpte_updatepp)
664 bl . /* patched by htab_finish_init() */
665
666 /* if we failed because typically the HPTE wasn't really here
667 * we try an insertion.
668 */
669 cmpdi 0,r3,-1
670 beq- htab_insert_pte
671
672 /* Clear the BUSY bit and Write out the PTE */
673 li r0,_PAGE_BUSY
674 andc r30,r30,r0
675 ld r6,STK_PARAM(R6)(r1)
676 std r30,0(r6)
677 li r3,0
678 b htab_bail
679
680 htab_wrong_access:
681 /* Bail out clearing reservation */
682 stdcx. r31,0,r6
683 li r3,1
684 b htab_bail
685
686 htab_pte_insert_failure:
687 /* Bail out restoring old PTE */
688 ld r6,STK_PARAM(R6)(r1)
689 std r31,0(r6)
690 li r3,-1
691 b htab_bail
692
693 #endif /* CONFIG_PPC_64K_PAGES */
694
695 #ifdef CONFIG_PPC_HAS_HASH_64K
696
697 /*****************************************************************************
698 * *
699 * 64K SW & 64K HW in a 64K segment pages implementation *
700 * *
701 *****************************************************************************/
702
703 _GLOBAL(__hash_page_64K)
704 mflr r0
705 std r0,16(r1)
706 stdu r1,-STACKFRAMESIZE(r1)
707 /* Save all params that we need after a function call */
708 std r6,STK_PARAM(R6)(r1)
709 std r8,STK_PARAM(R8)(r1)
710 std r9,STK_PARAM(R9)(r1)
711
712 /* Save non-volatile registers.
713 * r31 will hold "old PTE"
714 * r30 is "new PTE"
715 * r29 is vpn
716 * r28 is a hash value
717 * r27 is hashtab mask (maybe dynamic patched instead ?)
718 */
719 std r27,STK_REG(R27)(r1)
720 std r28,STK_REG(R28)(r1)
721 std r29,STK_REG(R29)(r1)
722 std r30,STK_REG(R30)(r1)
723 std r31,STK_REG(R31)(r1)
724
725 /* Step 1:
726 *
727 * Check permissions, atomically mark the linux PTE busy
728 * and hashed.
729 */
730 1:
731 ldarx r31,0,r6
732 /* Check access rights (access & ~(pte_val(*ptep))) */
733 andc. r0,r4,r31
734 bne- ht64_wrong_access
735 /* Check if PTE is busy */
736 andi. r0,r31,_PAGE_BUSY
737 /* If so, just bail out and refault if needed. Someone else
738 * is changing this PTE anyway and might hash it.
739 */
740 bne- ht64_bail_ok
741 BEGIN_FTR_SECTION
742 /* Check if PTE has the cache-inhibit bit set */
743 andi. r0,r31,_PAGE_NO_CACHE
744 /* If so, bail out and refault as a 4k page */
745 bne- ht64_bail_ok
746 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_CI_LARGE_PAGE)
747 /* Prepare new PTE value (turn access RW into DIRTY, then
748 * add BUSY and ACCESSED)
749 */
750 rlwinm r30,r4,32-9+7,31-7,31-7 /* _PAGE_RW -> _PAGE_DIRTY */
751 or r30,r30,r31
752 ori r30,r30,_PAGE_BUSY | _PAGE_ACCESSED
753 /* Write the linux PTE atomically (setting busy) */
754 stdcx. r30,0,r6
755 bne- 1b
756 isync
757
758 /* Step 2:
759 *
760 * Insert/Update the HPTE in the hash table. At this point,
761 * r4 (access) is re-useable, we use it for the new HPTE flags
762 */
763
764 BEGIN_FTR_SECTION
765 cmpdi r9,0 /* check segment size */
766 bne 3f
767 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
768 /* Calc vpn and put it in r29 */
769 sldi r29,r5,SID_SHIFT - VPN_SHIFT
770 rldicl r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT - VPN_SHIFT)
771 or r29,r28,r29
772
773 /* Calculate hash value for primary slot and store it in r28
774 * r3 = va, r5 = vsid
775 * r0 = (va >> 16) & ((1ul << (28 - 16)) -1)
776 */
777 rldicl r0,r3,64-16,52
778 xor r28,r5,r0 /* hash */
779 b 4f
780
781 3: /* Calc vpn and put it in r29 */
782 sldi r29,r5,SID_SHIFT_1T - VPN_SHIFT
783 rldicl r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT_1T - VPN_SHIFT)
784 or r29,r28,r29
785 /*
786 * calculate hash value for primary slot and
787 * store it in r28 for 1T segment
788 * r3 = va, r5 = vsid
789 */
790 sldi r28,r5,25 /* vsid << 25 */
791 /* r0 = (va >> 16) & ((1ul << (40 - 16)) -1) */
792 rldicl r0,r3,64-16,40
793 xor r28,r28,r5 /* vsid ^ ( vsid << 25) */
794 xor r28,r28,r0 /* hash */
795
796 /* Convert linux PTE bits into HW equivalents */
797 4: andi. r3,r30,0x1fe /* Get basic set of flags */
798 xori r3,r3,HPTE_R_N /* _PAGE_EXEC -> NOEXEC */
799 rlwinm r0,r30,32-9+1,30,30 /* _PAGE_RW -> _PAGE_USER (r0) */
800 rlwinm r4,r30,32-7+1,30,30 /* _PAGE_DIRTY -> _PAGE_USER (r4) */
801 and r0,r0,r4 /* _PAGE_RW & _PAGE_DIRTY ->r0 bit 30*/
802 andc r0,r30,r0 /* r0 = pte & ~r0 */
803 rlwimi r3,r0,32-1,31,31 /* Insert result into PP lsb */
804 /*
805 * Always add "C" bit for perf. Memory coherence is always enabled
806 */
807 ori r3,r3,HPTE_R_C | HPTE_R_M
808
809 /* We eventually do the icache sync here (maybe inline that
810 * code rather than call a C function...)
811 */
812 BEGIN_FTR_SECTION
813 mr r4,r30
814 mr r5,r7
815 bl .hash_page_do_lazy_icache
816 END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)
817
818 /* At this point, r3 contains new PP bits, save them in
819 * place of "access" in the param area (sic)
820 */
821 std r3,STK_PARAM(R4)(r1)
822
823 /* Get htab_hash_mask */
824 ld r4,htab_hash_mask@got(2)
825 ld r27,0(r4) /* htab_hash_mask -> r27 */
826
827 /* Check if we may already be in the hashtable, in this case, we
828 * go to out-of-line code to try to modify the HPTE
829 */
830 rldicl. r0,r31,64-12,48
831 bne ht64_modify_pte
832
833 ht64_insert_pte:
834 /* Clear hpte bits in new pte (we also clear BUSY btw) and
835 * add _PAGE_HPTE_SUB0
836 */
837 lis r0,_PAGE_HPTEFLAGS@h
838 ori r0,r0,_PAGE_HPTEFLAGS@l
839 andc r30,r30,r0
840 #ifdef CONFIG_PPC_64K_PAGES
841 oris r30,r30,_PAGE_HPTE_SUB0@h
842 #else
843 ori r30,r30,_PAGE_HASHPTE
844 #endif
845 /* Phyical address in r5 */
846 rldicl r5,r31,64-PTE_RPN_SHIFT,PTE_RPN_SHIFT
847 sldi r5,r5,PAGE_SHIFT
848
849 /* Calculate primary group hash */
850 and r0,r28,r27
851 rldicr r3,r0,3,63-3 /* r0 = (hash & mask) << 3 */
852
853 /* Call ppc_md.hpte_insert */
854 ld r6,STK_PARAM(R4)(r1) /* Retrieve new pp bits */
855 mr r4,r29 /* Retrieve vpn */
856 li r7,0 /* !bolted, !secondary */
857 li r8,MMU_PAGE_64K
858 li r9,MMU_PAGE_64K /* actual page size */
859 ld r10,STK_PARAM(R9)(r1) /* segment size */
860 _GLOBAL(ht64_call_hpte_insert1)
861 bl . /* patched by htab_finish_init() */
862 cmpdi 0,r3,0
863 bge ht64_pte_insert_ok /* Insertion successful */
864 cmpdi 0,r3,-2 /* Critical failure */
865 beq- ht64_pte_insert_failure
866
867 /* Now try secondary slot */
868
869 /* Phyical address in r5 */
870 rldicl r5,r31,64-PTE_RPN_SHIFT,PTE_RPN_SHIFT
871 sldi r5,r5,PAGE_SHIFT
872
873 /* Calculate secondary group hash */
874 andc r0,r27,r28
875 rldicr r3,r0,3,63-3 /* r0 = (~hash & mask) << 3 */
876
877 /* Call ppc_md.hpte_insert */
878 ld r6,STK_PARAM(R4)(r1) /* Retrieve new pp bits */
879 mr r4,r29 /* Retrieve vpn */
880 li r7,HPTE_V_SECONDARY /* !bolted, secondary */
881 li r8,MMU_PAGE_64K
882 li r9,MMU_PAGE_64K /* actual page size */
883 ld r10,STK_PARAM(R9)(r1) /* segment size */
884 _GLOBAL(ht64_call_hpte_insert2)
885 bl . /* patched by htab_finish_init() */
886 cmpdi 0,r3,0
887 bge+ ht64_pte_insert_ok /* Insertion successful */
888 cmpdi 0,r3,-2 /* Critical failure */
889 beq- ht64_pte_insert_failure
890
891 /* Both are full, we need to evict something */
892 mftb r0
893 /* Pick a random group based on TB */
894 andi. r0,r0,1
895 mr r5,r28
896 bne 2f
897 not r5,r5
898 2: and r0,r5,r27
899 rldicr r3,r0,3,63-3 /* r0 = (hash & mask) << 3 */
900 /* Call ppc_md.hpte_remove */
901 _GLOBAL(ht64_call_hpte_remove)
902 bl . /* patched by htab_finish_init() */
903
904 /* Try all again */
905 b ht64_insert_pte
906
907 ht64_bail_ok:
908 li r3,0
909 b ht64_bail
910
911 ht64_pte_insert_ok:
912 /* Insert slot number & secondary bit in PTE */
913 rldimi r30,r3,12,63-15
914
915 /* Write out the PTE with a normal write
916 * (maybe add eieio may be good still ?)
917 */
918 ht64_write_out_pte:
919 ld r6,STK_PARAM(R6)(r1)
920 std r30,0(r6)
921 li r3, 0
922 ht64_bail:
923 ld r27,STK_REG(R27)(r1)
924 ld r28,STK_REG(R28)(r1)
925 ld r29,STK_REG(R29)(r1)
926 ld r30,STK_REG(R30)(r1)
927 ld r31,STK_REG(R31)(r1)
928 addi r1,r1,STACKFRAMESIZE
929 ld r0,16(r1)
930 mtlr r0
931 blr
932
933 ht64_modify_pte:
934 /* Keep PP bits in r4 and slot idx from the PTE around in r3 */
935 mr r4,r3
936 rlwinm r3,r31,32-12,29,31
937
938 /* Secondary group ? if yes, get a inverted hash value */
939 mr r5,r28
940 andi. r0,r31,_PAGE_F_SECOND
941 beq 1f
942 not r5,r5
943 1:
944 /* Calculate proper slot value for ppc_md.hpte_updatepp */
945 and r0,r5,r27
946 rldicr r0,r0,3,63-3 /* r0 = (hash & mask) << 3 */
947 add r3,r0,r3 /* add slot idx */
948
949 /* Call ppc_md.hpte_updatepp */
950 mr r5,r29 /* vpn */
951 li r6,MMU_PAGE_64K /* base page size */
952 li r7,MMU_PAGE_64K /* actual page size */
953 ld r8,STK_PARAM(R9)(r1) /* segment size */
954 ld r9,STK_PARAM(R8)(r1) /* get "local" param */
955 _GLOBAL(ht64_call_hpte_updatepp)
956 bl . /* patched by htab_finish_init() */
957
958 /* if we failed because typically the HPTE wasn't really here
959 * we try an insertion.
960 */
961 cmpdi 0,r3,-1
962 beq- ht64_insert_pte
963
964 /* Clear the BUSY bit and Write out the PTE */
965 li r0,_PAGE_BUSY
966 andc r30,r30,r0
967 b ht64_write_out_pte
968
969 ht64_wrong_access:
970 /* Bail out clearing reservation */
971 stdcx. r31,0,r6
972 li r3,1
973 b ht64_bail
974
975 ht64_pte_insert_failure:
976 /* Bail out restoring old PTE */
977 ld r6,STK_PARAM(R6)(r1)
978 std r31,0(r6)
979 li r3,-1
980 b ht64_bail
981
982
983 #endif /* CONFIG_PPC_HAS_HASH_64K */
984
985
986 /*****************************************************************************
987 * *
988 * Huge pages implementation is in hugetlbpage.c *
989 * *
990 *****************************************************************************/
Linux kernel - Deliverables
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