2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/export.h>
31 #include <linux/ctype.h>
32 #include <linux/cache.h>
33 #include <linux/init.h>
34 #include <linux/signal.h>
35 #include <linux/memblock.h>
37 #include <asm/processor.h>
38 #include <asm/pgtable.h>
40 #include <asm/mmu_context.h>
42 #include <asm/types.h>
43 #include <asm/uaccess.h>
44 #include <asm/machdep.h>
46 #include <asm/tlbflush.h>
50 #include <asm/cacheflush.h>
51 #include <asm/cputable.h>
52 #include <asm/sections.h>
55 #include <asm/code-patching.h>
56 #include <asm/fadump.h>
57 #include <asm/firmware.h>
61 #define DBG(fmt...) udbg_printf(fmt)
67 #define DBG_LOW(fmt...) udbg_printf(fmt)
69 #define DBG_LOW(fmt...)
77 * Note: pte --> Linux PTE
78 * HPTE --> PowerPC Hashed Page Table Entry
81 * htab_initialize is called with the MMU off (of course), but
82 * the kernel has been copied down to zero so it can directly
83 * reference global data. At this point it is very difficult
84 * to print debug info.
89 extern unsigned long dart_tablebase
;
90 #endif /* CONFIG_U3_DART */
92 static unsigned long _SDR1
;
93 struct mmu_psize_def mmu_psize_defs
[MMU_PAGE_COUNT
];
95 struct hash_pte
*htab_address
;
96 unsigned long htab_size_bytes
;
97 unsigned long htab_hash_mask
;
98 EXPORT_SYMBOL_GPL(htab_hash_mask
);
99 int mmu_linear_psize
= MMU_PAGE_4K
;
100 int mmu_virtual_psize
= MMU_PAGE_4K
;
101 int mmu_vmalloc_psize
= MMU_PAGE_4K
;
102 #ifdef CONFIG_SPARSEMEM_VMEMMAP
103 int mmu_vmemmap_psize
= MMU_PAGE_4K
;
105 int mmu_io_psize
= MMU_PAGE_4K
;
106 int mmu_kernel_ssize
= MMU_SEGSIZE_256M
;
107 int mmu_highuser_ssize
= MMU_SEGSIZE_256M
;
108 u16 mmu_slb_size
= 64;
109 EXPORT_SYMBOL_GPL(mmu_slb_size
);
110 #ifdef CONFIG_PPC_64K_PAGES
111 int mmu_ci_restrictions
;
113 #ifdef CONFIG_DEBUG_PAGEALLOC
114 static u8
*linear_map_hash_slots
;
115 static unsigned long linear_map_hash_count
;
116 static DEFINE_SPINLOCK(linear_map_hash_lock
);
117 #endif /* CONFIG_DEBUG_PAGEALLOC */
119 /* There are definitions of page sizes arrays to be used when none
120 * is provided by the firmware.
123 /* Pre-POWER4 CPUs (4k pages only)
125 static struct mmu_psize_def mmu_psize_defaults_old
[] = {
129 .penc
= {[MMU_PAGE_4K
] = 0, [1 ... MMU_PAGE_COUNT
- 1] = -1},
135 /* POWER4, GPUL, POWER5
137 * Support for 16Mb large pages
139 static struct mmu_psize_def mmu_psize_defaults_gp
[] = {
143 .penc
= {[MMU_PAGE_4K
] = 0, [1 ... MMU_PAGE_COUNT
- 1] = -1},
150 .penc
= {[0 ... MMU_PAGE_16M
- 1] = -1, [MMU_PAGE_16M
] = 0,
151 [MMU_PAGE_16M
+ 1 ... MMU_PAGE_COUNT
- 1] = -1 },
157 static unsigned long htab_convert_pte_flags(unsigned long pteflags
)
159 unsigned long rflags
= pteflags
& 0x1fa;
161 /* _PAGE_EXEC -> NOEXEC */
162 if ((pteflags
& _PAGE_EXEC
) == 0)
165 /* PP bits. PAGE_USER is already PP bit 0x2, so we only
166 * need to add in 0x1 if it's a read-only user page
168 if ((pteflags
& _PAGE_USER
) && !((pteflags
& _PAGE_RW
) &&
169 (pteflags
& _PAGE_DIRTY
)))
173 return rflags
| HPTE_R_C
;
176 int htab_bolt_mapping(unsigned long vstart
, unsigned long vend
,
177 unsigned long pstart
, unsigned long prot
,
178 int psize
, int ssize
)
180 unsigned long vaddr
, paddr
;
181 unsigned int step
, shift
;
184 shift
= mmu_psize_defs
[psize
].shift
;
187 prot
= htab_convert_pte_flags(prot
);
189 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
190 vstart
, vend
, pstart
, prot
, psize
, ssize
);
192 for (vaddr
= vstart
, paddr
= pstart
; vaddr
< vend
;
193 vaddr
+= step
, paddr
+= step
) {
194 unsigned long hash
, hpteg
;
195 unsigned long vsid
= get_kernel_vsid(vaddr
, ssize
);
196 unsigned long vpn
= hpt_vpn(vaddr
, vsid
, ssize
);
197 unsigned long tprot
= prot
;
200 * If we hit a bad address return error.
204 /* Make kernel text executable */
205 if (overlaps_kernel_text(vaddr
, vaddr
+ step
))
208 hash
= hpt_hash(vpn
, shift
, ssize
);
209 hpteg
= ((hash
& htab_hash_mask
) * HPTES_PER_GROUP
);
211 BUG_ON(!ppc_md
.hpte_insert
);
212 ret
= ppc_md
.hpte_insert(hpteg
, vpn
, paddr
, tprot
,
213 HPTE_V_BOLTED
, psize
, psize
, ssize
);
217 #ifdef CONFIG_DEBUG_PAGEALLOC
218 if ((paddr
>> PAGE_SHIFT
) < linear_map_hash_count
)
219 linear_map_hash_slots
[paddr
>> PAGE_SHIFT
] = ret
| 0x80;
220 #endif /* CONFIG_DEBUG_PAGEALLOC */
222 return ret
< 0 ? ret
: 0;
225 #ifdef CONFIG_MEMORY_HOTPLUG
226 static int htab_remove_mapping(unsigned long vstart
, unsigned long vend
,
227 int psize
, int ssize
)
230 unsigned int step
, shift
;
232 shift
= mmu_psize_defs
[psize
].shift
;
235 if (!ppc_md
.hpte_removebolted
) {
236 printk(KERN_WARNING
"Platform doesn't implement "
237 "hpte_removebolted\n");
241 for (vaddr
= vstart
; vaddr
< vend
; vaddr
+= step
)
242 ppc_md
.hpte_removebolted(vaddr
, psize
, ssize
);
246 #endif /* CONFIG_MEMORY_HOTPLUG */
248 static int __init
htab_dt_scan_seg_sizes(unsigned long node
,
249 const char *uname
, int depth
,
252 char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
254 unsigned long size
= 0;
256 /* We are scanning "cpu" nodes only */
257 if (type
== NULL
|| strcmp(type
, "cpu") != 0)
260 prop
= (u32
*)of_get_flat_dt_prop(node
, "ibm,processor-segment-sizes",
264 for (; size
>= 4; size
-= 4, ++prop
) {
266 DBG("1T segment support detected\n");
267 cur_cpu_spec
->mmu_features
|= MMU_FTR_1T_SEGMENT
;
271 cur_cpu_spec
->mmu_features
&= ~MMU_FTR_NO_SLBIE_B
;
275 static void __init
htab_init_seg_sizes(void)
277 of_scan_flat_dt(htab_dt_scan_seg_sizes
, NULL
);
280 static int __init
get_idx_from_shift(unsigned int shift
)
304 static int __init
htab_dt_scan_page_sizes(unsigned long node
,
305 const char *uname
, int depth
,
308 char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
310 unsigned long size
= 0;
312 /* We are scanning "cpu" nodes only */
313 if (type
== NULL
|| strcmp(type
, "cpu") != 0)
316 prop
= (u32
*)of_get_flat_dt_prop(node
,
317 "ibm,segment-page-sizes", &size
);
319 pr_info("Page sizes from device-tree:\n");
321 cur_cpu_spec
->mmu_features
&= ~(MMU_FTR_16M_PAGE
);
323 unsigned int base_shift
= prop
[0];
324 unsigned int slbenc
= prop
[1];
325 unsigned int lpnum
= prop
[2];
326 struct mmu_psize_def
*def
;
329 size
-= 3; prop
+= 3;
330 base_idx
= get_idx_from_shift(base_shift
);
333 * skip the pte encoding also
335 prop
+= lpnum
* 2; size
-= lpnum
* 2;
338 def
= &mmu_psize_defs
[base_idx
];
339 if (base_idx
== MMU_PAGE_16M
)
340 cur_cpu_spec
->mmu_features
|= MMU_FTR_16M_PAGE
;
342 def
->shift
= base_shift
;
343 if (base_shift
<= 23)
346 def
->avpnm
= (1 << (base_shift
- 23)) - 1;
349 * We don't know for sure what's up with tlbiel, so
350 * for now we only set it for 4K and 64K pages
352 if (base_idx
== MMU_PAGE_4K
|| base_idx
== MMU_PAGE_64K
)
357 while (size
> 0 && lpnum
) {
358 unsigned int shift
= prop
[0];
361 prop
+= 2; size
-= 2;
364 idx
= get_idx_from_shift(shift
);
369 pr_err("Invalid penc for base_shift=%d "
370 "shift=%d\n", base_shift
, shift
);
372 def
->penc
[idx
] = penc
;
373 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
374 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
375 base_shift
, shift
, def
->sllp
,
376 def
->avpnm
, def
->tlbiel
, def
->penc
[idx
]);
384 #ifdef CONFIG_HUGETLB_PAGE
385 /* Scan for 16G memory blocks that have been set aside for huge pages
386 * and reserve those blocks for 16G huge pages.
388 static int __init
htab_dt_scan_hugepage_blocks(unsigned long node
,
389 const char *uname
, int depth
,
391 char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
392 unsigned long *addr_prop
;
393 u32
*page_count_prop
;
394 unsigned int expected_pages
;
395 long unsigned int phys_addr
;
396 long unsigned int block_size
;
398 /* We are scanning "memory" nodes only */
399 if (type
== NULL
|| strcmp(type
, "memory") != 0)
402 /* This property is the log base 2 of the number of virtual pages that
403 * will represent this memory block. */
404 page_count_prop
= of_get_flat_dt_prop(node
, "ibm,expected#pages", NULL
);
405 if (page_count_prop
== NULL
)
407 expected_pages
= (1 << page_count_prop
[0]);
408 addr_prop
= of_get_flat_dt_prop(node
, "reg", NULL
);
409 if (addr_prop
== NULL
)
411 phys_addr
= addr_prop
[0];
412 block_size
= addr_prop
[1];
413 if (block_size
!= (16 * GB
))
415 printk(KERN_INFO
"Huge page(16GB) memory: "
416 "addr = 0x%lX size = 0x%lX pages = %d\n",
417 phys_addr
, block_size
, expected_pages
);
418 if (phys_addr
+ (16 * GB
) <= memblock_end_of_DRAM()) {
419 memblock_reserve(phys_addr
, block_size
* expected_pages
);
420 add_gpage(phys_addr
, block_size
, expected_pages
);
424 #endif /* CONFIG_HUGETLB_PAGE */
426 static void mmu_psize_set_default_penc(void)
429 for (bpsize
= 0; bpsize
< MMU_PAGE_COUNT
; bpsize
++)
430 for (apsize
= 0; apsize
< MMU_PAGE_COUNT
; apsize
++)
431 mmu_psize_defs
[bpsize
].penc
[apsize
] = -1;
434 static void __init
htab_init_page_sizes(void)
438 /* se the invalid penc to -1 */
439 mmu_psize_set_default_penc();
441 /* Default to 4K pages only */
442 memcpy(mmu_psize_defs
, mmu_psize_defaults_old
,
443 sizeof(mmu_psize_defaults_old
));
446 * Try to find the available page sizes in the device-tree
448 rc
= of_scan_flat_dt(htab_dt_scan_page_sizes
, NULL
);
449 if (rc
!= 0) /* Found */
453 * Not in the device-tree, let's fallback on known size
454 * list for 16M capable GP & GR
456 if (mmu_has_feature(MMU_FTR_16M_PAGE
))
457 memcpy(mmu_psize_defs
, mmu_psize_defaults_gp
,
458 sizeof(mmu_psize_defaults_gp
));
460 #ifndef CONFIG_DEBUG_PAGEALLOC
462 * Pick a size for the linear mapping. Currently, we only support
463 * 16M, 1M and 4K which is the default
465 if (mmu_psize_defs
[MMU_PAGE_16M
].shift
)
466 mmu_linear_psize
= MMU_PAGE_16M
;
467 else if (mmu_psize_defs
[MMU_PAGE_1M
].shift
)
468 mmu_linear_psize
= MMU_PAGE_1M
;
469 #endif /* CONFIG_DEBUG_PAGEALLOC */
471 #ifdef CONFIG_PPC_64K_PAGES
473 * Pick a size for the ordinary pages. Default is 4K, we support
474 * 64K for user mappings and vmalloc if supported by the processor.
475 * We only use 64k for ioremap if the processor
476 * (and firmware) support cache-inhibited large pages.
477 * If not, we use 4k and set mmu_ci_restrictions so that
478 * hash_page knows to switch processes that use cache-inhibited
479 * mappings to 4k pages.
481 if (mmu_psize_defs
[MMU_PAGE_64K
].shift
) {
482 mmu_virtual_psize
= MMU_PAGE_64K
;
483 mmu_vmalloc_psize
= MMU_PAGE_64K
;
484 if (mmu_linear_psize
== MMU_PAGE_4K
)
485 mmu_linear_psize
= MMU_PAGE_64K
;
486 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE
)) {
488 * Don't use 64k pages for ioremap on pSeries, since
489 * that would stop us accessing the HEA ethernet.
491 if (!machine_is(pseries
))
492 mmu_io_psize
= MMU_PAGE_64K
;
494 mmu_ci_restrictions
= 1;
496 #endif /* CONFIG_PPC_64K_PAGES */
498 #ifdef CONFIG_SPARSEMEM_VMEMMAP
499 /* We try to use 16M pages for vmemmap if that is supported
500 * and we have at least 1G of RAM at boot
502 if (mmu_psize_defs
[MMU_PAGE_16M
].shift
&&
503 memblock_phys_mem_size() >= 0x40000000)
504 mmu_vmemmap_psize
= MMU_PAGE_16M
;
505 else if (mmu_psize_defs
[MMU_PAGE_64K
].shift
)
506 mmu_vmemmap_psize
= MMU_PAGE_64K
;
508 mmu_vmemmap_psize
= MMU_PAGE_4K
;
509 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
511 printk(KERN_DEBUG
"Page orders: linear mapping = %d, "
512 "virtual = %d, io = %d"
513 #ifdef CONFIG_SPARSEMEM_VMEMMAP
517 mmu_psize_defs
[mmu_linear_psize
].shift
,
518 mmu_psize_defs
[mmu_virtual_psize
].shift
,
519 mmu_psize_defs
[mmu_io_psize
].shift
520 #ifdef CONFIG_SPARSEMEM_VMEMMAP
521 ,mmu_psize_defs
[mmu_vmemmap_psize
].shift
525 #ifdef CONFIG_HUGETLB_PAGE
526 /* Reserve 16G huge page memory sections for huge pages */
527 of_scan_flat_dt(htab_dt_scan_hugepage_blocks
, NULL
);
528 #endif /* CONFIG_HUGETLB_PAGE */
531 static int __init
htab_dt_scan_pftsize(unsigned long node
,
532 const char *uname
, int depth
,
535 char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
538 /* We are scanning "cpu" nodes only */
539 if (type
== NULL
|| strcmp(type
, "cpu") != 0)
542 prop
= (u32
*)of_get_flat_dt_prop(node
, "ibm,pft-size", NULL
);
544 /* pft_size[0] is the NUMA CEC cookie */
545 ppc64_pft_size
= prop
[1];
551 static unsigned long __init
htab_get_table_size(void)
553 unsigned long mem_size
, rnd_mem_size
, pteg_count
, psize
;
555 /* If hash size isn't already provided by the platform, we try to
556 * retrieve it from the device-tree. If it's not there neither, we
557 * calculate it now based on the total RAM size
559 if (ppc64_pft_size
== 0)
560 of_scan_flat_dt(htab_dt_scan_pftsize
, NULL
);
562 return 1UL << ppc64_pft_size
;
564 /* round mem_size up to next power of 2 */
565 mem_size
= memblock_phys_mem_size();
566 rnd_mem_size
= 1UL << __ilog2(mem_size
);
567 if (rnd_mem_size
< mem_size
)
571 psize
= mmu_psize_defs
[mmu_virtual_psize
].shift
;
572 pteg_count
= max(rnd_mem_size
>> (psize
+ 1), 1UL << 11);
574 return pteg_count
<< 7;
577 #ifdef CONFIG_MEMORY_HOTPLUG
578 int create_section_mapping(unsigned long start
, unsigned long end
)
580 return htab_bolt_mapping(start
, end
, __pa(start
),
581 pgprot_val(PAGE_KERNEL
), mmu_linear_psize
,
585 int remove_section_mapping(unsigned long start
, unsigned long end
)
587 return htab_remove_mapping(start
, end
, mmu_linear_psize
,
590 #endif /* CONFIG_MEMORY_HOTPLUG */
592 #define FUNCTION_TEXT(A) ((*(unsigned long *)(A)))
594 static void __init
htab_finish_init(void)
596 extern unsigned int *htab_call_hpte_insert1
;
597 extern unsigned int *htab_call_hpte_insert2
;
598 extern unsigned int *htab_call_hpte_remove
;
599 extern unsigned int *htab_call_hpte_updatepp
;
601 #ifdef CONFIG_PPC_HAS_HASH_64K
602 extern unsigned int *ht64_call_hpte_insert1
;
603 extern unsigned int *ht64_call_hpte_insert2
;
604 extern unsigned int *ht64_call_hpte_remove
;
605 extern unsigned int *ht64_call_hpte_updatepp
;
607 patch_branch(ht64_call_hpte_insert1
,
608 FUNCTION_TEXT(ppc_md
.hpte_insert
),
610 patch_branch(ht64_call_hpte_insert2
,
611 FUNCTION_TEXT(ppc_md
.hpte_insert
),
613 patch_branch(ht64_call_hpte_remove
,
614 FUNCTION_TEXT(ppc_md
.hpte_remove
),
616 patch_branch(ht64_call_hpte_updatepp
,
617 FUNCTION_TEXT(ppc_md
.hpte_updatepp
),
620 #endif /* CONFIG_PPC_HAS_HASH_64K */
622 patch_branch(htab_call_hpte_insert1
,
623 FUNCTION_TEXT(ppc_md
.hpte_insert
),
625 patch_branch(htab_call_hpte_insert2
,
626 FUNCTION_TEXT(ppc_md
.hpte_insert
),
628 patch_branch(htab_call_hpte_remove
,
629 FUNCTION_TEXT(ppc_md
.hpte_remove
),
631 patch_branch(htab_call_hpte_updatepp
,
632 FUNCTION_TEXT(ppc_md
.hpte_updatepp
),
636 static void __init
htab_initialize(void)
639 unsigned long pteg_count
;
641 unsigned long base
= 0, size
= 0, limit
;
642 struct memblock_region
*reg
;
644 DBG(" -> htab_initialize()\n");
646 /* Initialize segment sizes */
647 htab_init_seg_sizes();
649 /* Initialize page sizes */
650 htab_init_page_sizes();
652 if (mmu_has_feature(MMU_FTR_1T_SEGMENT
)) {
653 mmu_kernel_ssize
= MMU_SEGSIZE_1T
;
654 mmu_highuser_ssize
= MMU_SEGSIZE_1T
;
655 printk(KERN_INFO
"Using 1TB segments\n");
659 * Calculate the required size of the htab. We want the number of
660 * PTEGs to equal one half the number of real pages.
662 htab_size_bytes
= htab_get_table_size();
663 pteg_count
= htab_size_bytes
>> 7;
665 htab_hash_mask
= pteg_count
- 1;
667 if (firmware_has_feature(FW_FEATURE_LPAR
)) {
668 /* Using a hypervisor which owns the htab */
671 #ifdef CONFIG_FA_DUMP
673 * If firmware assisted dump is active firmware preserves
674 * the contents of htab along with entire partition memory.
675 * Clear the htab if firmware assisted dump is active so
676 * that we dont end up using old mappings.
678 if (is_fadump_active() && ppc_md
.hpte_clear_all
)
679 ppc_md
.hpte_clear_all();
682 /* Find storage for the HPT. Must be contiguous in
683 * the absolute address space. On cell we want it to be
684 * in the first 2 Gig so we can use it for IOMMU hacks.
686 if (machine_is(cell
))
689 limit
= MEMBLOCK_ALLOC_ANYWHERE
;
691 table
= memblock_alloc_base(htab_size_bytes
, htab_size_bytes
, limit
);
693 DBG("Hash table allocated at %lx, size: %lx\n", table
,
696 htab_address
= __va(table
);
698 /* htab absolute addr + encoded htabsize */
699 _SDR1
= table
+ __ilog2(pteg_count
) - 11;
701 /* Initialize the HPT with no entries */
702 memset((void *)table
, 0, htab_size_bytes
);
705 mtspr(SPRN_SDR1
, _SDR1
);
708 prot
= pgprot_val(PAGE_KERNEL
);
710 #ifdef CONFIG_DEBUG_PAGEALLOC
711 linear_map_hash_count
= memblock_end_of_DRAM() >> PAGE_SHIFT
;
712 linear_map_hash_slots
= __va(memblock_alloc_base(linear_map_hash_count
,
714 memset(linear_map_hash_slots
, 0, linear_map_hash_count
);
715 #endif /* CONFIG_DEBUG_PAGEALLOC */
717 /* On U3 based machines, we need to reserve the DART area and
718 * _NOT_ map it to avoid cache paradoxes as it's remapped non
722 /* create bolted the linear mapping in the hash table */
723 for_each_memblock(memory
, reg
) {
724 base
= (unsigned long)__va(reg
->base
);
727 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
730 #ifdef CONFIG_U3_DART
731 /* Do not map the DART space. Fortunately, it will be aligned
732 * in such a way that it will not cross two memblock regions and
733 * will fit within a single 16Mb page.
734 * The DART space is assumed to be a full 16Mb region even if
735 * we only use 2Mb of that space. We will use more of it later
736 * for AGP GART. We have to use a full 16Mb large page.
738 DBG("DART base: %lx\n", dart_tablebase
);
740 if (dart_tablebase
!= 0 && dart_tablebase
>= base
741 && dart_tablebase
< (base
+ size
)) {
742 unsigned long dart_table_end
= dart_tablebase
+ 16 * MB
;
743 if (base
!= dart_tablebase
)
744 BUG_ON(htab_bolt_mapping(base
, dart_tablebase
,
748 if ((base
+ size
) > dart_table_end
)
749 BUG_ON(htab_bolt_mapping(dart_tablebase
+16*MB
,
751 __pa(dart_table_end
),
757 #endif /* CONFIG_U3_DART */
758 BUG_ON(htab_bolt_mapping(base
, base
+ size
, __pa(base
),
759 prot
, mmu_linear_psize
, mmu_kernel_ssize
));
761 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE
);
764 * If we have a memory_limit and we've allocated TCEs then we need to
765 * explicitly map the TCE area at the top of RAM. We also cope with the
766 * case that the TCEs start below memory_limit.
767 * tce_alloc_start/end are 16MB aligned so the mapping should work
768 * for either 4K or 16MB pages.
770 if (tce_alloc_start
) {
771 tce_alloc_start
= (unsigned long)__va(tce_alloc_start
);
772 tce_alloc_end
= (unsigned long)__va(tce_alloc_end
);
774 if (base
+ size
>= tce_alloc_start
)
775 tce_alloc_start
= base
+ size
+ 1;
777 BUG_ON(htab_bolt_mapping(tce_alloc_start
, tce_alloc_end
,
778 __pa(tce_alloc_start
), prot
,
779 mmu_linear_psize
, mmu_kernel_ssize
));
784 DBG(" <- htab_initialize()\n");
789 void __init
early_init_mmu(void)
791 /* Setup initial STAB address in the PACA */
792 get_paca()->stab_real
= __pa((u64
)&initial_stab
);
793 get_paca()->stab_addr
= (u64
)&initial_stab
;
795 /* Initialize the MMU Hash table and create the linear mapping
796 * of memory. Has to be done before stab/slb initialization as
797 * this is currently where the page size encoding is obtained
801 /* Initialize stab / SLB management */
802 if (mmu_has_feature(MMU_FTR_SLB
))
805 stab_initialize(get_paca()->stab_real
);
809 void __cpuinit
early_init_mmu_secondary(void)
811 /* Initialize hash table for that CPU */
812 if (!firmware_has_feature(FW_FEATURE_LPAR
))
813 mtspr(SPRN_SDR1
, _SDR1
);
815 /* Initialize STAB/SLB. We use a virtual address as it works
816 * in real mode on pSeries.
818 if (mmu_has_feature(MMU_FTR_SLB
))
821 stab_initialize(get_paca()->stab_addr
);
823 #endif /* CONFIG_SMP */
826 * Called by asm hashtable.S for doing lazy icache flush
828 unsigned int hash_page_do_lazy_icache(unsigned int pp
, pte_t pte
, int trap
)
832 if (!pfn_valid(pte_pfn(pte
)))
835 page
= pte_page(pte
);
838 if (!test_bit(PG_arch_1
, &page
->flags
) && !PageReserved(page
)) {
840 flush_dcache_icache_page(page
);
841 set_bit(PG_arch_1
, &page
->flags
);
848 #ifdef CONFIG_PPC_MM_SLICES
849 unsigned int get_paca_psize(unsigned long addr
)
852 unsigned char *hpsizes
;
853 unsigned long index
, mask_index
;
855 if (addr
< SLICE_LOW_TOP
) {
856 lpsizes
= get_paca()->context
.low_slices_psize
;
857 index
= GET_LOW_SLICE_INDEX(addr
);
858 return (lpsizes
>> (index
* 4)) & 0xF;
860 hpsizes
= get_paca()->context
.high_slices_psize
;
861 index
= GET_HIGH_SLICE_INDEX(addr
);
862 mask_index
= index
& 0x1;
863 return (hpsizes
[index
>> 1] >> (mask_index
* 4)) & 0xF;
867 unsigned int get_paca_psize(unsigned long addr
)
869 return get_paca()->context
.user_psize
;
874 * Demote a segment to using 4k pages.
875 * For now this makes the whole process use 4k pages.
877 #ifdef CONFIG_PPC_64K_PAGES
878 void demote_segment_4k(struct mm_struct
*mm
, unsigned long addr
)
880 if (get_slice_psize(mm
, addr
) == MMU_PAGE_4K
)
882 slice_set_range_psize(mm
, addr
, 1, MMU_PAGE_4K
);
883 #ifdef CONFIG_SPU_BASE
884 spu_flush_all_slbs(mm
);
886 if (get_paca_psize(addr
) != MMU_PAGE_4K
) {
887 get_paca()->context
= mm
->context
;
888 slb_flush_and_rebolt();
891 #endif /* CONFIG_PPC_64K_PAGES */
893 #ifdef CONFIG_PPC_SUBPAGE_PROT
895 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
896 * Userspace sets the subpage permissions using the subpage_prot system call.
898 * Result is 0: full permissions, _PAGE_RW: read-only,
899 * _PAGE_USER or _PAGE_USER|_PAGE_RW: no access.
901 static int subpage_protection(struct mm_struct
*mm
, unsigned long ea
)
903 struct subpage_prot_table
*spt
= &mm
->context
.spt
;
907 if (ea
>= spt
->maxaddr
)
909 if (ea
< 0x100000000) {
910 /* addresses below 4GB use spt->low_prot */
911 sbpm
= spt
->low_prot
;
913 sbpm
= spt
->protptrs
[ea
>> SBP_L3_SHIFT
];
917 sbpp
= sbpm
[(ea
>> SBP_L2_SHIFT
) & (SBP_L2_COUNT
- 1)];
920 spp
= sbpp
[(ea
>> PAGE_SHIFT
) & (SBP_L1_COUNT
- 1)];
922 /* extract 2-bit bitfield for this 4k subpage */
923 spp
>>= 30 - 2 * ((ea
>> 12) & 0xf);
925 /* turn 0,1,2,3 into combination of _PAGE_USER and _PAGE_RW */
926 spp
= ((spp
& 2) ? _PAGE_USER
: 0) | ((spp
& 1) ? _PAGE_RW
: 0);
930 #else /* CONFIG_PPC_SUBPAGE_PROT */
931 static inline int subpage_protection(struct mm_struct
*mm
, unsigned long ea
)
937 void hash_failure_debug(unsigned long ea
, unsigned long access
,
938 unsigned long vsid
, unsigned long trap
,
939 int ssize
, int psize
, int lpsize
, unsigned long pte
)
941 if (!printk_ratelimit())
943 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
944 ea
, access
, current
->comm
);
945 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
946 trap
, vsid
, ssize
, psize
, lpsize
, pte
);
951 * 1 - normal page fault
952 * -1 - critical hash insertion error
953 * -2 - access not permitted by subpage protection mechanism
955 int hash_page(unsigned long ea
, unsigned long access
, unsigned long trap
)
959 struct mm_struct
*mm
;
962 const struct cpumask
*tmp
;
963 int rc
, user_region
= 0, local
= 0;
966 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
969 /* Get region & vsid */
970 switch (REGION_ID(ea
)) {
975 DBG_LOW(" user region with no mm !\n");
978 psize
= get_slice_psize(mm
, ea
);
979 ssize
= user_segment_size(ea
);
980 vsid
= get_vsid(mm
->context
.id
, ea
, ssize
);
982 case VMALLOC_REGION_ID
:
984 vsid
= get_kernel_vsid(ea
, mmu_kernel_ssize
);
985 if (ea
< VMALLOC_END
)
986 psize
= mmu_vmalloc_psize
;
988 psize
= mmu_io_psize
;
989 ssize
= mmu_kernel_ssize
;
993 * Send the problem up to do_page_fault
997 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm
, mm
->pgd
, vsid
);
1001 DBG_LOW("Bad address!\n");
1009 /* Check CPU locality */
1010 tmp
= cpumask_of(smp_processor_id());
1011 if (user_region
&& cpumask_equal(mm_cpumask(mm
), tmp
))
1014 #ifndef CONFIG_PPC_64K_PAGES
1015 /* If we use 4K pages and our psize is not 4K, then we might
1016 * be hitting a special driver mapping, and need to align the
1017 * address before we fetch the PTE.
1019 * It could also be a hugepage mapping, in which case this is
1020 * not necessary, but it's not harmful, either.
1022 if (psize
!= MMU_PAGE_4K
)
1023 ea
&= ~((1ul << mmu_psize_defs
[psize
].shift
) - 1);
1024 #endif /* CONFIG_PPC_64K_PAGES */
1026 /* Get PTE and page size from page tables */
1027 ptep
= find_linux_pte_or_hugepte(pgdir
, ea
, &hugeshift
);
1028 if (ptep
== NULL
|| !pte_present(*ptep
)) {
1029 DBG_LOW(" no PTE !\n");
1033 /* Add _PAGE_PRESENT to the required access perm */
1034 access
|= _PAGE_PRESENT
;
1036 /* Pre-check access permissions (will be re-checked atomically
1037 * in __hash_page_XX but this pre-check is a fast path
1039 if (access
& ~pte_val(*ptep
)) {
1040 DBG_LOW(" no access !\n");
1044 #ifdef CONFIG_HUGETLB_PAGE
1046 return __hash_page_huge(ea
, access
, vsid
, ptep
, trap
, local
,
1047 ssize
, hugeshift
, psize
);
1048 #endif /* CONFIG_HUGETLB_PAGE */
1050 #ifndef CONFIG_PPC_64K_PAGES
1051 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep
));
1053 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep
),
1054 pte_val(*(ptep
+ PTRS_PER_PTE
)));
1056 /* Do actual hashing */
1057 #ifdef CONFIG_PPC_64K_PAGES
1058 /* If _PAGE_4K_PFN is set, make sure this is a 4k segment */
1059 if ((pte_val(*ptep
) & _PAGE_4K_PFN
) && psize
== MMU_PAGE_64K
) {
1060 demote_segment_4k(mm
, ea
);
1061 psize
= MMU_PAGE_4K
;
1064 /* If this PTE is non-cacheable and we have restrictions on
1065 * using non cacheable large pages, then we switch to 4k
1067 if (mmu_ci_restrictions
&& psize
== MMU_PAGE_64K
&&
1068 (pte_val(*ptep
) & _PAGE_NO_CACHE
)) {
1070 demote_segment_4k(mm
, ea
);
1071 psize
= MMU_PAGE_4K
;
1072 } else if (ea
< VMALLOC_END
) {
1074 * some driver did a non-cacheable mapping
1075 * in vmalloc space, so switch vmalloc
1078 printk(KERN_ALERT
"Reducing vmalloc segment "
1079 "to 4kB pages because of "
1080 "non-cacheable mapping\n");
1081 psize
= mmu_vmalloc_psize
= MMU_PAGE_4K
;
1082 #ifdef CONFIG_SPU_BASE
1083 spu_flush_all_slbs(mm
);
1088 if (psize
!= get_paca_psize(ea
)) {
1089 get_paca()->context
= mm
->context
;
1090 slb_flush_and_rebolt();
1092 } else if (get_paca()->vmalloc_sllp
!=
1093 mmu_psize_defs
[mmu_vmalloc_psize
].sllp
) {
1094 get_paca()->vmalloc_sllp
=
1095 mmu_psize_defs
[mmu_vmalloc_psize
].sllp
;
1096 slb_vmalloc_update();
1098 #endif /* CONFIG_PPC_64K_PAGES */
1100 #ifdef CONFIG_PPC_HAS_HASH_64K
1101 if (psize
== MMU_PAGE_64K
)
1102 rc
= __hash_page_64K(ea
, access
, vsid
, ptep
, trap
, local
, ssize
);
1104 #endif /* CONFIG_PPC_HAS_HASH_64K */
1106 int spp
= subpage_protection(mm
, ea
);
1110 rc
= __hash_page_4K(ea
, access
, vsid
, ptep
, trap
,
1114 /* Dump some info in case of hash insertion failure, they should
1115 * never happen so it is really useful to know if/when they do
1118 hash_failure_debug(ea
, access
, vsid
, trap
, ssize
, psize
,
1119 psize
, pte_val(*ptep
));
1120 #ifndef CONFIG_PPC_64K_PAGES
1121 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep
));
1123 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep
),
1124 pte_val(*(ptep
+ PTRS_PER_PTE
)));
1126 DBG_LOW(" -> rc=%d\n", rc
);
1129 EXPORT_SYMBOL_GPL(hash_page
);
1131 void hash_preload(struct mm_struct
*mm
, unsigned long ea
,
1132 unsigned long access
, unsigned long trap
)
1137 unsigned long flags
;
1138 int rc
, ssize
, local
= 0;
1140 BUG_ON(REGION_ID(ea
) != USER_REGION_ID
);
1142 #ifdef CONFIG_PPC_MM_SLICES
1143 /* We only prefault standard pages for now */
1144 if (unlikely(get_slice_psize(mm
, ea
) != mm
->context
.user_psize
))
1148 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1149 " trap=%lx\n", mm
, mm
->pgd
, ea
, access
, trap
);
1151 /* Get Linux PTE if available */
1155 ptep
= find_linux_pte(pgdir
, ea
);
1159 #ifdef CONFIG_PPC_64K_PAGES
1160 /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
1161 * a 64K kernel), then we don't preload, hash_page() will take
1162 * care of it once we actually try to access the page.
1163 * That way we don't have to duplicate all of the logic for segment
1164 * page size demotion here
1166 if (pte_val(*ptep
) & (_PAGE_4K_PFN
| _PAGE_NO_CACHE
))
1168 #endif /* CONFIG_PPC_64K_PAGES */
1171 ssize
= user_segment_size(ea
);
1172 vsid
= get_vsid(mm
->context
.id
, ea
, ssize
);
1176 /* Hash doesn't like irqs */
1177 local_irq_save(flags
);
1179 /* Is that local to this CPU ? */
1180 if (cpumask_equal(mm_cpumask(mm
), cpumask_of(smp_processor_id())))
1184 #ifdef CONFIG_PPC_HAS_HASH_64K
1185 if (mm
->context
.user_psize
== MMU_PAGE_64K
)
1186 rc
= __hash_page_64K(ea
, access
, vsid
, ptep
, trap
, local
, ssize
);
1188 #endif /* CONFIG_PPC_HAS_HASH_64K */
1189 rc
= __hash_page_4K(ea
, access
, vsid
, ptep
, trap
, local
, ssize
,
1190 subpage_protection(mm
, ea
));
1192 /* Dump some info in case of hash insertion failure, they should
1193 * never happen so it is really useful to know if/when they do
1196 hash_failure_debug(ea
, access
, vsid
, trap
, ssize
,
1197 mm
->context
.user_psize
,
1198 mm
->context
.user_psize
,
1201 local_irq_restore(flags
);
1204 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1205 * do not forget to update the assembly call site !
1207 void flush_hash_page(unsigned long vpn
, real_pte_t pte
, int psize
, int ssize
,
1210 unsigned long hash
, index
, shift
, hidx
, slot
;
1212 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn
);
1213 pte_iterate_hashed_subpages(pte
, psize
, vpn
, index
, shift
) {
1214 hash
= hpt_hash(vpn
, shift
, ssize
);
1215 hidx
= __rpte_to_hidx(pte
, index
);
1216 if (hidx
& _PTEIDX_SECONDARY
)
1218 slot
= (hash
& htab_hash_mask
) * HPTES_PER_GROUP
;
1219 slot
+= hidx
& _PTEIDX_GROUP_IX
;
1220 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index
, slot
, hidx
);
1221 ppc_md
.hpte_invalidate(slot
, vpn
, psize
, ssize
, local
);
1222 } pte_iterate_hashed_end();
1224 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1225 /* Transactions are not aborted by tlbiel, only tlbie.
1226 * Without, syncing a page back to a block device w/ PIO could pick up
1227 * transactional data (bad!) so we force an abort here. Before the
1228 * sync the page will be made read-only, which will flush_hash_page.
1229 * BIG ISSUE here: if the kernel uses a page from userspace without
1230 * unmapping it first, it may see the speculated version.
1232 if (local
&& cpu_has_feature(CPU_FTR_TM
) &&
1233 current
->thread
.regs
&&
1234 MSR_TM_ACTIVE(current
->thread
.regs
->msr
)) {
1236 tm_abort(TM_CAUSE_TLBI
);
1241 void flush_hash_range(unsigned long number
, int local
)
1243 if (ppc_md
.flush_hash_range
)
1244 ppc_md
.flush_hash_range(number
, local
);
1247 struct ppc64_tlb_batch
*batch
=
1248 &__get_cpu_var(ppc64_tlb_batch
);
1250 for (i
= 0; i
< number
; i
++)
1251 flush_hash_page(batch
->vpn
[i
], batch
->pte
[i
],
1252 batch
->psize
, batch
->ssize
, local
);
1257 * low_hash_fault is called when we the low level hash code failed
1258 * to instert a PTE due to an hypervisor error
1260 void low_hash_fault(struct pt_regs
*regs
, unsigned long address
, int rc
)
1262 if (user_mode(regs
)) {
1263 #ifdef CONFIG_PPC_SUBPAGE_PROT
1265 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, address
);
1268 _exception(SIGBUS
, regs
, BUS_ADRERR
, address
);
1270 bad_page_fault(regs
, address
, SIGBUS
);
1273 long hpte_insert_repeating(unsigned long hash
, unsigned long vpn
,
1274 unsigned long pa
, unsigned long rflags
,
1275 unsigned long vflags
, int psize
, int ssize
)
1277 unsigned long hpte_group
;
1281 hpte_group
= ((hash
& htab_hash_mask
) *
1282 HPTES_PER_GROUP
) & ~0x7UL
;
1284 /* Insert into the hash table, primary slot */
1285 slot
= ppc_md
.hpte_insert(hpte_group
, vpn
, pa
, rflags
, vflags
,
1286 psize
, psize
, ssize
);
1288 /* Primary is full, try the secondary */
1289 if (unlikely(slot
== -1)) {
1290 hpte_group
= ((~hash
& htab_hash_mask
) *
1291 HPTES_PER_GROUP
) & ~0x7UL
;
1292 slot
= ppc_md
.hpte_insert(hpte_group
, vpn
, pa
, rflags
,
1293 vflags
| HPTE_V_SECONDARY
,
1294 psize
, psize
, ssize
);
1297 hpte_group
= ((hash
& htab_hash_mask
) *
1298 HPTES_PER_GROUP
)&~0x7UL
;
1300 ppc_md
.hpte_remove(hpte_group
);
1308 #ifdef CONFIG_DEBUG_PAGEALLOC
1309 static void kernel_map_linear_page(unsigned long vaddr
, unsigned long lmi
)
1312 unsigned long vsid
= get_kernel_vsid(vaddr
, mmu_kernel_ssize
);
1313 unsigned long vpn
= hpt_vpn(vaddr
, vsid
, mmu_kernel_ssize
);
1314 unsigned long mode
= htab_convert_pte_flags(PAGE_KERNEL
);
1317 hash
= hpt_hash(vpn
, PAGE_SHIFT
, mmu_kernel_ssize
);
1319 /* Don't create HPTE entries for bad address */
1323 ret
= hpte_insert_repeating(hash
, vpn
, __pa(vaddr
), mode
,
1325 mmu_linear_psize
, mmu_kernel_ssize
);
1328 spin_lock(&linear_map_hash_lock
);
1329 BUG_ON(linear_map_hash_slots
[lmi
] & 0x80);
1330 linear_map_hash_slots
[lmi
] = ret
| 0x80;
1331 spin_unlock(&linear_map_hash_lock
);
1334 static void kernel_unmap_linear_page(unsigned long vaddr
, unsigned long lmi
)
1336 unsigned long hash
, hidx
, slot
;
1337 unsigned long vsid
= get_kernel_vsid(vaddr
, mmu_kernel_ssize
);
1338 unsigned long vpn
= hpt_vpn(vaddr
, vsid
, mmu_kernel_ssize
);
1340 hash
= hpt_hash(vpn
, PAGE_SHIFT
, mmu_kernel_ssize
);
1341 spin_lock(&linear_map_hash_lock
);
1342 BUG_ON(!(linear_map_hash_slots
[lmi
] & 0x80));
1343 hidx
= linear_map_hash_slots
[lmi
] & 0x7f;
1344 linear_map_hash_slots
[lmi
] = 0;
1345 spin_unlock(&linear_map_hash_lock
);
1346 if (hidx
& _PTEIDX_SECONDARY
)
1348 slot
= (hash
& htab_hash_mask
) * HPTES_PER_GROUP
;
1349 slot
+= hidx
& _PTEIDX_GROUP_IX
;
1350 ppc_md
.hpte_invalidate(slot
, vpn
, mmu_linear_psize
, mmu_kernel_ssize
, 0);
1353 void kernel_map_pages(struct page
*page
, int numpages
, int enable
)
1355 unsigned long flags
, vaddr
, lmi
;
1358 local_irq_save(flags
);
1359 for (i
= 0; i
< numpages
; i
++, page
++) {
1360 vaddr
= (unsigned long)page_address(page
);
1361 lmi
= __pa(vaddr
) >> PAGE_SHIFT
;
1362 if (lmi
>= linear_map_hash_count
)
1365 kernel_map_linear_page(vaddr
, lmi
);
1367 kernel_unmap_linear_page(vaddr
, lmi
);
1369 local_irq_restore(flags
);
1371 #endif /* CONFIG_DEBUG_PAGEALLOC */
1373 void setup_initial_memory_limit(phys_addr_t first_memblock_base
,
1374 phys_addr_t first_memblock_size
)
1376 /* We don't currently support the first MEMBLOCK not mapping 0
1377 * physical on those processors
1379 BUG_ON(first_memblock_base
!= 0);
1381 /* On LPAR systems, the first entry is our RMA region,
1382 * non-LPAR 64-bit hash MMU systems don't have a limitation
1383 * on real mode access, but using the first entry works well
1384 * enough. We also clamp it to 1G to avoid some funky things
1385 * such as RTAS bugs etc...
1387 ppc64_rma_size
= min_t(u64
, first_memblock_size
, 0x40000000);
1389 /* Finally limit subsequent allocations */
1390 memblock_set_current_limit(ppc64_rma_size
);