2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <linux/config.h>
25 #include <linux/spinlock.h>
26 #include <linux/errno.h>
27 #include <linux/sched.h>
28 #include <linux/proc_fs.h>
29 #include <linux/stat.h>
30 #include <linux/sysctl.h>
31 #include <linux/ctype.h>
32 #include <linux/cache.h>
33 #include <linux/init.h>
34 #include <linux/signal.h>
36 #include <asm/processor.h>
37 #include <asm/pgtable.h>
39 #include <asm/mmu_context.h>
41 #include <asm/types.h>
42 #include <asm/system.h>
43 #include <asm/uaccess.h>
44 #include <asm/machdep.h>
46 #include <asm/abs_addr.h>
47 #include <asm/tlbflush.h>
51 #include <asm/cacheflush.h>
52 #include <asm/cputable.h>
53 #include <asm/abs_addr.h>
54 #include <asm/sections.h>
57 #define DBG(fmt...) udbg_printf(fmt)
63 #define DBG_LOW(fmt...) udbg_printf(fmt)
65 #define DBG_LOW(fmt...)
72 * Note: pte --> Linux PTE
73 * HPTE --> PowerPC Hashed Page Table Entry
76 * htab_initialize is called with the MMU off (of course), but
77 * the kernel has been copied down to zero so it can directly
78 * reference global data. At this point it is very difficult
79 * to print debug info.
84 extern unsigned long dart_tablebase
;
85 #endif /* CONFIG_U3_DART */
87 static unsigned long _SDR1
;
88 struct mmu_psize_def mmu_psize_defs
[MMU_PAGE_COUNT
];
91 unsigned long htab_size_bytes
;
92 unsigned long htab_hash_mask
;
93 int mmu_linear_psize
= MMU_PAGE_4K
;
94 int mmu_virtual_psize
= MMU_PAGE_4K
;
95 int mmu_vmalloc_psize
= MMU_PAGE_4K
;
96 int mmu_io_psize
= MMU_PAGE_4K
;
97 #ifdef CONFIG_HUGETLB_PAGE
98 int mmu_huge_psize
= MMU_PAGE_16M
;
99 unsigned int HPAGE_SHIFT
;
101 #ifdef CONFIG_PPC_64K_PAGES
102 int mmu_ci_restrictions
;
105 /* There are definitions of page sizes arrays to be used when none
106 * is provided by the firmware.
109 /* Pre-POWER4 CPUs (4k pages only)
111 struct mmu_psize_def mmu_psize_defaults_old
[] = {
121 /* POWER4, GPUL, POWER5
123 * Support for 16Mb large pages
125 struct mmu_psize_def mmu_psize_defaults_gp
[] = {
143 int htab_bolt_mapping(unsigned long vstart
, unsigned long vend
,
144 unsigned long pstart
, unsigned long mode
, int psize
)
146 unsigned long vaddr
, paddr
;
147 unsigned int step
, shift
;
148 unsigned long tmp_mode
;
151 shift
= mmu_psize_defs
[psize
].shift
;
154 for (vaddr
= vstart
, paddr
= pstart
; vaddr
< vend
;
155 vaddr
+= step
, paddr
+= step
) {
156 unsigned long vpn
, hash
, hpteg
;
157 unsigned long vsid
= get_kernel_vsid(vaddr
);
158 unsigned long va
= (vsid
<< 28) | (vaddr
& 0x0fffffff);
163 /* Make non-kernel text non-executable */
164 if (!in_kernel_text(vaddr
))
165 tmp_mode
= mode
| HPTE_R_N
;
167 hash
= hpt_hash(va
, shift
);
168 hpteg
= ((hash
& htab_hash_mask
) * HPTES_PER_GROUP
);
170 /* The crap below can be cleaned once ppd_md.probe() can
171 * set up the hash callbacks, thus we can just used the
172 * normal insert callback here.
174 #ifdef CONFIG_PPC_ISERIES
175 if (machine_is(iseries
))
176 ret
= iSeries_hpte_insert(hpteg
, va
,
183 #ifdef CONFIG_PPC_PSERIES
184 if (machine_is(pseries
) && firmware_has_feature(FW_FEATURE_LPAR
))
185 ret
= pSeries_lpar_hpte_insert(hpteg
, va
,
192 #ifdef CONFIG_PPC_MULTIPLATFORM
193 ret
= native_hpte_insert(hpteg
, va
,
195 tmp_mode
, HPTE_V_BOLTED
,
201 return ret
< 0 ? ret
: 0;
204 static int __init
htab_dt_scan_page_sizes(unsigned long node
,
205 const char *uname
, int depth
,
208 char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
210 unsigned long size
= 0;
212 /* We are scanning "cpu" nodes only */
213 if (type
== NULL
|| strcmp(type
, "cpu") != 0)
216 prop
= (u32
*)of_get_flat_dt_prop(node
,
217 "ibm,segment-page-sizes", &size
);
219 DBG("Page sizes from device-tree:\n");
221 cur_cpu_spec
->cpu_features
&= ~(CPU_FTR_16M_PAGE
);
223 unsigned int shift
= prop
[0];
224 unsigned int slbenc
= prop
[1];
225 unsigned int lpnum
= prop
[2];
226 unsigned int lpenc
= 0;
227 struct mmu_psize_def
*def
;
230 size
-= 3; prop
+= 3;
231 while(size
> 0 && lpnum
) {
232 if (prop
[0] == shift
)
234 prop
+= 2; size
-= 2;
249 cur_cpu_spec
->cpu_features
|= CPU_FTR_16M_PAGE
;
257 def
= &mmu_psize_defs
[idx
];
262 def
->avpnm
= (1 << (shift
- 23)) - 1;
265 /* We don't know for sure what's up with tlbiel, so
266 * for now we only set it for 4K and 64K pages
268 if (idx
== MMU_PAGE_4K
|| idx
== MMU_PAGE_64K
)
273 DBG(" %d: shift=%02x, sllp=%04x, avpnm=%08x, "
274 "tlbiel=%d, penc=%d\n",
275 idx
, shift
, def
->sllp
, def
->avpnm
, def
->tlbiel
,
284 static void __init
htab_init_page_sizes(void)
288 /* Default to 4K pages only */
289 memcpy(mmu_psize_defs
, mmu_psize_defaults_old
,
290 sizeof(mmu_psize_defaults_old
));
293 * Try to find the available page sizes in the device-tree
295 rc
= of_scan_flat_dt(htab_dt_scan_page_sizes
, NULL
);
296 if (rc
!= 0) /* Found */
300 * Not in the device-tree, let's fallback on known size
301 * list for 16M capable GP & GR
303 if (cpu_has_feature(CPU_FTR_16M_PAGE
) && !machine_is(iseries
))
304 memcpy(mmu_psize_defs
, mmu_psize_defaults_gp
,
305 sizeof(mmu_psize_defaults_gp
));
308 * Pick a size for the linear mapping. Currently, we only support
309 * 16M, 1M and 4K which is the default
311 if (mmu_psize_defs
[MMU_PAGE_16M
].shift
)
312 mmu_linear_psize
= MMU_PAGE_16M
;
313 else if (mmu_psize_defs
[MMU_PAGE_1M
].shift
)
314 mmu_linear_psize
= MMU_PAGE_1M
;
316 #ifdef CONFIG_PPC_64K_PAGES
318 * Pick a size for the ordinary pages. Default is 4K, we support
319 * 64K for user mappings and vmalloc if supported by the processor.
320 * We only use 64k for ioremap if the processor
321 * (and firmware) support cache-inhibited large pages.
322 * If not, we use 4k and set mmu_ci_restrictions so that
323 * hash_page knows to switch processes that use cache-inhibited
324 * mappings to 4k pages.
326 if (mmu_psize_defs
[MMU_PAGE_64K
].shift
) {
327 mmu_virtual_psize
= MMU_PAGE_64K
;
328 mmu_vmalloc_psize
= MMU_PAGE_64K
;
329 if (cpu_has_feature(CPU_FTR_CI_LARGE_PAGE
))
330 mmu_io_psize
= MMU_PAGE_64K
;
332 mmu_ci_restrictions
= 1;
336 printk(KERN_DEBUG
"Page orders: linear mapping = %d, "
337 "virtual = %d, io = %d\n",
338 mmu_psize_defs
[mmu_linear_psize
].shift
,
339 mmu_psize_defs
[mmu_virtual_psize
].shift
,
340 mmu_psize_defs
[mmu_io_psize
].shift
);
342 #ifdef CONFIG_HUGETLB_PAGE
343 /* Init large page size. Currently, we pick 16M or 1M depending
344 * on what is available
346 if (mmu_psize_defs
[MMU_PAGE_16M
].shift
)
347 mmu_huge_psize
= MMU_PAGE_16M
;
348 /* With 4k/4level pagetables, we can't (for now) cope with a
349 * huge page size < PMD_SIZE */
350 else if (mmu_psize_defs
[MMU_PAGE_1M
].shift
)
351 mmu_huge_psize
= MMU_PAGE_1M
;
353 /* Calculate HPAGE_SHIFT and sanity check it */
354 if (mmu_psize_defs
[mmu_huge_psize
].shift
> MIN_HUGEPTE_SHIFT
&&
355 mmu_psize_defs
[mmu_huge_psize
].shift
< SID_SHIFT
)
356 HPAGE_SHIFT
= mmu_psize_defs
[mmu_huge_psize
].shift
;
358 HPAGE_SHIFT
= 0; /* No huge pages dude ! */
359 #endif /* CONFIG_HUGETLB_PAGE */
362 static int __init
htab_dt_scan_pftsize(unsigned long node
,
363 const char *uname
, int depth
,
366 char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
369 /* We are scanning "cpu" nodes only */
370 if (type
== NULL
|| strcmp(type
, "cpu") != 0)
373 prop
= (u32
*)of_get_flat_dt_prop(node
, "ibm,pft-size", NULL
);
375 /* pft_size[0] is the NUMA CEC cookie */
376 ppc64_pft_size
= prop
[1];
382 static unsigned long __init
htab_get_table_size(void)
384 unsigned long mem_size
, rnd_mem_size
, pteg_count
;
386 /* If hash size isn't already provided by the platform, we try to
387 * retrieve it from the device-tree. If it's not there neither, we
388 * calculate it now based on the total RAM size
390 if (ppc64_pft_size
== 0)
391 of_scan_flat_dt(htab_dt_scan_pftsize
, NULL
);
393 return 1UL << ppc64_pft_size
;
395 /* round mem_size up to next power of 2 */
396 mem_size
= lmb_phys_mem_size();
397 rnd_mem_size
= 1UL << __ilog2(mem_size
);
398 if (rnd_mem_size
< mem_size
)
402 pteg_count
= max(rnd_mem_size
>> (12 + 1), 1UL << 11);
404 return pteg_count
<< 7;
407 #ifdef CONFIG_MEMORY_HOTPLUG
408 void create_section_mapping(unsigned long start
, unsigned long end
)
410 BUG_ON(htab_bolt_mapping(start
, end
, __pa(start
),
411 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_COHERENT
| PP_RWXX
,
414 #endif /* CONFIG_MEMORY_HOTPLUG */
416 void __init
htab_initialize(void)
419 unsigned long pteg_count
;
420 unsigned long mode_rw
;
421 unsigned long base
= 0, size
= 0;
424 extern unsigned long tce_alloc_start
, tce_alloc_end
;
426 DBG(" -> htab_initialize()\n");
428 /* Initialize page sizes */
429 htab_init_page_sizes();
432 * Calculate the required size of the htab. We want the number of
433 * PTEGs to equal one half the number of real pages.
435 htab_size_bytes
= htab_get_table_size();
436 pteg_count
= htab_size_bytes
>> 7;
438 htab_hash_mask
= pteg_count
- 1;
440 if (firmware_has_feature(FW_FEATURE_LPAR
)) {
441 /* Using a hypervisor which owns the htab */
445 /* Find storage for the HPT. Must be contiguous in
446 * the absolute address space.
448 table
= lmb_alloc(htab_size_bytes
, htab_size_bytes
);
450 DBG("Hash table allocated at %lx, size: %lx\n", table
,
453 htab_address
= abs_to_virt(table
);
455 /* htab absolute addr + encoded htabsize */
456 _SDR1
= table
+ __ilog2(pteg_count
) - 11;
458 /* Initialize the HPT with no entries */
459 memset((void *)table
, 0, htab_size_bytes
);
462 mtspr(SPRN_SDR1
, _SDR1
);
465 mode_rw
= _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_COHERENT
| PP_RWXX
;
467 /* On U3 based machines, we need to reserve the DART area and
468 * _NOT_ map it to avoid cache paradoxes as it's remapped non
472 /* create bolted the linear mapping in the hash table */
473 for (i
=0; i
< lmb
.memory
.cnt
; i
++) {
474 base
= (unsigned long)__va(lmb
.memory
.region
[i
].base
);
475 size
= lmb
.memory
.region
[i
].size
;
477 DBG("creating mapping for region: %lx : %lx\n", base
, size
);
479 #ifdef CONFIG_U3_DART
480 /* Do not map the DART space. Fortunately, it will be aligned
481 * in such a way that it will not cross two lmb regions and
482 * will fit within a single 16Mb page.
483 * The DART space is assumed to be a full 16Mb region even if
484 * we only use 2Mb of that space. We will use more of it later
485 * for AGP GART. We have to use a full 16Mb large page.
487 DBG("DART base: %lx\n", dart_tablebase
);
489 if (dart_tablebase
!= 0 && dart_tablebase
>= base
490 && dart_tablebase
< (base
+ size
)) {
491 unsigned long dart_table_end
= dart_tablebase
+ 16 * MB
;
492 if (base
!= dart_tablebase
)
493 BUG_ON(htab_bolt_mapping(base
, dart_tablebase
,
496 if ((base
+ size
) > dart_table_end
)
497 BUG_ON(htab_bolt_mapping(dart_tablebase
+16*MB
,
499 __pa(dart_table_end
),
504 #endif /* CONFIG_U3_DART */
505 BUG_ON(htab_bolt_mapping(base
, base
+ size
, __pa(base
),
506 mode_rw
, mmu_linear_psize
));
510 * If we have a memory_limit and we've allocated TCEs then we need to
511 * explicitly map the TCE area at the top of RAM. We also cope with the
512 * case that the TCEs start below memory_limit.
513 * tce_alloc_start/end are 16MB aligned so the mapping should work
514 * for either 4K or 16MB pages.
516 if (tce_alloc_start
) {
517 tce_alloc_start
= (unsigned long)__va(tce_alloc_start
);
518 tce_alloc_end
= (unsigned long)__va(tce_alloc_end
);
520 if (base
+ size
>= tce_alloc_start
)
521 tce_alloc_start
= base
+ size
+ 1;
523 BUG_ON(htab_bolt_mapping(tce_alloc_start
, tce_alloc_end
,
524 __pa(tce_alloc_start
), mode_rw
,
528 DBG(" <- htab_initialize()\n");
533 void htab_initialize_secondary(void)
535 if (!firmware_has_feature(FW_FEATURE_LPAR
))
536 mtspr(SPRN_SDR1
, _SDR1
);
540 * Called by asm hashtable.S for doing lazy icache flush
542 unsigned int hash_page_do_lazy_icache(unsigned int pp
, pte_t pte
, int trap
)
546 if (!pfn_valid(pte_pfn(pte
)))
549 page
= pte_page(pte
);
552 if (!test_bit(PG_arch_1
, &page
->flags
) && !PageReserved(page
)) {
554 __flush_dcache_icache(page_address(page
));
555 set_bit(PG_arch_1
, &page
->flags
);
564 * 1 - normal page fault
565 * -1 - critical hash insertion error
567 int hash_page(unsigned long ea
, unsigned long access
, unsigned long trap
)
571 struct mm_struct
*mm
;
574 int rc
, user_region
= 0, local
= 0;
577 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
580 if ((ea
& ~REGION_MASK
) >= PGTABLE_RANGE
) {
581 DBG_LOW(" out of pgtable range !\n");
585 /* Get region & vsid */
586 switch (REGION_ID(ea
)) {
591 DBG_LOW(" user region with no mm !\n");
594 vsid
= get_vsid(mm
->context
.id
, ea
);
595 psize
= mm
->context
.user_psize
;
597 case VMALLOC_REGION_ID
:
599 vsid
= get_kernel_vsid(ea
);
600 if (ea
< VMALLOC_END
)
601 psize
= mmu_vmalloc_psize
;
603 psize
= mmu_io_psize
;
607 * Send the problem up to do_page_fault
611 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm
, mm
->pgd
, vsid
);
618 /* Check CPU locality */
619 tmp
= cpumask_of_cpu(smp_processor_id());
620 if (user_region
&& cpus_equal(mm
->cpu_vm_mask
, tmp
))
623 /* Handle hugepage regions */
624 if (unlikely(in_hugepage_area(mm
->context
, ea
))) {
625 DBG_LOW(" -> huge page !\n");
626 return hash_huge_page(mm
, access
, ea
, vsid
, local
, trap
);
629 /* Get PTE and page size from page tables */
630 ptep
= find_linux_pte(pgdir
, ea
);
631 if (ptep
== NULL
|| !pte_present(*ptep
)) {
632 DBG_LOW(" no PTE !\n");
636 #ifndef CONFIG_PPC_64K_PAGES
637 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep
));
639 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep
),
640 pte_val(*(ptep
+ PTRS_PER_PTE
)));
642 /* Pre-check access permissions (will be re-checked atomically
643 * in __hash_page_XX but this pre-check is a fast path
645 if (access
& ~pte_val(*ptep
)) {
646 DBG_LOW(" no access !\n");
650 /* Do actual hashing */
651 #ifndef CONFIG_PPC_64K_PAGES
652 rc
= __hash_page_4K(ea
, access
, vsid
, ptep
, trap
, local
);
654 if (mmu_ci_restrictions
) {
655 /* If this PTE is non-cacheable, switch to 4k */
656 if (psize
== MMU_PAGE_64K
&&
657 (pte_val(*ptep
) & _PAGE_NO_CACHE
)) {
660 mm
->context
.user_psize
= MMU_PAGE_4K
;
661 mm
->context
.sllp
= SLB_VSID_USER
|
662 mmu_psize_defs
[MMU_PAGE_4K
].sllp
;
663 } else if (ea
< VMALLOC_END
) {
665 * some driver did a non-cacheable mapping
666 * in vmalloc space, so switch vmalloc
669 printk(KERN_ALERT
"Reducing vmalloc segment "
670 "to 4kB pages because of "
671 "non-cacheable mapping\n");
672 psize
= mmu_vmalloc_psize
= MMU_PAGE_4K
;
676 if (psize
!= get_paca()->context
.user_psize
) {
677 get_paca()->context
= mm
->context
;
678 slb_flush_and_rebolt();
680 } else if (get_paca()->vmalloc_sllp
!=
681 mmu_psize_defs
[mmu_vmalloc_psize
].sllp
) {
682 get_paca()->vmalloc_sllp
=
683 mmu_psize_defs
[mmu_vmalloc_psize
].sllp
;
684 slb_flush_and_rebolt();
687 if (psize
== MMU_PAGE_64K
)
688 rc
= __hash_page_64K(ea
, access
, vsid
, ptep
, trap
, local
);
690 rc
= __hash_page_4K(ea
, access
, vsid
, ptep
, trap
, local
);
691 #endif /* CONFIG_PPC_64K_PAGES */
693 #ifndef CONFIG_PPC_64K_PAGES
694 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep
));
696 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep
),
697 pte_val(*(ptep
+ PTRS_PER_PTE
)));
699 DBG_LOW(" -> rc=%d\n", rc
);
702 EXPORT_SYMBOL_GPL(hash_page
);
704 void hash_preload(struct mm_struct
*mm
, unsigned long ea
,
705 unsigned long access
, unsigned long trap
)
714 /* We don't want huge pages prefaulted for now
716 if (unlikely(in_hugepage_area(mm
->context
, ea
)))
719 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
720 " trap=%lx\n", mm
, mm
->pgd
, ea
, access
, trap
);
722 /* Get PTE, VSID, access mask */
726 ptep
= find_linux_pte(pgdir
, ea
);
729 vsid
= get_vsid(mm
->context
.id
, ea
);
732 local_irq_save(flags
);
733 mask
= cpumask_of_cpu(smp_processor_id());
734 if (cpus_equal(mm
->cpu_vm_mask
, mask
))
736 #ifndef CONFIG_PPC_64K_PAGES
737 __hash_page_4K(ea
, access
, vsid
, ptep
, trap
, local
);
739 if (mmu_ci_restrictions
) {
740 /* If this PTE is non-cacheable, switch to 4k */
741 if (mm
->context
.user_psize
== MMU_PAGE_64K
&&
742 (pte_val(*ptep
) & _PAGE_NO_CACHE
)) {
743 mm
->context
.user_psize
= MMU_PAGE_4K
;
744 mm
->context
.sllp
= SLB_VSID_USER
|
745 mmu_psize_defs
[MMU_PAGE_4K
].sllp
;
746 get_paca()->context
= mm
->context
;
747 slb_flush_and_rebolt();
750 if (mm
->context
.user_psize
== MMU_PAGE_64K
)
751 __hash_page_64K(ea
, access
, vsid
, ptep
, trap
, local
);
753 __hash_page_4K(ea
, access
, vsid
, ptep
, trap
, local
);
754 #endif /* CONFIG_PPC_64K_PAGES */
755 local_irq_restore(flags
);
758 void flush_hash_page(unsigned long va
, real_pte_t pte
, int psize
, int local
)
760 unsigned long hash
, index
, shift
, hidx
, slot
;
762 DBG_LOW("flush_hash_page(va=%016x)\n", va
);
763 pte_iterate_hashed_subpages(pte
, psize
, va
, index
, shift
) {
764 hash
= hpt_hash(va
, shift
);
765 hidx
= __rpte_to_hidx(pte
, index
);
766 if (hidx
& _PTEIDX_SECONDARY
)
768 slot
= (hash
& htab_hash_mask
) * HPTES_PER_GROUP
;
769 slot
+= hidx
& _PTEIDX_GROUP_IX
;
770 DBG_LOW(" sub %d: hash=%x, hidx=%x\n", index
, slot
, hidx
);
771 ppc_md
.hpte_invalidate(slot
, va
, psize
, local
);
772 } pte_iterate_hashed_end();
775 void flush_hash_range(unsigned long number
, int local
)
777 if (ppc_md
.flush_hash_range
)
778 ppc_md
.flush_hash_range(number
, local
);
781 struct ppc64_tlb_batch
*batch
=
782 &__get_cpu_var(ppc64_tlb_batch
);
784 for (i
= 0; i
< number
; i
++)
785 flush_hash_page(batch
->vaddr
[i
], batch
->pte
[i
],
786 batch
->psize
, local
);
790 static inline void make_bl(unsigned int *insn_addr
, void *func
)
792 unsigned long funcp
= *((unsigned long *)func
);
793 int offset
= funcp
- (unsigned long)insn_addr
;
795 *insn_addr
= (unsigned int)(0x48000001 | (offset
& 0x03fffffc));
796 flush_icache_range((unsigned long)insn_addr
, 4+
797 (unsigned long)insn_addr
);
801 * low_hash_fault is called when we the low level hash code failed
802 * to instert a PTE due to an hypervisor error
804 void low_hash_fault(struct pt_regs
*regs
, unsigned long address
)
806 if (user_mode(regs
)) {
809 info
.si_signo
= SIGBUS
;
811 info
.si_code
= BUS_ADRERR
;
812 info
.si_addr
= (void __user
*)address
;
813 force_sig_info(SIGBUS
, &info
, current
);
816 bad_page_fault(regs
, address
, SIGBUS
);
819 void __init
htab_finish_init(void)
821 extern unsigned int *htab_call_hpte_insert1
;
822 extern unsigned int *htab_call_hpte_insert2
;
823 extern unsigned int *htab_call_hpte_remove
;
824 extern unsigned int *htab_call_hpte_updatepp
;
826 #ifdef CONFIG_PPC_64K_PAGES
827 extern unsigned int *ht64_call_hpte_insert1
;
828 extern unsigned int *ht64_call_hpte_insert2
;
829 extern unsigned int *ht64_call_hpte_remove
;
830 extern unsigned int *ht64_call_hpte_updatepp
;
832 make_bl(ht64_call_hpte_insert1
, ppc_md
.hpte_insert
);
833 make_bl(ht64_call_hpte_insert2
, ppc_md
.hpte_insert
);
834 make_bl(ht64_call_hpte_remove
, ppc_md
.hpte_remove
);
835 make_bl(ht64_call_hpte_updatepp
, ppc_md
.hpte_updatepp
);
836 #endif /* CONFIG_PPC_64K_PAGES */
838 make_bl(htab_call_hpte_insert1
, ppc_md
.hpte_insert
);
839 make_bl(htab_call_hpte_insert2
, ppc_md
.hpte_insert
);
840 make_bl(htab_call_hpte_remove
, ppc_md
.hpte_remove
);
841 make_bl(htab_call_hpte_updatepp
, ppc_md
.hpte_updatepp
);