arch/powerpc/mm/tlb_nohash.c

   1 /*
   2  * This file contains the routines for TLB flushing.
   3  * On machines where the MMU does not use a hash table to store virtual to
   4  * physical translations (ie, SW loaded TLBs or Book3E compilant processors,
   5  * this does -not- include 603 however which shares the implementation with
   6  * hash based processors)
   7  *
   8  *  -- BenH
   9  *
  10  * Copyright 2008,2009 Ben Herrenschmidt <benh@kernel.crashing.org>
  11  *                     IBM Corp.
  12  *
  13  *  Derived from arch/ppc/mm/init.c:
  14  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  15  *
  16  *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
  17  *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
  18  *    Copyright (C) 1996 Paul Mackerras
  19  *
  20  *  Derived from "arch/i386/mm/init.c"
  21  *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
  22  *
  23  *  This program is free software; you can redistribute it and/or
  24  *  modify it under the terms of the GNU General Public License
  25  *  as published by the Free Software Foundation; either version
  26  *  2 of the License, or (at your option) any later version.
  27  *
  28  */
  29
  30 #include <linux/kernel.h>
  31 #include <linux/export.h>
  32 #include <linux/mm.h>
  33 #include <linux/init.h>
  34 #include <linux/highmem.h>
  35 #include <linux/pagemap.h>
  36 #include <linux/preempt.h>
  37 #include <linux/spinlock.h>
  38 #include <linux/memblock.h>
  39 #include <linux/of_fdt.h>
  40 #include <linux/hugetlb.h>
  41
  42 #include <asm/tlbflush.h>
  43 #include <asm/tlb.h>
  44 #include <asm/code-patching.h>
  45 #include <asm/hugetlb.h>
  46 #include <asm/paca.h>
  47
  48 #include "mmu_decl.h"
  49
  50 /*
  51  * This struct lists the sw-supported page sizes.  The hardawre MMU may support
  52  * other sizes not listed here.   The .ind field is only used on MMUs that have
  53  * indirect page table entries.
  54  */
  55 #ifdef CONFIG_PPC_BOOK3E_MMU
  56 #ifdef CONFIG_PPC_FSL_BOOK3E
  57 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
  58         [MMU_PAGE_4K] = {
  59                 .shift  = 12,
  60                 .enc    = BOOK3E_PAGESZ_4K,
  61         },
  62         [MMU_PAGE_2M] = {
  63                 .shift  = 21,
  64                 .enc    = BOOK3E_PAGESZ_2M,
  65         },
  66         [MMU_PAGE_4M] = {
  67                 .shift  = 22,
  68                 .enc    = BOOK3E_PAGESZ_4M,
  69         },
  70         [MMU_PAGE_16M] = {
  71                 .shift  = 24,
  72                 .enc    = BOOK3E_PAGESZ_16M,
  73         },
  74         [MMU_PAGE_64M] = {
  75                 .shift  = 26,
  76                 .enc    = BOOK3E_PAGESZ_64M,
  77         },
  78         [MMU_PAGE_256M] = {
  79                 .shift  = 28,
  80                 .enc    = BOOK3E_PAGESZ_256M,
  81         },
  82         [MMU_PAGE_1G] = {
  83                 .shift  = 30,
  84                 .enc    = BOOK3E_PAGESZ_1GB,
  85         },
  86 };
  87 #else
  88 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
  89         [MMU_PAGE_4K] = {
  90                 .shift  = 12,
  91                 .ind    = 20,
  92                 .enc    = BOOK3E_PAGESZ_4K,
  93         },
  94         [MMU_PAGE_16K] = {
  95                 .shift  = 14,
  96                 .enc    = BOOK3E_PAGESZ_16K,
  97         },
  98         [MMU_PAGE_64K] = {
  99                 .shift  = 16,
 100                 .ind    = 28,
 101                 .enc    = BOOK3E_PAGESZ_64K,
 102         },
 103         [MMU_PAGE_1M] = {
 104                 .shift  = 20,
 105                 .enc    = BOOK3E_PAGESZ_1M,
 106         },
 107         [MMU_PAGE_16M] = {
 108                 .shift  = 24,
 109                 .ind    = 36,
 110                 .enc    = BOOK3E_PAGESZ_16M,
 111         },
 112         [MMU_PAGE_256M] = {
 113                 .shift  = 28,
 114                 .enc    = BOOK3E_PAGESZ_256M,
 115         },
 116         [MMU_PAGE_1G] = {
 117                 .shift  = 30,
 118                 .enc    = BOOK3E_PAGESZ_1GB,
 119         },
 120 };
 121 #endif /* CONFIG_FSL_BOOKE */
 122
 123 static inline int mmu_get_tsize(int psize)
 124 {
 125         return mmu_psize_defs[psize].enc;
 126 }
 127 #else
 128 static inline int mmu_get_tsize(int psize)
 129 {
 130         /* This isn't used on !Book3E for now */
 131         return 0;
 132 }
 133 #endif /* CONFIG_PPC_BOOK3E_MMU */
 134
 135 /* The variables below are currently only used on 64-bit Book3E
 136  * though this will probably be made common with other nohash
 137  * implementations at some point
 138  */
 139 #ifdef CONFIG_PPC64
 140
 141 int mmu_linear_psize;           /* Page size used for the linear mapping */
 142 int mmu_pte_psize;              /* Page size used for PTE pages */
 143 int mmu_vmemmap_psize;          /* Page size used for the virtual mem map */
 144 int book3e_htw_mode;            /* HW tablewalk?  Value is PPC_HTW_* */
 145 unsigned long linear_map_top;   /* Top of linear mapping */
 146
 147
 148 /*
 149  * Number of bytes to add to SPRN_SPRG_TLB_EXFRAME on crit/mcheck/debug
 150  * exceptions.  This is used for bolted and e6500 TLB miss handlers which
 151  * do not modify this SPRG in the TLB miss code; for other TLB miss handlers,
 152  * this is set to zero.
 153  */
 154 int extlb_level_exc;
 155
 156 #endif /* CONFIG_PPC64 */
 157
 158 #ifdef CONFIG_PPC_FSL_BOOK3E
 159 /* next_tlbcam_idx is used to round-robin tlbcam entry assignment */
 160 DEFINE_PER_CPU(int, next_tlbcam_idx);
 161 EXPORT_PER_CPU_SYMBOL(next_tlbcam_idx);
 162 #endif
 163
 164 /*
 165  * Base TLB flushing operations:
 166  *
 167  *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
 168  *  - flush_tlb_page(vma, vmaddr) flushes one page
 169  *  - flush_tlb_range(vma, start, end) flushes a range of pages
 170  *  - flush_tlb_kernel_range(start, end) flushes kernel pages
 171  *
 172  *  - local_* variants of page and mm only apply to the current
 173  *    processor
 174  */
 175
 176 /*
 177  * These are the base non-SMP variants of page and mm flushing
 178  */
 179 void local_flush_tlb_mm(struct mm_struct *mm)
 180 {
 181         unsigned int pid;
 182
 183         preempt_disable();
 184         pid = mm->context.id;
 185         if (pid != MMU_NO_CONTEXT)
 186                 _tlbil_pid(pid);
 187         preempt_enable();
 188 }
 189 EXPORT_SYMBOL(local_flush_tlb_mm);
 190
 191 void __local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
 192                             int tsize, int ind)
 193 {
 194         unsigned int pid;
 195
 196         preempt_disable();
 197         pid = mm ? mm->context.id : 0;
 198         if (pid != MMU_NO_CONTEXT)
 199                 _tlbil_va(vmaddr, pid, tsize, ind);
 200         preempt_enable();
 201 }
 202
 203 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
 204 {
 205         __local_flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
 206                                mmu_get_tsize(mmu_virtual_psize), 0);
 207 }
 208 EXPORT_SYMBOL(local_flush_tlb_page);
 209
 210 /*
 211  * And here are the SMP non-local implementations
 212  */
 213 #ifdef CONFIG_SMP
 214
 215 static DEFINE_RAW_SPINLOCK(tlbivax_lock);
 216
 217 static int mm_is_core_local(struct mm_struct *mm)
 218 {
 219         return cpumask_subset(mm_cpumask(mm),
 220                               topology_thread_cpumask(smp_processor_id()));
 221 }
 222
 223 struct tlb_flush_param {
 224         unsigned long addr;
 225         unsigned int pid;
 226         unsigned int tsize;
 227         unsigned int ind;
 228 };
 229
 230 static void do_flush_tlb_mm_ipi(void *param)
 231 {
 232         struct tlb_flush_param *p = param;
 233
 234         _tlbil_pid(p ? p->pid : 0);
 235 }
 236
 237 static void do_flush_tlb_page_ipi(void *param)
 238 {
 239         struct tlb_flush_param *p = param;
 240
 241         _tlbil_va(p->addr, p->pid, p->tsize, p->ind);
 242 }
 243
 244
 245 /* Note on invalidations and PID:
 246  *
 247  * We snapshot the PID with preempt disabled. At this point, it can still
 248  * change either because:
 249  * - our context is being stolen (PID -> NO_CONTEXT) on another CPU
 250  * - we are invaliating some target that isn't currently running here
 251  *   and is concurrently acquiring a new PID on another CPU
 252  * - some other CPU is re-acquiring a lost PID for this mm
 253  * etc...
 254  *
 255  * However, this shouldn't be a problem as we only guarantee
 256  * invalidation of TLB entries present prior to this call, so we
 257  * don't care about the PID changing, and invalidating a stale PID
 258  * is generally harmless.
 259  */
 260
 261 void flush_tlb_mm(struct mm_struct *mm)
 262 {
 263         unsigned int pid;
 264
 265         preempt_disable();
 266         pid = mm->context.id;
 267         if (unlikely(pid == MMU_NO_CONTEXT))
 268                 goto no_context;
 269         if (!mm_is_core_local(mm)) {
 270                 struct tlb_flush_param p = { .pid = pid };
 271                 /* Ignores smp_processor_id() even if set. */
 272                 smp_call_function_many(mm_cpumask(mm),
 273                                        do_flush_tlb_mm_ipi, &p, 1);
 274         }
 275         _tlbil_pid(pid);
 276  no_context:
 277         preempt_enable();
 278 }
 279 EXPORT_SYMBOL(flush_tlb_mm);
 280
 281 void __flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
 282                       int tsize, int ind)
 283 {
 284         struct cpumask *cpu_mask;
 285         unsigned int pid;
 286
 287         preempt_disable();
 288         pid = mm ? mm->context.id : 0;
 289         if (unlikely(pid == MMU_NO_CONTEXT))
 290                 goto bail;
 291         cpu_mask = mm_cpumask(mm);
 292         if (!mm_is_core_local(mm)) {
 293                 /* If broadcast tlbivax is supported, use it */
 294                 if (mmu_has_feature(MMU_FTR_USE_TLBIVAX_BCAST)) {
 295                         int lock = mmu_has_feature(MMU_FTR_LOCK_BCAST_INVAL);
 296                         if (lock)
 297                                 raw_spin_lock(&tlbivax_lock);
 298                         _tlbivax_bcast(vmaddr, pid, tsize, ind);
 299                         if (lock)
 300                                 raw_spin_unlock(&tlbivax_lock);
 301                         goto bail;
 302                 } else {
 303                         struct tlb_flush_param p = {
 304                                 .pid = pid,
 305                                 .addr = vmaddr,
 306                                 .tsize = tsize,
 307                                 .ind = ind,
 308                         };
 309                         /* Ignores smp_processor_id() even if set in cpu_mask */
 310                         smp_call_function_many(cpu_mask,
 311                                                do_flush_tlb_page_ipi, &p, 1);
 312                 }
 313         }
 314         _tlbil_va(vmaddr, pid, tsize, ind);
 315  bail:
 316         preempt_enable();
 317 }
 318
 319 void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
 320 {
 321 #ifdef CONFIG_HUGETLB_PAGE
 322         if (vma && is_vm_hugetlb_page(vma))
 323                 flush_hugetlb_page(vma, vmaddr);
 324 #endif
 325
 326         __flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
 327                          mmu_get_tsize(mmu_virtual_psize), 0);
 328 }
 329 EXPORT_SYMBOL(flush_tlb_page);
 330
 331 #endif /* CONFIG_SMP */
 332
 333 #ifdef CONFIG_PPC_47x
 334 void __init early_init_mmu_47x(void)
 335 {
 336 #ifdef CONFIG_SMP
 337         unsigned long root = of_get_flat_dt_root();
 338         if (of_get_flat_dt_prop(root, "cooperative-partition", NULL))
 339                 mmu_clear_feature(MMU_FTR_USE_TLBIVAX_BCAST);
 340 #endif /* CONFIG_SMP */
 341 }
 342 #endif /* CONFIG_PPC_47x */
 343
 344 /*
 345  * Flush kernel TLB entries in the given range
 346  */
 347 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
 348 {
 349 #ifdef CONFIG_SMP
 350         preempt_disable();
 351         smp_call_function(do_flush_tlb_mm_ipi, NULL, 1);
 352         _tlbil_pid(0);
 353         preempt_enable();
 354 #else
 355         _tlbil_pid(0);
 356 #endif
 357 }
 358 EXPORT_SYMBOL(flush_tlb_kernel_range);
 359
 360 /*
 361  * Currently, for range flushing, we just do a full mm flush. This should
 362  * be optimized based on a threshold on the size of the range, since
 363  * some implementation can stack multiple tlbivax before a tlbsync but
 364  * for now, we keep it that way
 365  */
 366 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 367                      unsigned long end)
 368
 369 {
 370         flush_tlb_mm(vma->vm_mm);
 371 }
 372 EXPORT_SYMBOL(flush_tlb_range);
 373
 374 void tlb_flush(struct mmu_gather *tlb)
 375 {
 376         flush_tlb_mm(tlb->mm);
 377 }
 378
 379 /*
 380  * Below are functions specific to the 64-bit variant of Book3E though that
 381  * may change in the future
 382  */
 383
 384 #ifdef CONFIG_PPC64
 385
 386 /*
 387  * Handling of virtual linear page tables or indirect TLB entries
 388  * flushing when PTE pages are freed
 389  */
 390 void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address)
 391 {
 392         int tsize = mmu_psize_defs[mmu_pte_psize].enc;
 393
 394         if (book3e_htw_mode != PPC_HTW_NONE) {
 395                 unsigned long start = address & PMD_MASK;
 396                 unsigned long end = address + PMD_SIZE;
 397                 unsigned long size = 1UL << mmu_psize_defs[mmu_pte_psize].shift;
 398
 399                 /* This isn't the most optimal, ideally we would factor out the
 400                  * while preempt & CPU mask mucking around, or even the IPI but
 401                  * it will do for now
 402                  */
 403                 while (start < end) {
 404                         __flush_tlb_page(tlb->mm, start, tsize, 1);
 405                         start += size;
 406                 }
 407         } else {
 408                 unsigned long rmask = 0xf000000000000000ul;
 409                 unsigned long rid = (address & rmask) | 0x1000000000000000ul;
 410                 unsigned long vpte = address & ~rmask;
 411
 412 #ifdef CONFIG_PPC_64K_PAGES
 413                 vpte = (vpte >> (PAGE_SHIFT - 4)) & ~0xfffful;
 414 #else
 415                 vpte = (vpte >> (PAGE_SHIFT - 3)) & ~0xffful;
 416 #endif
 417                 vpte |= rid;
 418                 __flush_tlb_page(tlb->mm, vpte, tsize, 0);
 419         }
 420 }
 421
 422 static void setup_page_sizes(void)
 423 {
 424         unsigned int tlb0cfg;
 425         unsigned int tlb0ps;
 426         unsigned int eptcfg;
 427         int i, psize;
 428
 429 #ifdef CONFIG_PPC_FSL_BOOK3E
 430         unsigned int mmucfg = mfspr(SPRN_MMUCFG);
 431         int fsl_mmu = mmu_has_feature(MMU_FTR_TYPE_FSL_E);
 432
 433         if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
 434                 unsigned int tlb1cfg = mfspr(SPRN_TLB1CFG);
 435                 unsigned int min_pg, max_pg;
 436
 437                 min_pg = (tlb1cfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
 438                 max_pg = (tlb1cfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
 439
 440                 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
 441                         struct mmu_psize_def *def;
 442                         unsigned int shift;
 443
 444                         def = &mmu_psize_defs[psize];
 445                         shift = def->shift;
 446
 447                         if (shift == 0 || shift & 1)
 448                                 continue;
 449
 450                         /* adjust to be in terms of 4^shift Kb */
 451                         shift = (shift - 10) >> 1;
 452
 453                         if ((shift >= min_pg) && (shift <= max_pg))
 454                                 def->flags |= MMU_PAGE_SIZE_DIRECT;
 455                 }
 456
 457                 goto out;
 458         }
 459
 460         if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
 461                 u32 tlb1cfg, tlb1ps;
 462
 463                 tlb0cfg = mfspr(SPRN_TLB0CFG);
 464                 tlb1cfg = mfspr(SPRN_TLB1CFG);
 465                 tlb1ps = mfspr(SPRN_TLB1PS);
 466                 eptcfg = mfspr(SPRN_EPTCFG);
 467
 468                 if ((tlb1cfg & TLBnCFG_IND) && (tlb0cfg & TLBnCFG_PT))
 469                         book3e_htw_mode = PPC_HTW_E6500;
 470
 471                 /*
 472                  * We expect 4K subpage size and unrestricted indirect size.
 473                  * The lack of a restriction on indirect size is a Freescale
 474                  * extension, indicated by PSn = 0 but SPSn != 0.
 475                  */
 476                 if (eptcfg != 2)
 477                         book3e_htw_mode = PPC_HTW_NONE;
 478
 479                 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
 480                         struct mmu_psize_def *def = &mmu_psize_defs[psize];
 481
 482                         if (tlb1ps & (1U << (def->shift - 10))) {
 483                                 def->flags |= MMU_PAGE_SIZE_DIRECT;
 484
 485                                 if (book3e_htw_mode && psize == MMU_PAGE_2M)
 486                                         def->flags |= MMU_PAGE_SIZE_INDIRECT;
 487                         }
 488                 }
 489
 490                 goto out;
 491         }
 492 #endif
 493
 494         tlb0cfg = mfspr(SPRN_TLB0CFG);
 495         tlb0ps = mfspr(SPRN_TLB0PS);
 496         eptcfg = mfspr(SPRN_EPTCFG);
 497
 498         /* Look for supported direct sizes */
 499         for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
 500                 struct mmu_psize_def *def = &mmu_psize_defs[psize];
 501
 502                 if (tlb0ps & (1U << (def->shift - 10)))
 503                         def->flags |= MMU_PAGE_SIZE_DIRECT;
 504         }
 505
 506         /* Indirect page sizes supported ? */
 507         if ((tlb0cfg & TLBnCFG_IND) == 0 ||
 508             (tlb0cfg & TLBnCFG_PT) == 0)
 509                 goto out;
 510
 511         book3e_htw_mode = PPC_HTW_IBM;
 512
 513         /* Now, we only deal with one IND page size for each
 514          * direct size. Hopefully all implementations today are
 515          * unambiguous, but we might want to be careful in the
 516          * future.
 517          */
 518         for (i = 0; i < 3; i++) {
 519                 unsigned int ps, sps;
 520
 521                 sps = eptcfg & 0x1f;
 522                 eptcfg >>= 5;
 523                 ps = eptcfg & 0x1f;
 524                 eptcfg >>= 5;
 525                 if (!ps || !sps)
 526                         continue;
 527                 for (psize = 0; psize < MMU_PAGE_COUNT; psize++) {
 528                         struct mmu_psize_def *def = &mmu_psize_defs[psize];
 529
 530                         if (ps == (def->shift - 10))
 531                                 def->flags |= MMU_PAGE_SIZE_INDIRECT;
 532                         if (sps == (def->shift - 10))
 533                                 def->ind = ps + 10;
 534                 }
 535         }
 536
 537 out:
 538         /* Cleanup array and print summary */
 539         pr_info("MMU: Supported page sizes\n");
 540         for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
 541                 struct mmu_psize_def *def = &mmu_psize_defs[psize];
 542                 const char *__page_type_names[] = {
 543                         "unsupported",
 544                         "direct",
 545                         "indirect",
 546                         "direct & indirect"
 547                 };
 548                 if (def->flags == 0) {
 549                         def->shift = 0;
 550                         continue;
 551                 }
 552                 pr_info("  %8ld KB as %s\n", 1ul << (def->shift - 10),
 553                         __page_type_names[def->flags & 0x3]);
 554         }
 555 }
 556
 557 static void setup_mmu_htw(void)
 558 {
 559         /*
 560          * If we want to use HW tablewalk, enable it by patching the TLB miss
 561          * handlers to branch to the one dedicated to it.
 562          */
 563
 564         switch (book3e_htw_mode) {
 565         case PPC_HTW_IBM:
 566                 patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e);
 567                 patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e);
 568                 break;
 569 #ifdef CONFIG_PPC_FSL_BOOK3E
 570         case PPC_HTW_E6500:
 571                 extlb_level_exc = EX_TLB_SIZE;
 572                 patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e);
 573                 patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e);
 574                 break;
 575 #endif
 576         }
 577         pr_info("MMU: Book3E HW tablewalk %s\n",
 578                 book3e_htw_mode != PPC_HTW_NONE ? "enabled" : "not supported");
 579 }
 580
 581 /*
 582  * Early initialization of the MMU TLB code
 583  */
 584 static void early_init_this_mmu(void)
 585 {
 586         unsigned int mas4;
 587
 588         /* Set MAS4 based on page table setting */
 589
 590         mas4 = 0x4 << MAS4_WIMGED_SHIFT;
 591         switch (book3e_htw_mode) {
 592         case PPC_HTW_E6500:
 593                 mas4 |= MAS4_INDD;
 594                 mas4 |= BOOK3E_PAGESZ_2M << MAS4_TSIZED_SHIFT;
 595                 mas4 |= MAS4_TLBSELD(1);
 596                 mmu_pte_psize = MMU_PAGE_2M;
 597                 break;
 598
 599         case PPC_HTW_IBM:
 600                 mas4 |= MAS4_INDD;
 601 #ifdef CONFIG_PPC_64K_PAGES
 602                 mas4 |= BOOK3E_PAGESZ_256M << MAS4_TSIZED_SHIFT;
 603                 mmu_pte_psize = MMU_PAGE_256M;
 604 #else
 605                 mas4 |= BOOK3E_PAGESZ_1M << MAS4_TSIZED_SHIFT;
 606                 mmu_pte_psize = MMU_PAGE_1M;
 607 #endif
 608                 break;
 609
 610         case PPC_HTW_NONE:
 611 #ifdef CONFIG_PPC_64K_PAGES
 612                 mas4 |= BOOK3E_PAGESZ_64K << MAS4_TSIZED_SHIFT;
 613 #else
 614                 mas4 |= BOOK3E_PAGESZ_4K << MAS4_TSIZED_SHIFT;
 615 #endif
 616                 mmu_pte_psize = mmu_virtual_psize;
 617                 break;
 618         }
 619         mtspr(SPRN_MAS4, mas4);
 620
 621 #ifdef CONFIG_PPC_FSL_BOOK3E
 622         if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
 623                 unsigned int num_cams;
 624
 625                 /* use a quarter of the TLBCAM for bolted linear map */
 626                 num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
 627                 linear_map_top = map_mem_in_cams(linear_map_top, num_cams);
 628         }
 629 #endif
 630
 631         /* A sync won't hurt us after mucking around with
 632          * the MMU configuration
 633          */
 634         mb();
 635 }
 636
 637 static void __init early_init_mmu_global(void)
 638 {
 639         /* XXX This will have to be decided at runtime, but right
 640          * now our boot and TLB miss code hard wires it. Ideally
 641          * we should find out a suitable page size and patch the
 642          * TLB miss code (either that or use the PACA to store
 643          * the value we want)
 644          */
 645         mmu_linear_psize = MMU_PAGE_1G;
 646
 647         /* XXX This should be decided at runtime based on supported
 648          * page sizes in the TLB, but for now let's assume 16M is
 649          * always there and a good fit (which it probably is)
 650          *
 651          * Freescale booke only supports 4K pages in TLB0, so use that.
 652          */
 653         if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
 654                 mmu_vmemmap_psize = MMU_PAGE_4K;
 655         else
 656                 mmu_vmemmap_psize = MMU_PAGE_16M;
 657
 658         /* XXX This code only checks for TLB 0 capabilities and doesn't
 659          *     check what page size combos are supported by the HW. It
 660          *     also doesn't handle the case where a separate array holds
 661          *     the IND entries from the array loaded by the PT.
 662          */
 663         /* Look for supported page sizes */
 664         setup_page_sizes();
 665
 666         /* Look for HW tablewalk support */
 667         setup_mmu_htw();
 668
 669 #ifdef CONFIG_PPC_FSL_BOOK3E
 670         if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
 671                 if (book3e_htw_mode == PPC_HTW_NONE) {
 672                         extlb_level_exc = EX_TLB_SIZE;
 673                         patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
 674                         patch_exception(0x1e0,
 675                                 exc_instruction_tlb_miss_bolted_book3e);
 676                 }
 677         }
 678 #endif
 679
 680         /* Set the global containing the top of the linear mapping
 681          * for use by the TLB miss code
 682          */
 683         linear_map_top = memblock_end_of_DRAM();
 684 }
 685
 686 static void __init early_mmu_set_memory_limit(void)
 687 {
 688 #ifdef CONFIG_PPC_FSL_BOOK3E
 689         if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
 690                 /*
 691                  * Limit memory so we dont have linear faults.
 692                  * Unlike memblock_set_current_limit, which limits
 693                  * memory available during early boot, this permanently
 694                  * reduces the memory available to Linux.  We need to
 695                  * do this because highmem is not supported on 64-bit.
 696                  */
 697                 memblock_enforce_memory_limit(linear_map_top);
 698         }
 699 #endif
 700
 701         memblock_set_current_limit(linear_map_top);
 702 }
 703
 704 /* boot cpu only */
 705 void __init early_init_mmu(void)
 706 {
 707         early_init_mmu_global();
 708         early_init_this_mmu();
 709         early_mmu_set_memory_limit();
 710 }
 711
 712 void early_init_mmu_secondary(void)
 713 {
 714         early_init_this_mmu();
 715 }
 716
 717 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
 718                                 phys_addr_t first_memblock_size)
 719 {
 720         /* On non-FSL Embedded 64-bit, we adjust the RMA size to match
 721          * the bolted TLB entry. We know for now that only 1G
 722          * entries are supported though that may eventually
 723          * change.
 724          *
 725          * on FSL Embedded 64-bit, we adjust the RMA size to match the
 726          * first bolted TLB entry size.  We still limit max to 1G even if
 727          * the TLB could cover more.  This is due to what the early init
 728          * code is setup to do.
 729          *
 730          * We crop it to the size of the first MEMBLOCK to
 731          * avoid going over total available memory just in case...
 732          */
 733 #ifdef CONFIG_PPC_FSL_BOOK3E
 734         if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
 735                 unsigned long linear_sz;
 736                 linear_sz = calc_cam_sz(first_memblock_size, PAGE_OFFSET,
 737                                         first_memblock_base);
 738                 ppc64_rma_size = min_t(u64, linear_sz, 0x40000000);
 739         } else
 740 #endif
 741                 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
 742
 743         /* Finally limit subsequent allocations */
 744         memblock_set_current_limit(first_memblock_base + ppc64_rma_size);
 745 }
 746 #else /* ! CONFIG_PPC64 */
 747 void __init early_init_mmu(void)
 748 {
 749 #ifdef CONFIG_PPC_47x
 750         early_init_mmu_47x();
 751 #endif
 752 }
 753 #endif /* CONFIG_PPC64 */