2 * Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights reserved.
4 * Author: John Rigby <jrigby@freescale.com>
9 * This is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/kernel.h>
17 #include <linux/irq.h>
18 #include <linux/of_platform.h>
19 #include <linux/fsl-diu-fb.h>
20 #include <linux/bootmem.h>
21 #include <sysdev/fsl_soc.h>
23 #include <asm/cacheflush.h>
24 #include <asm/machdep.h>
28 #include <asm/mpc5121.h>
29 #include <asm/mpc52xx_psc.h>
33 static struct mpc512x_reset_module __iomem
*reset_module_base
;
35 static void __init
mpc512x_restart_init(void)
37 struct device_node
*np
;
38 const char *reset_compat
;
40 reset_compat
= mpc512x_select_reset_compat();
41 np
= of_find_compatible_node(NULL
, NULL
, reset_compat
);
45 reset_module_base
= of_iomap(np
, 0);
49 void mpc512x_restart(char *cmd
)
51 if (reset_module_base
) {
52 /* Enable software reset "RSTE" */
53 out_be32(&reset_module_base
->rpr
, 0x52535445);
54 /* Set software hard reset */
55 out_be32(&reset_module_base
->rcr
, 0x2);
57 pr_err("Restart module not mapped.\n");
63 struct fsl_diu_shared_fb
{
64 u8 gamma
[0x300]; /* 32-bit aligned! */
65 struct diu_ad ad0
; /* 32-bit aligned! */
71 #define DIU_DIV_MASK 0x000000ff
72 static void mpc512x_set_pixel_clock(unsigned int pixclock
)
74 unsigned long bestval
, bestfreq
, speed
, busfreq
;
75 unsigned long minpixclock
, maxpixclock
, pixval
;
76 struct mpc512x_ccm __iomem
*ccm
;
77 struct device_node
*np
;
82 np
= of_find_compatible_node(NULL
, NULL
, "fsl,mpc5121-clock");
84 pr_err("Can't find clock control module.\n");
88 ccm
= of_iomap(np
, 0);
91 pr_err("Can't map clock control module reg.\n");
95 np
= of_find_node_by_type(NULL
, "cpu");
97 const unsigned int *prop
=
98 of_get_property(np
, "bus-frequency", NULL
);
104 pr_err("Can't get bus-frequency property\n");
108 pr_err("Can't find 'cpu' node.\n");
112 /* Pixel Clock configuration */
113 pr_debug("DIU: Bus Frequency = %lu\n", busfreq
);
114 speed
= busfreq
* 4; /* DIU_DIV ratio is 4 * CSB_CLK / DIU_CLK */
116 /* Calculate the pixel clock with the smallest error */
117 /* calculate the following in steps to avoid overflow */
118 pr_debug("DIU pixclock in ps - %d\n", pixclock
);
119 temp
= (1000000000 / pixclock
) * 1000;
121 pr_debug("DIU pixclock freq - %u\n", pixclock
);
123 temp
= temp
/ 20; /* pixclock * 0.05 */
124 pr_debug("deviation = %d\n", temp
);
125 minpixclock
= pixclock
- temp
;
126 maxpixclock
= pixclock
+ temp
;
127 pr_debug("DIU minpixclock - %lu\n", minpixclock
);
128 pr_debug("DIU maxpixclock - %lu\n", maxpixclock
);
129 pixval
= speed
/pixclock
;
130 pr_debug("DIU pixval = %lu\n", pixval
);
134 pr_debug("DIU bestval = %lu\n", bestval
);
137 for (i
= -1; i
<= 1; i
++) {
138 temp
= speed
/ (pixval
+i
);
139 pr_debug("DIU test pixval i=%d, pixval=%lu, temp freq. = %u\n",
141 if ((temp
< minpixclock
) || (temp
> maxpixclock
))
142 pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
143 minpixclock
, maxpixclock
);
144 else if (abs(temp
- pixclock
) < err
) {
145 pr_debug("Entered the else if block %d\n", i
);
146 err
= abs(temp
- pixclock
);
147 bestval
= pixval
+ i
;
152 pr_debug("DIU chose = %lx\n", bestval
);
153 pr_debug("DIU error = %ld\n NomPixClk ", err
);
154 pr_debug("DIU: Best Freq = %lx\n", bestfreq
);
155 /* Modify DIU_DIV in CCM SCFR1 */
156 temp
= in_be32(&ccm
->scfr1
);
157 pr_debug("DIU: Current value of SCFR1: 0x%08x\n", temp
);
158 temp
&= ~DIU_DIV_MASK
;
159 temp
|= (bestval
& DIU_DIV_MASK
);
160 out_be32(&ccm
->scfr1
, temp
);
161 pr_debug("DIU: Modified value of SCFR1: 0x%08x\n", temp
);
165 static enum fsl_diu_monitor_port
166 mpc512x_valid_monitor_port(enum fsl_diu_monitor_port port
)
168 return FSL_DIU_PORT_DVI
;
171 static struct fsl_diu_shared_fb
__attribute__ ((__aligned__(8))) diu_shared_fb
;
173 static inline void mpc512x_free_bootmem(struct page
*page
)
175 BUG_ON(PageTail(page
));
176 BUG_ON(atomic_read(&page
->_count
) > 1);
177 free_reserved_page(page
);
180 static void mpc512x_release_bootmem(void)
182 unsigned long addr
= diu_shared_fb
.fb_phys
& PAGE_MASK
;
183 unsigned long size
= diu_shared_fb
.fb_len
;
184 unsigned long start
, end
;
186 if (diu_shared_fb
.in_use
) {
187 start
= PFN_UP(addr
);
188 end
= PFN_DOWN(addr
+ size
);
190 for (; start
< end
; start
++)
191 mpc512x_free_bootmem(pfn_to_page(start
));
193 diu_shared_fb
.in_use
= false;
195 diu_ops
.release_bootmem
= NULL
;
199 * Check if DIU was pre-initialized. If so, perform steps
200 * needed to continue displaying through the whole boot process.
201 * Move area descriptor and gamma table elsewhere, they are
202 * destroyed by bootmem allocator otherwise. The frame buffer
203 * address range will be reserved in setup_arch() after bootmem
206 static void __init
mpc512x_init_diu(void)
208 struct device_node
*np
;
209 struct diu __iomem
*diu_reg
;
212 unsigned long mode
, pix_fmt
, res
, bpp
;
215 np
= of_find_compatible_node(NULL
, NULL
, "fsl,mpc5121-diu");
217 pr_err("No DIU node\n");
221 diu_reg
= of_iomap(np
, 0);
224 pr_err("Can't map DIU\n");
228 mode
= in_be32(&diu_reg
->diu_mode
);
229 if (mode
== MFB_MODE0
) {
230 pr_info("%s: DIU OFF\n", __func__
);
234 desc
= in_be32(&diu_reg
->desc
[0]);
235 vaddr
= ioremap(desc
, sizeof(struct diu_ad
));
237 pr_err("Can't map DIU area desc.\n");
240 memcpy(&diu_shared_fb
.ad0
, vaddr
, sizeof(struct diu_ad
));
241 /* flush fb area descriptor */
242 dst
= (unsigned long)&diu_shared_fb
.ad0
;
243 flush_dcache_range(dst
, dst
+ sizeof(struct diu_ad
) - 1);
245 res
= in_be32(&diu_reg
->disp_size
);
246 pix_fmt
= in_le32(vaddr
);
247 bpp
= ((pix_fmt
>> 16) & 0x3) + 1;
248 diu_shared_fb
.fb_phys
= in_le32(vaddr
+ 4);
249 diu_shared_fb
.fb_len
= ((res
& 0xfff0000) >> 16) * (res
& 0xfff) * bpp
;
250 diu_shared_fb
.in_use
= true;
253 desc
= in_be32(&diu_reg
->gamma
);
254 vaddr
= ioremap(desc
, sizeof(diu_shared_fb
.gamma
));
256 pr_err("Can't map DIU area desc.\n");
257 diu_shared_fb
.in_use
= false;
260 memcpy(&diu_shared_fb
.gamma
, vaddr
, sizeof(diu_shared_fb
.gamma
));
261 /* flush gamma table */
262 dst
= (unsigned long)&diu_shared_fb
.gamma
;
263 flush_dcache_range(dst
, dst
+ sizeof(diu_shared_fb
.gamma
) - 1);
266 out_be32(&diu_reg
->gamma
, virt_to_phys(&diu_shared_fb
.gamma
));
267 out_be32(&diu_reg
->desc
[1], 0);
268 out_be32(&diu_reg
->desc
[2], 0);
269 out_be32(&diu_reg
->desc
[0], virt_to_phys(&diu_shared_fb
.ad0
));
275 static void __init
mpc512x_setup_diu(void)
280 * We do not allocate and configure new area for bitmap buffer
281 * because it would requere copying bitmap data (splash image)
282 * and so negatively affect boot time. Instead we reserve the
283 * already configured frame buffer area so that it won't be
284 * destroyed. The starting address of the area to reserve and
285 * also it's length is passed to reserve_bootmem(). It will be
286 * freed later on first open of fbdev, when splash image is not
289 if (diu_shared_fb
.in_use
) {
290 ret
= reserve_bootmem(diu_shared_fb
.fb_phys
,
291 diu_shared_fb
.fb_len
,
294 pr_err("%s: reserve bootmem failed\n", __func__
);
295 diu_shared_fb
.in_use
= false;
299 diu_ops
.set_pixel_clock
= mpc512x_set_pixel_clock
;
300 diu_ops
.valid_monitor_port
= mpc512x_valid_monitor_port
;
301 diu_ops
.release_bootmem
= mpc512x_release_bootmem
;
304 void __init
mpc512x_init_IRQ(void)
306 struct device_node
*np
;
308 np
= of_find_compatible_node(NULL
, NULL
, "fsl,mpc5121-ipic");
316 * Initialize the default interrupt mapping priorities,
317 * in case the boot rom changed something on us.
319 ipic_set_default_priority();
323 * Nodes to do bus probe on, soc and localbus
325 static struct of_device_id __initdata of_bus_ids
[] = {
326 { .compatible
= "fsl,mpc5121-immr", },
327 { .compatible
= "fsl,mpc5121-localbus", },
328 { .compatible
= "fsl,mpc5121-mbx", },
329 { .compatible
= "fsl,mpc5121-nfc", },
330 { .compatible
= "fsl,mpc5121-sram", },
331 { .compatible
= "fsl,mpc5121-pci", },
332 { .compatible
= "gpio-leds", },
336 static void __init
mpc512x_declare_of_platform_devices(void)
338 if (of_platform_bus_probe(NULL
, of_bus_ids
, NULL
))
339 printk(KERN_ERR __FILE__
": "
340 "Error while probing of_platform bus\n");
343 #define DEFAULT_FIFO_SIZE 16
345 const char *mpc512x_select_psc_compat(void)
347 if (of_machine_is_compatible("fsl,mpc5121"))
348 return "fsl,mpc5121-psc";
350 if (of_machine_is_compatible("fsl,mpc5125"))
351 return "fsl,mpc5125-psc";
356 const char *mpc512x_select_reset_compat(void)
358 if (of_machine_is_compatible("fsl,mpc5121"))
359 return "fsl,mpc5121-reset";
361 if (of_machine_is_compatible("fsl,mpc5125"))
362 return "fsl,mpc5125-reset";
367 static unsigned int __init
get_fifo_size(struct device_node
*np
,
370 const unsigned int *fp
;
372 fp
= of_get_property(np
, prop_name
, NULL
);
376 pr_warning("no %s property in %s node, defaulting to %d\n",
377 prop_name
, np
->full_name
, DEFAULT_FIFO_SIZE
);
379 return DEFAULT_FIFO_SIZE
;
382 #define FIFOC(_base) ((struct mpc512x_psc_fifo __iomem *) \
383 ((u32)(_base) + sizeof(struct mpc52xx_psc)))
385 /* Init PSC FIFO space for TX and RX slices */
386 static void __init
mpc512x_psc_fifo_init(void)
388 struct device_node
*np
;
390 unsigned int tx_fifo_size
;
391 unsigned int rx_fifo_size
;
392 const char *psc_compat
;
393 int fifobase
= 0; /* current fifo address in 32 bit words */
395 psc_compat
= mpc512x_select_psc_compat();
397 pr_err("%s: no compatible devices found\n", __func__
);
401 for_each_compatible_node(np
, NULL
, psc_compat
) {
402 tx_fifo_size
= get_fifo_size(np
, "fsl,tx-fifo-size");
403 rx_fifo_size
= get_fifo_size(np
, "fsl,rx-fifo-size");
405 /* size in register is in 4 byte units */
413 psc
= of_iomap(np
, 0);
415 pr_err("%s: Can't map %s device\n",
416 __func__
, np
->full_name
);
420 /* FIFO space is 4KiB, check if requested size is available */
421 if ((fifobase
+ tx_fifo_size
+ rx_fifo_size
) > 0x1000) {
422 pr_err("%s: no fifo space available for %s\n",
423 __func__
, np
->full_name
);
426 * chances are that another device requests less
427 * fifo space, so we continue.
432 /* set tx and rx fifo size registers */
433 out_be32(&FIFOC(psc
)->txsz
, (fifobase
<< 16) | tx_fifo_size
);
434 fifobase
+= tx_fifo_size
;
435 out_be32(&FIFOC(psc
)->rxsz
, (fifobase
<< 16) | rx_fifo_size
);
436 fifobase
+= rx_fifo_size
;
438 /* reset and enable the slices */
439 out_be32(&FIFOC(psc
)->txcmd
, 0x80);
440 out_be32(&FIFOC(psc
)->txcmd
, 0x01);
441 out_be32(&FIFOC(psc
)->rxcmd
, 0x80);
442 out_be32(&FIFOC(psc
)->rxcmd
, 0x01);
448 void __init
mpc512x_init_early(void)
450 mpc512x_restart_init();
451 if (IS_ENABLED(CONFIG_FB_FSL_DIU
))
455 void __init
mpc512x_init(void)
458 mpc512x_declare_of_platform_devices();
459 mpc512x_psc_fifo_init();
462 void __init
mpc512x_setup_arch(void)
464 if (IS_ENABLED(CONFIG_FB_FSL_DIU
))
469 * mpc512x_cs_config - Setup chip select configuration
470 * @cs: chip select number
471 * @val: chip select configuration value
473 * Perform chip select configuration for devices on LocalPlus Bus.
474 * Intended to dynamically reconfigure the chip select parameters
475 * for configurable devices on the bus.
477 int mpc512x_cs_config(unsigned int cs
, u32 val
)
479 static struct mpc512x_lpc __iomem
*lpc
;
480 struct device_node
*np
;
486 np
= of_find_compatible_node(NULL
, NULL
, "fsl,mpc5121-lpc");
487 lpc
= of_iomap(np
, 0);
493 out_be32(&lpc
->cs_cfg
[cs
], val
);
496 EXPORT_SYMBOL(mpc512x_cs_config
);