arch/powerpc/platforms/8xx/mpc885ads_setup.c

   1 /*arch/powerpc/platforms/8xx/mpc885ads_setup.c
   2  *
   3  * Platform setup for the Freescale mpc885ads board
   4  *
   5  * Vitaly Bordug <vbordug@ru.mvista.com>
   6  *
   7  * Copyright 2005 MontaVista Software Inc.
   8  *
   9  * This file is licensed under the terms of the GNU General Public License
  10  * version 2. This program is licensed "as is" without any warranty of any
  11  * kind, whether express or implied.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16 #include <linux/param.h>
  17 #include <linux/string.h>
  18 #include <linux/ioport.h>
  19 #include <linux/device.h>
  20 #include <linux/delay.h>
  21 #include <linux/root_dev.h>
  22
  23 #include <linux/fs_enet_pd.h>
  24 #include <linux/fs_uart_pd.h>
  25 #include <linux/fsl_devices.h>
  26 #include <linux/mii.h>
  27
  28 #include <asm/delay.h>
  29 #include <asm/io.h>
  30 #include <asm/machdep.h>
  31 #include <asm/page.h>
  32 #include <asm/processor.h>
  33 #include <asm/system.h>
  34 #include <asm/time.h>
  35 #include <asm/mpc8xx.h>
  36 #include <asm/8xx_immap.h>
  37 #include <asm/commproc.h>
  38 #include <asm/fs_pd.h>
  39 #include <asm/prom.h>
  40
  41 extern void cpm_reset(void);
  42 extern void mpc8xx_show_cpuinfo(struct seq_file *);
  43 extern void mpc8xx_restart(char *cmd);
  44 extern void mpc8xx_calibrate_decr(void);
  45 extern int mpc8xx_set_rtc_time(struct rtc_time *tm);
  46 extern void mpc8xx_get_rtc_time(struct rtc_time *tm);
  47 extern void m8xx_pic_init(void);
  48 extern unsigned int mpc8xx_get_irq(void);
  49
  50 static void init_smc1_uart_ioports(struct fs_uart_platform_info *fpi);
  51 static void init_smc2_uart_ioports(struct fs_uart_platform_info *fpi);
  52 static void init_scc3_ioports(struct fs_platform_info *ptr);
  53
  54 #ifdef CONFIG_PCMCIA_M8XX
  55 static void pcmcia_hw_setup(int slot, int enable)
  56 {
  57         unsigned *bcsr_io;
  58
  59         bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
  60         if (enable)
  61                 clrbits32(bcsr_io, BCSR1_PCCEN);
  62         else
  63                 setbits32(bcsr_io, BCSR1_PCCEN);
  64
  65         iounmap(bcsr_io);
  66 }
  67
  68 static int pcmcia_set_voltage(int slot, int vcc, int vpp)
  69 {
  70         u32 reg = 0;
  71         unsigned *bcsr_io;
  72
  73         bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
  74
  75         switch (vcc) {
  76         case 0:
  77                 break;
  78         case 33:
  79                 reg |= BCSR1_PCCVCC0;
  80                 break;
  81         case 50:
  82                 reg |= BCSR1_PCCVCC1;
  83                 break;
  84         default:
  85                 return 1;
  86         }
  87
  88         switch (vpp) {
  89         case 0:
  90                 break;
  91         case 33:
  92         case 50:
  93                 if (vcc == vpp)
  94                         reg |= BCSR1_PCCVPP1;
  95                 else
  96                         return 1;
  97                 break;
  98         case 120:
  99                 if ((vcc == 33) || (vcc == 50))
 100                         reg |= BCSR1_PCCVPP0;
 101                 else
 102                         return 1;
 103         default:
 104                 return 1;
 105         }
 106
 107         /* first, turn off all power */
 108         clrbits32(bcsr_io, 0x00610000);
 109
 110         /* enable new powersettings */
 111         setbits32(bcsr_io, reg);
 112
 113         iounmap(bcsr_io);
 114         return 0;
 115 }
 116 #endif
 117
 118 void __init mpc885ads_board_setup(void)
 119 {
 120         cpm8xx_t *cp;
 121         unsigned int *bcsr_io;
 122         u8 tmpval8;
 123
 124 #ifdef CONFIG_FS_ENET
 125         iop8xx_t *io_port;
 126 #endif
 127
 128         bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
 129         cp = (cpm8xx_t *) immr_map(im_cpm);
 130
 131         if (bcsr_io == NULL) {
 132                 printk(KERN_CRIT "Could not remap BCSR\n");
 133                 return;
 134         }
 135 #ifdef CONFIG_SERIAL_CPM_SMC1
 136         clrbits32(bcsr_io, BCSR1_RS232EN_1);
 137         clrbits32(&cp->cp_simode, 0xe0000000 >> 17);    /* brg1 */
 138         tmpval8 = in_8(&(cp->cp_smc[0].smc_smcm)) | (SMCM_RX | SMCM_TX);
 139         out_8(&(cp->cp_smc[0].smc_smcm), tmpval8);
 140         clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN);     /* brg1 */
 141 #else
 142         setbits32(bcsr_io, BCSR1_RS232EN_1);
 143         out_be16(&cp->cp_smc[0].smc_smcmr, 0);
 144         out_8(&cp->cp_smc[0].smc_smce, 0);
 145 #endif
 146
 147 #ifdef CONFIG_SERIAL_CPM_SMC2
 148         clrbits32(bcsr_io, BCSR1_RS232EN_2);
 149         clrbits32(&cp->cp_simode, 0xe0000000 >> 1);
 150         setbits32(&cp->cp_simode, 0x20000000 >> 1);     /* brg2 */
 151         tmpval8 = in_8(&(cp->cp_smc[1].smc_smcm)) | (SMCM_RX | SMCM_TX);
 152         out_8(&(cp->cp_smc[1].smc_smcm), tmpval8);
 153         clrbits16(&cp->cp_smc[1].smc_smcmr, SMCMR_REN | SMCMR_TEN);
 154
 155         init_smc2_uart_ioports(0);
 156 #else
 157         setbits32(bcsr_io, BCSR1_RS232EN_2);
 158         out_be16(&cp->cp_smc[1].smc_smcmr, 0);
 159         out_8(&cp->cp_smc[1].smc_smce, 0);
 160 #endif
 161         immr_unmap(cp);
 162         iounmap(bcsr_io);
 163
 164 #ifdef CONFIG_FS_ENET
 165         /* use MDC for MII (common) */
 166         io_port = (iop8xx_t *) immr_map(im_ioport);
 167         setbits16(&io_port->iop_pdpar, 0x0080);
 168         clrbits16(&io_port->iop_pddir, 0x0080);
 169
 170         bcsr_io = ioremap(BCSR5, sizeof(unsigned long));
 171         clrbits32(bcsr_io, BCSR5_MII1_EN);
 172         clrbits32(bcsr_io, BCSR5_MII1_RST);
 173 #ifndef CONFIG_FC_ENET_HAS_SCC
 174         clrbits32(bcsr_io, BCSR5_MII2_EN);
 175         clrbits32(bcsr_io, BCSR5_MII2_RST);
 176
 177 #endif
 178         iounmap(bcsr_io);
 179         immr_unmap(io_port);
 180
 181 #endif
 182
 183 #ifdef CONFIG_PCMCIA_M8XX
 184         /*Set up board specific hook-ups */
 185         m8xx_pcmcia_ops.hw_ctrl = pcmcia_hw_setup;
 186         m8xx_pcmcia_ops.voltage_set = pcmcia_set_voltage;
 187 #endif
 188 }
 189
 190 static void init_fec1_ioports(struct fs_platform_info *ptr)
 191 {
 192         cpm8xx_t *cp = (cpm8xx_t *) immr_map(im_cpm);
 193         iop8xx_t *io_port = (iop8xx_t *) immr_map(im_ioport);
 194
 195         /* configure FEC1 pins  */
 196         setbits16(&io_port->iop_papar, 0xf830);
 197         setbits16(&io_port->iop_padir, 0x0830);
 198         clrbits16(&io_port->iop_padir, 0xf000);
 199
 200         setbits32(&cp->cp_pbpar, 0x00001001);
 201         clrbits32(&cp->cp_pbdir, 0x00001001);
 202
 203         setbits16(&io_port->iop_pcpar, 0x000c);
 204         clrbits16(&io_port->iop_pcdir, 0x000c);
 205
 206         setbits32(&cp->cp_pepar, 0x00000003);
 207         setbits32(&cp->cp_pedir, 0x00000003);
 208         clrbits32(&cp->cp_peso, 0x00000003);
 209         clrbits32(&cp->cp_cptr, 0x00000100);
 210
 211         immr_unmap(io_port);
 212         immr_unmap(cp);
 213 }
 214
 215 static void init_fec2_ioports(struct fs_platform_info *ptr)
 216 {
 217         cpm8xx_t *cp = (cpm8xx_t *) immr_map(im_cpm);
 218         iop8xx_t *io_port = (iop8xx_t *) immr_map(im_ioport);
 219
 220         /* configure FEC2 pins */
 221         setbits32(&cp->cp_pepar, 0x0003fffc);
 222         setbits32(&cp->cp_pedir, 0x0003fffc);
 223         clrbits32(&cp->cp_peso, 0x000087fc);
 224         setbits32(&cp->cp_peso, 0x00037800);
 225         clrbits32(&cp->cp_cptr, 0x00000080);
 226
 227         immr_unmap(io_port);
 228         immr_unmap(cp);
 229 }
 230
 231 void init_fec_ioports(struct fs_platform_info *fpi)
 232 {
 233         int fec_no = fs_get_fec_index(fpi->fs_no);
 234
 235         switch (fec_no) {
 236         case 0:
 237                 init_fec1_ioports(fpi);
 238                 break;
 239         case 1:
 240                 init_fec2_ioports(fpi);
 241                 break;
 242         default:
 243                 printk(KERN_ERR "init_fec_ioports: invalid FEC number\n");
 244                 return;
 245         }
 246 }
 247
 248 static void init_scc3_ioports(struct fs_platform_info *fpi)
 249 {
 250         unsigned *bcsr_io;
 251         iop8xx_t *io_port;
 252         cpm8xx_t *cp;
 253
 254         bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE);
 255         io_port = (iop8xx_t *) immr_map(im_ioport);
 256         cp = (cpm8xx_t *) immr_map(im_cpm);
 257
 258         if (bcsr_io == NULL) {
 259                 printk(KERN_CRIT "Could not remap BCSR\n");
 260                 return;
 261         }
 262
 263         /* Enable the PHY.
 264          */
 265         clrbits32(bcsr_io + 4, BCSR4_ETH10_RST);
 266         udelay(1000);
 267         setbits32(bcsr_io + 4, BCSR4_ETH10_RST);
 268         /* Configure port A pins for Txd and Rxd.
 269          */
 270         setbits16(&io_port->iop_papar, PA_ENET_RXD | PA_ENET_TXD);
 271         clrbits16(&io_port->iop_padir, PA_ENET_RXD | PA_ENET_TXD);
 272
 273         /* Configure port C pins to enable CLSN and RENA.
 274          */
 275         clrbits16(&io_port->iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
 276         clrbits16(&io_port->iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
 277         setbits16(&io_port->iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
 278
 279         /* Configure port E for TCLK and RCLK.
 280          */
 281         setbits32(&cp->cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK);
 282         clrbits32(&cp->cp_pepar, PE_ENET_TENA);
 283         clrbits32(&cp->cp_pedir, PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA);
 284         clrbits32(&cp->cp_peso, PE_ENET_TCLK | PE_ENET_RCLK);
 285         setbits32(&cp->cp_peso, PE_ENET_TENA);
 286
 287         /* Configure Serial Interface clock routing.
 288          * First, clear all SCC bits to zero, then set the ones we want.
 289          */
 290         clrbits32(&cp->cp_sicr, SICR_ENET_MASK);
 291         setbits32(&cp->cp_sicr, SICR_ENET_CLKRT);
 292
 293         /* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used.
 294          */
 295         clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN);
 296         /* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode
 297          * by H/W setting after reset. SCC ethernet controller support only half duplex.
 298          * This discrepancy of modes causes a lot of carrier lost errors.
 299          */
 300
 301         /* In the original SCC enet driver the following code is placed at
 302            the end of the initialization */
 303         setbits32(&cp->cp_pepar, PE_ENET_TENA);
 304         clrbits32(&cp->cp_pedir, PE_ENET_TENA);
 305         setbits32(&cp->cp_peso, PE_ENET_TENA);
 306
 307         setbits32(bcsr_io + 4, BCSR1_ETHEN);
 308         iounmap(bcsr_io);
 309         immr_unmap(io_port);
 310         immr_unmap(cp);
 311 }
 312
 313 void init_scc_ioports(struct fs_platform_info *fpi)
 314 {
 315         int scc_no = fs_get_scc_index(fpi->fs_no);
 316
 317         switch (scc_no) {
 318         case 2:
 319                 init_scc3_ioports(fpi);
 320                 break;
 321         default:
 322                 printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
 323                 return;
 324         }
 325 }
 326
 327 static void init_smc1_uart_ioports(struct fs_uart_platform_info *ptr)
 328 {
 329         unsigned *bcsr_io;
 330         cpm8xx_t *cp;
 331
 332         cp = (cpm8xx_t *) immr_map(im_cpm);
 333         setbits32(&cp->cp_pepar, 0x000000c0);
 334         clrbits32(&cp->cp_pedir, 0x000000c0);
 335         clrbits32(&cp->cp_peso, 0x00000040);
 336         setbits32(&cp->cp_peso, 0x00000080);
 337         immr_unmap(cp);
 338
 339         bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
 340
 341         if (bcsr_io == NULL) {
 342                 printk(KERN_CRIT "Could not remap BCSR1\n");
 343                 return;
 344         }
 345         clrbits32(bcsr_io, BCSR1_RS232EN_1);
 346         iounmap(bcsr_io);
 347 }
 348
 349 static void init_smc2_uart_ioports(struct fs_uart_platform_info *fpi)
 350 {
 351         unsigned *bcsr_io;
 352         cpm8xx_t *cp;
 353
 354         cp = (cpm8xx_t *) immr_map(im_cpm);
 355         setbits32(&cp->cp_pepar, 0x00000c00);
 356         clrbits32(&cp->cp_pedir, 0x00000c00);
 357         clrbits32(&cp->cp_peso, 0x00000400);
 358         setbits32(&cp->cp_peso, 0x00000800);
 359         immr_unmap(cp);
 360
 361         bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
 362
 363         if (bcsr_io == NULL) {
 364                 printk(KERN_CRIT "Could not remap BCSR1\n");
 365                 return;
 366         }
 367         clrbits32(bcsr_io, BCSR1_RS232EN_2);
 368         iounmap(bcsr_io);
 369 }
 370
 371 void init_smc_ioports(struct fs_uart_platform_info *data)
 372 {
 373         int smc_no = fs_uart_id_fsid2smc(data->fs_no);
 374
 375         switch (smc_no) {
 376         case 0:
 377                 init_smc1_uart_ioports(data);
 378                 data->brg = data->clk_rx;
 379                 break;
 380         case 1:
 381                 init_smc2_uart_ioports(data);
 382                 data->brg = data->clk_rx;
 383                 break;
 384         default:
 385                 printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
 386                 return;
 387         }
 388 }
 389
 390 int platform_device_skip(const char *model, int id)
 391 {
 392 #ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
 393         const char *dev = "FEC";
 394         int n = 2;
 395 #else
 396         const char *dev = "SCC";
 397         int n = 3;
 398 #endif
 399
 400         if (!strcmp(model, dev) && n == id)
 401                 return 1;
 402
 403         return 0;
 404 }
 405
 406 static void __init mpc885ads_setup_arch(void)
 407 {
 408         cpm_reset();
 409
 410         mpc885ads_board_setup();
 411
 412         ROOT_DEV = Root_NFS;
 413 }
 414
 415 static int __init mpc885ads_probe(void)
 416 {
 417         char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
 418                                           "model", NULL);
 419         if (model == NULL)
 420                 return 0;
 421         if (strcmp(model, "MPC885ADS"))
 422                 return 0;
 423
 424         return 1;
 425 }
 426
 427 define_machine(mpc885_ads)
 428 {
 429         .name            = "MPC885 ADS",
 430         .probe           = mpc885ads_probe,
 431         .setup_arch      = mpc885ads_setup_arch,
 432         .init_IRQ        = m8xx_pic_init,
 433         .show_cpuinfo    = mpc8xx_show_cpuinfo,
 434         .get_irq         = mpc8xx_get_irq,
 435         .restart         = mpc8xx_restart,
 436         .calibrate_decr  = mpc8xx_calibrate_decr,
 437         .set_rtc_time    = mpc8xx_set_rtc_time,
 438         .get_rtc_time    = mpc8xx_get_rtc_time,
 439 };