Merge branch 'master'
[deliverable/linux.git] / arch / powerpc / platforms / cell / interrupt.h
1 #ifndef ASM_CELL_PIC_H
2 #define ASM_CELL_PIC_H
3 #ifdef __KERNEL__
4 /*
5 * Mapping of IIC pending bits into per-node
6 * interrupt numbers.
7 *
8 * IRQ FF CC SS PP FF CC SS PP Description
9 *
10 * 00-3f 80 02 +0 00 - 80 02 +0 3f South Bridge
11 * 00-3f 80 02 +b 00 - 80 02 +b 3f South Bridge
12 * 41-4a 80 00 +1 ** - 80 00 +a ** SPU Class 0
13 * 51-5a 80 01 +1 ** - 80 01 +a ** SPU Class 1
14 * 61-6a 80 02 +1 ** - 80 02 +a ** SPU Class 2
15 * 70-7f C0 ** ** 00 - C0 ** ** 0f IPI
16 *
17 * F flags
18 * C class
19 * S source
20 * P Priority
21 * + node number
22 * * don't care
23 *
24 * A node consists of a Cell Broadband Engine and an optional
25 * south bridge device providing a maximum of 64 IRQs.
26 * The south bridge may be connected to either IOIF0
27 * or IOIF1.
28 * Each SPE is represented as three IRQ lines, one per
29 * interrupt class.
30 * 16 IRQ numbers are reserved for inter processor
31 * interruptions, although these are only used in the
32 * range of the first node.
33 *
34 * This scheme needs 128 IRQ numbers per BIF node ID,
35 * which means that with the total of 512 lines
36 * available, we can have a maximum of four nodes.
37 */
38
39 enum {
40 IIC_IRQ_INVALID = 0xff,
41 IIC_IRQ_MAX = 0x3f,
42 IIC_IRQ_EXT_IOIF0 = 0x20,
43 IIC_IRQ_EXT_IOIF1 = 0x2b,
44 IIC_IRQ_IPI0 = 0x40,
45 IIC_NUM_IPIS = 0x10, /* IRQs reserved for IPI */
46 IIC_SOURCE_COUNT = 0x50,
47 };
48
49 extern void iic_init_IRQ(void);
50 extern void iic_cause_IPI(int cpu, int mesg);
51 extern void iic_request_IPIs(void);
52 extern void iic_setup_cpu(void);
53
54 extern u8 iic_get_target_id(int cpu);
55 extern struct irq_host *iic_get_irq_host(int node);
56
57 extern void spider_init_IRQ(void);
58
59 #endif
60 #endif /* ASM_CELL_PIC_H */
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