2 * Support PCI/PCIe on PowerNV platforms
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/crash_dump.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
22 #include <linux/irq.h>
24 #include <linux/msi.h>
25 #include <linux/memblock.h>
26 #include <linux/iommu.h>
27 #include <linux/rculist.h>
28 #include <linux/sizes.h>
30 #include <asm/sections.h>
33 #include <asm/pci-bridge.h>
34 #include <asm/machdep.h>
35 #include <asm/msi_bitmap.h>
36 #include <asm/ppc-pci.h>
38 #include <asm/iommu.h>
41 #include <asm/debug.h>
42 #include <asm/firmware.h>
43 #include <asm/pnv-pci.h>
44 #include <asm/mmzone.h>
46 #include <misc/cxl-base.h>
51 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */
52 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */
53 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
55 #define POWERNV_IOMMU_DEFAULT_LEVELS 1
56 #define POWERNV_IOMMU_MAX_LEVELS 5
58 static const char * const pnv_phb_names
[] = { "IODA1", "IODA2", "NPU" };
59 static void pnv_pci_ioda2_table_free_pages(struct iommu_table
*tbl
);
61 void pe_level_printk(const struct pnv_ioda_pe
*pe
, const char *level
,
73 if (pe
->flags
& PNV_IODA_PE_DEV
)
74 strlcpy(pfix
, dev_name(&pe
->pdev
->dev
), sizeof(pfix
));
75 else if (pe
->flags
& (PNV_IODA_PE_BUS
| PNV_IODA_PE_BUS_ALL
))
76 sprintf(pfix
, "%04x:%02x ",
77 pci_domain_nr(pe
->pbus
), pe
->pbus
->number
);
79 else if (pe
->flags
& PNV_IODA_PE_VF
)
80 sprintf(pfix
, "%04x:%02x:%2x.%d",
81 pci_domain_nr(pe
->parent_dev
->bus
),
82 (pe
->rid
& 0xff00) >> 8,
83 PCI_SLOT(pe
->rid
), PCI_FUNC(pe
->rid
));
84 #endif /* CONFIG_PCI_IOV*/
86 printk("%spci %s: [PE# %.3d] %pV",
87 level
, pfix
, pe
->pe_number
, &vaf
);
92 static bool pnv_iommu_bypass_disabled __read_mostly
;
94 static int __init
iommu_setup(char *str
)
100 if (!strncmp(str
, "nobypass", 8)) {
101 pnv_iommu_bypass_disabled
= true;
102 pr_info("PowerNV: IOMMU bypass window disabled.\n");
105 str
+= strcspn(str
, ",");
112 early_param("iommu", iommu_setup
);
114 static inline bool pnv_pci_is_m64(struct pnv_phb
*phb
, struct resource
*r
)
117 * WARNING: We cannot rely on the resource flags. The Linux PCI
118 * allocation code sometimes decides to put a 64-bit prefetchable
119 * BAR in the 32-bit window, so we have to compare the addresses.
121 * For simplicity we only test resource start.
123 return (r
->start
>= phb
->ioda
.m64_base
&&
124 r
->start
< (phb
->ioda
.m64_base
+ phb
->ioda
.m64_size
));
127 static struct pnv_ioda_pe
*pnv_ioda_init_pe(struct pnv_phb
*phb
, int pe_no
)
129 phb
->ioda
.pe_array
[pe_no
].phb
= phb
;
130 phb
->ioda
.pe_array
[pe_no
].pe_number
= pe_no
;
132 return &phb
->ioda
.pe_array
[pe_no
];
135 static void pnv_ioda_reserve_pe(struct pnv_phb
*phb
, int pe_no
)
137 if (!(pe_no
>= 0 && pe_no
< phb
->ioda
.total_pe_num
)) {
138 pr_warn("%s: Invalid PE %d on PHB#%x\n",
139 __func__
, pe_no
, phb
->hose
->global_number
);
143 if (test_and_set_bit(pe_no
, phb
->ioda
.pe_alloc
))
144 pr_debug("%s: PE %d was reserved on PHB#%x\n",
145 __func__
, pe_no
, phb
->hose
->global_number
);
147 pnv_ioda_init_pe(phb
, pe_no
);
150 static struct pnv_ioda_pe
*pnv_ioda_alloc_pe(struct pnv_phb
*phb
)
154 for (pe
= phb
->ioda
.total_pe_num
- 1; pe
>= 0; pe
--) {
155 if (!test_and_set_bit(pe
, phb
->ioda
.pe_alloc
))
156 return pnv_ioda_init_pe(phb
, pe
);
162 static void pnv_ioda_free_pe(struct pnv_ioda_pe
*pe
)
164 struct pnv_phb
*phb
= pe
->phb
;
165 unsigned int pe_num
= pe
->pe_number
;
169 memset(pe
, 0, sizeof(struct pnv_ioda_pe
));
170 clear_bit(pe_num
, phb
->ioda
.pe_alloc
);
173 /* The default M64 BAR is shared by all PEs */
174 static int pnv_ioda2_init_m64(struct pnv_phb
*phb
)
180 /* Configure the default M64 BAR */
181 rc
= opal_pci_set_phb_mem_window(phb
->opal_id
,
182 OPAL_M64_WINDOW_TYPE
,
183 phb
->ioda
.m64_bar_idx
,
187 if (rc
!= OPAL_SUCCESS
) {
188 desc
= "configuring";
192 /* Enable the default M64 BAR */
193 rc
= opal_pci_phb_mmio_enable(phb
->opal_id
,
194 OPAL_M64_WINDOW_TYPE
,
195 phb
->ioda
.m64_bar_idx
,
196 OPAL_ENABLE_M64_SPLIT
);
197 if (rc
!= OPAL_SUCCESS
) {
203 * Exclude the segments for reserved and root bus PE, which
204 * are first or last two PEs.
206 r
= &phb
->hose
->mem_resources
[1];
207 if (phb
->ioda
.reserved_pe_idx
== 0)
208 r
->start
+= (2 * phb
->ioda
.m64_segsize
);
209 else if (phb
->ioda
.reserved_pe_idx
== (phb
->ioda
.total_pe_num
- 1))
210 r
->end
-= (2 * phb
->ioda
.m64_segsize
);
212 pr_warn(" Cannot strip M64 segment for reserved PE#%d\n",
213 phb
->ioda
.reserved_pe_idx
);
218 pr_warn(" Failure %lld %s M64 BAR#%d\n",
219 rc
, desc
, phb
->ioda
.m64_bar_idx
);
220 opal_pci_phb_mmio_enable(phb
->opal_id
,
221 OPAL_M64_WINDOW_TYPE
,
222 phb
->ioda
.m64_bar_idx
,
227 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev
*pdev
,
228 unsigned long *pe_bitmap
)
230 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
231 struct pnv_phb
*phb
= hose
->private_data
;
233 resource_size_t base
, sgsz
, start
, end
;
236 base
= phb
->ioda
.m64_base
;
237 sgsz
= phb
->ioda
.m64_segsize
;
238 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
239 r
= &pdev
->resource
[i
];
240 if (!r
->parent
|| !pnv_pci_is_m64(phb
, r
))
243 start
= _ALIGN_DOWN(r
->start
- base
, sgsz
);
244 end
= _ALIGN_UP(r
->end
- base
, sgsz
);
245 for (segno
= start
/ sgsz
; segno
< end
/ sgsz
; segno
++) {
247 set_bit(segno
, pe_bitmap
);
249 pnv_ioda_reserve_pe(phb
, segno
);
254 static int pnv_ioda1_init_m64(struct pnv_phb
*phb
)
260 * There are 16 M64 BARs, each of which has 8 segments. So
261 * there are as many M64 segments as the maximum number of
264 for (index
= 0; index
< PNV_IODA1_M64_NUM
; index
++) {
265 unsigned long base
, segsz
= phb
->ioda
.m64_segsize
;
268 base
= phb
->ioda
.m64_base
+
269 index
* PNV_IODA1_M64_SEGS
* segsz
;
270 rc
= opal_pci_set_phb_mem_window(phb
->opal_id
,
271 OPAL_M64_WINDOW_TYPE
, index
, base
, 0,
272 PNV_IODA1_M64_SEGS
* segsz
);
273 if (rc
!= OPAL_SUCCESS
) {
274 pr_warn(" Error %lld setting M64 PHB#%d-BAR#%d\n",
275 rc
, phb
->hose
->global_number
, index
);
279 rc
= opal_pci_phb_mmio_enable(phb
->opal_id
,
280 OPAL_M64_WINDOW_TYPE
, index
,
281 OPAL_ENABLE_M64_SPLIT
);
282 if (rc
!= OPAL_SUCCESS
) {
283 pr_warn(" Error %lld enabling M64 PHB#%d-BAR#%d\n",
284 rc
, phb
->hose
->global_number
, index
);
290 * Exclude the segments for reserved and root bus PE, which
291 * are first or last two PEs.
293 r
= &phb
->hose
->mem_resources
[1];
294 if (phb
->ioda
.reserved_pe_idx
== 0)
295 r
->start
+= (2 * phb
->ioda
.m64_segsize
);
296 else if (phb
->ioda
.reserved_pe_idx
== (phb
->ioda
.total_pe_num
- 1))
297 r
->end
-= (2 * phb
->ioda
.m64_segsize
);
299 WARN(1, "Wrong reserved PE#%d on PHB#%d\n",
300 phb
->ioda
.reserved_pe_idx
, phb
->hose
->global_number
);
305 for ( ; index
>= 0; index
--)
306 opal_pci_phb_mmio_enable(phb
->opal_id
,
307 OPAL_M64_WINDOW_TYPE
, index
, OPAL_DISABLE_M64
);
312 static void pnv_ioda_reserve_m64_pe(struct pci_bus
*bus
,
313 unsigned long *pe_bitmap
,
316 struct pci_dev
*pdev
;
318 list_for_each_entry(pdev
, &bus
->devices
, bus_list
) {
319 pnv_ioda_reserve_dev_m64_pe(pdev
, pe_bitmap
);
321 if (all
&& pdev
->subordinate
)
322 pnv_ioda_reserve_m64_pe(pdev
->subordinate
,
327 static struct pnv_ioda_pe
*pnv_ioda_pick_m64_pe(struct pci_bus
*bus
, bool all
)
329 struct pci_controller
*hose
= pci_bus_to_host(bus
);
330 struct pnv_phb
*phb
= hose
->private_data
;
331 struct pnv_ioda_pe
*master_pe
, *pe
;
332 unsigned long size
, *pe_alloc
;
335 /* Root bus shouldn't use M64 */
336 if (pci_is_root_bus(bus
))
339 /* Allocate bitmap */
340 size
= _ALIGN_UP(phb
->ioda
.total_pe_num
/ 8, sizeof(unsigned long));
341 pe_alloc
= kzalloc(size
, GFP_KERNEL
);
343 pr_warn("%s: Out of memory !\n",
348 /* Figure out reserved PE numbers by the PE */
349 pnv_ioda_reserve_m64_pe(bus
, pe_alloc
, all
);
352 * the current bus might not own M64 window and that's all
353 * contributed by its child buses. For the case, we needn't
354 * pick M64 dependent PE#.
356 if (bitmap_empty(pe_alloc
, phb
->ioda
.total_pe_num
)) {
362 * Figure out the master PE and put all slave PEs to master
363 * PE's list to form compound PE.
367 while ((i
= find_next_bit(pe_alloc
, phb
->ioda
.total_pe_num
, i
+ 1)) <
368 phb
->ioda
.total_pe_num
) {
369 pe
= &phb
->ioda
.pe_array
[i
];
371 phb
->ioda
.m64_segmap
[pe
->pe_number
] = pe
->pe_number
;
373 pe
->flags
|= PNV_IODA_PE_MASTER
;
374 INIT_LIST_HEAD(&pe
->slaves
);
377 pe
->flags
|= PNV_IODA_PE_SLAVE
;
378 pe
->master
= master_pe
;
379 list_add_tail(&pe
->list
, &master_pe
->slaves
);
383 * P7IOC supports M64DT, which helps mapping M64 segment
384 * to one particular PE#. However, PHB3 has fixed mapping
385 * between M64 segment and PE#. In order to have same logic
386 * for P7IOC and PHB3, we enforce fixed mapping between M64
387 * segment and PE# on P7IOC.
389 if (phb
->type
== PNV_PHB_IODA1
) {
392 rc
= opal_pci_map_pe_mmio_window(phb
->opal_id
,
393 pe
->pe_number
, OPAL_M64_WINDOW_TYPE
,
394 pe
->pe_number
/ PNV_IODA1_M64_SEGS
,
395 pe
->pe_number
% PNV_IODA1_M64_SEGS
);
396 if (rc
!= OPAL_SUCCESS
)
397 pr_warn("%s: Error %lld mapping M64 for PHB#%d-PE#%d\n",
398 __func__
, rc
, phb
->hose
->global_number
,
407 static void __init
pnv_ioda_parse_m64_window(struct pnv_phb
*phb
)
409 struct pci_controller
*hose
= phb
->hose
;
410 struct device_node
*dn
= hose
->dn
;
411 struct resource
*res
;
416 if (phb
->type
!= PNV_PHB_IODA1
&& phb
->type
!= PNV_PHB_IODA2
) {
417 pr_info(" Not support M64 window\n");
421 if (!firmware_has_feature(FW_FEATURE_OPAL
)) {
422 pr_info(" Firmware too old to support M64 window\n");
426 r
= of_get_property(dn
, "ibm,opal-m64-window", NULL
);
428 pr_info(" No <ibm,opal-m64-window> on %s\n",
434 * Find the available M64 BAR range and pickup the last one for
435 * covering the whole 64-bits space. We support only one range.
437 if (of_property_read_u32_array(dn
, "ibm,opal-available-m64-ranges",
439 /* In absence of the property, assume 0..15 */
443 /* We only support 64 bits in our allocator */
444 if (m64_range
[1] > 63) {
445 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
446 __func__
, m64_range
[1], phb
->hose
->global_number
);
449 /* Empty range, no m64 */
450 if (m64_range
[1] <= m64_range
[0]) {
451 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
452 __func__
, phb
->hose
->global_number
);
456 /* Configure M64 informations */
457 res
= &hose
->mem_resources
[1];
458 res
->name
= dn
->full_name
;
459 res
->start
= of_translate_address(dn
, r
+ 2);
460 res
->end
= res
->start
+ of_read_number(r
+ 4, 2) - 1;
461 res
->flags
= (IORESOURCE_MEM
| IORESOURCE_MEM_64
| IORESOURCE_PREFETCH
);
462 pci_addr
= of_read_number(r
, 2);
463 hose
->mem_offset
[1] = res
->start
- pci_addr
;
465 phb
->ioda
.m64_size
= resource_size(res
);
466 phb
->ioda
.m64_segsize
= phb
->ioda
.m64_size
/ phb
->ioda
.total_pe_num
;
467 phb
->ioda
.m64_base
= pci_addr
;
469 /* This lines up nicely with the display from processing OF ranges */
470 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
471 res
->start
, res
->end
, pci_addr
, m64_range
[0],
472 m64_range
[0] + m64_range
[1] - 1);
474 /* Mark all M64 used up by default */
475 phb
->ioda
.m64_bar_alloc
= (unsigned long)-1;
477 /* Use last M64 BAR to cover M64 window */
479 phb
->ioda
.m64_bar_idx
= m64_range
[0] + m64_range
[1];
481 pr_info(" Using M64 #%d as default window\n", phb
->ioda
.m64_bar_idx
);
483 /* Mark remaining ones free */
484 for (i
= m64_range
[0]; i
< m64_range
[1]; i
++)
485 clear_bit(i
, &phb
->ioda
.m64_bar_alloc
);
488 * Setup init functions for M64 based on IODA version, IODA3 uses
491 if (phb
->type
== PNV_PHB_IODA1
)
492 phb
->init_m64
= pnv_ioda1_init_m64
;
494 phb
->init_m64
= pnv_ioda2_init_m64
;
495 phb
->reserve_m64_pe
= pnv_ioda_reserve_m64_pe
;
496 phb
->pick_m64_pe
= pnv_ioda_pick_m64_pe
;
499 static void pnv_ioda_freeze_pe(struct pnv_phb
*phb
, int pe_no
)
501 struct pnv_ioda_pe
*pe
= &phb
->ioda
.pe_array
[pe_no
];
502 struct pnv_ioda_pe
*slave
;
505 /* Fetch master PE */
506 if (pe
->flags
& PNV_IODA_PE_SLAVE
) {
508 if (WARN_ON(!pe
|| !(pe
->flags
& PNV_IODA_PE_MASTER
)))
511 pe_no
= pe
->pe_number
;
514 /* Freeze master PE */
515 rc
= opal_pci_eeh_freeze_set(phb
->opal_id
,
517 OPAL_EEH_ACTION_SET_FREEZE_ALL
);
518 if (rc
!= OPAL_SUCCESS
) {
519 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
520 __func__
, rc
, phb
->hose
->global_number
, pe_no
);
524 /* Freeze slave PEs */
525 if (!(pe
->flags
& PNV_IODA_PE_MASTER
))
528 list_for_each_entry(slave
, &pe
->slaves
, list
) {
529 rc
= opal_pci_eeh_freeze_set(phb
->opal_id
,
531 OPAL_EEH_ACTION_SET_FREEZE_ALL
);
532 if (rc
!= OPAL_SUCCESS
)
533 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
534 __func__
, rc
, phb
->hose
->global_number
,
539 static int pnv_ioda_unfreeze_pe(struct pnv_phb
*phb
, int pe_no
, int opt
)
541 struct pnv_ioda_pe
*pe
, *slave
;
545 pe
= &phb
->ioda
.pe_array
[pe_no
];
546 if (pe
->flags
& PNV_IODA_PE_SLAVE
) {
548 WARN_ON(!pe
|| !(pe
->flags
& PNV_IODA_PE_MASTER
));
549 pe_no
= pe
->pe_number
;
552 /* Clear frozen state for master PE */
553 rc
= opal_pci_eeh_freeze_clear(phb
->opal_id
, pe_no
, opt
);
554 if (rc
!= OPAL_SUCCESS
) {
555 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
556 __func__
, rc
, opt
, phb
->hose
->global_number
, pe_no
);
560 if (!(pe
->flags
& PNV_IODA_PE_MASTER
))
563 /* Clear frozen state for slave PEs */
564 list_for_each_entry(slave
, &pe
->slaves
, list
) {
565 rc
= opal_pci_eeh_freeze_clear(phb
->opal_id
,
568 if (rc
!= OPAL_SUCCESS
) {
569 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
570 __func__
, rc
, opt
, phb
->hose
->global_number
,
579 static int pnv_ioda_get_pe_state(struct pnv_phb
*phb
, int pe_no
)
581 struct pnv_ioda_pe
*slave
, *pe
;
586 /* Sanity check on PE number */
587 if (pe_no
< 0 || pe_no
>= phb
->ioda
.total_pe_num
)
588 return OPAL_EEH_STOPPED_PERM_UNAVAIL
;
591 * Fetch the master PE and the PE instance might be
592 * not initialized yet.
594 pe
= &phb
->ioda
.pe_array
[pe_no
];
595 if (pe
->flags
& PNV_IODA_PE_SLAVE
) {
597 WARN_ON(!pe
|| !(pe
->flags
& PNV_IODA_PE_MASTER
));
598 pe_no
= pe
->pe_number
;
601 /* Check the master PE */
602 rc
= opal_pci_eeh_freeze_status(phb
->opal_id
, pe_no
,
603 &state
, &pcierr
, NULL
);
604 if (rc
!= OPAL_SUCCESS
) {
605 pr_warn("%s: Failure %lld getting "
606 "PHB#%x-PE#%x state\n",
608 phb
->hose
->global_number
, pe_no
);
609 return OPAL_EEH_STOPPED_TEMP_UNAVAIL
;
612 /* Check the slave PE */
613 if (!(pe
->flags
& PNV_IODA_PE_MASTER
))
616 list_for_each_entry(slave
, &pe
->slaves
, list
) {
617 rc
= opal_pci_eeh_freeze_status(phb
->opal_id
,
622 if (rc
!= OPAL_SUCCESS
) {
623 pr_warn("%s: Failure %lld getting "
624 "PHB#%x-PE#%x state\n",
626 phb
->hose
->global_number
, slave
->pe_number
);
627 return OPAL_EEH_STOPPED_TEMP_UNAVAIL
;
631 * Override the result based on the ascending
641 /* Currently those 2 are only used when MSIs are enabled, this will change
642 * but in the meantime, we need to protect them to avoid warnings
644 #ifdef CONFIG_PCI_MSI
645 struct pnv_ioda_pe
*pnv_ioda_get_pe(struct pci_dev
*dev
)
647 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
648 struct pnv_phb
*phb
= hose
->private_data
;
649 struct pci_dn
*pdn
= pci_get_pdn(dev
);
653 if (pdn
->pe_number
== IODA_INVALID_PE
)
655 return &phb
->ioda
.pe_array
[pdn
->pe_number
];
657 #endif /* CONFIG_PCI_MSI */
659 static int pnv_ioda_set_one_peltv(struct pnv_phb
*phb
,
660 struct pnv_ioda_pe
*parent
,
661 struct pnv_ioda_pe
*child
,
664 const char *desc
= is_add
? "adding" : "removing";
665 uint8_t op
= is_add
? OPAL_ADD_PE_TO_DOMAIN
:
666 OPAL_REMOVE_PE_FROM_DOMAIN
;
667 struct pnv_ioda_pe
*slave
;
670 /* Parent PE affects child PE */
671 rc
= opal_pci_set_peltv(phb
->opal_id
, parent
->pe_number
,
672 child
->pe_number
, op
);
673 if (rc
!= OPAL_SUCCESS
) {
674 pe_warn(child
, "OPAL error %ld %s to parent PELTV\n",
679 if (!(child
->flags
& PNV_IODA_PE_MASTER
))
682 /* Compound case: parent PE affects slave PEs */
683 list_for_each_entry(slave
, &child
->slaves
, list
) {
684 rc
= opal_pci_set_peltv(phb
->opal_id
, parent
->pe_number
,
685 slave
->pe_number
, op
);
686 if (rc
!= OPAL_SUCCESS
) {
687 pe_warn(slave
, "OPAL error %ld %s to parent PELTV\n",
696 static int pnv_ioda_set_peltv(struct pnv_phb
*phb
,
697 struct pnv_ioda_pe
*pe
,
700 struct pnv_ioda_pe
*slave
;
701 struct pci_dev
*pdev
= NULL
;
705 * Clear PE frozen state. If it's master PE, we need
706 * clear slave PE frozen state as well.
709 opal_pci_eeh_freeze_clear(phb
->opal_id
, pe
->pe_number
,
710 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL
);
711 if (pe
->flags
& PNV_IODA_PE_MASTER
) {
712 list_for_each_entry(slave
, &pe
->slaves
, list
)
713 opal_pci_eeh_freeze_clear(phb
->opal_id
,
715 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL
);
720 * Associate PE in PELT. We need add the PE into the
721 * corresponding PELT-V as well. Otherwise, the error
722 * originated from the PE might contribute to other
725 ret
= pnv_ioda_set_one_peltv(phb
, pe
, pe
, is_add
);
729 /* For compound PEs, any one affects all of them */
730 if (pe
->flags
& PNV_IODA_PE_MASTER
) {
731 list_for_each_entry(slave
, &pe
->slaves
, list
) {
732 ret
= pnv_ioda_set_one_peltv(phb
, slave
, pe
, is_add
);
738 if (pe
->flags
& (PNV_IODA_PE_BUS_ALL
| PNV_IODA_PE_BUS
))
739 pdev
= pe
->pbus
->self
;
740 else if (pe
->flags
& PNV_IODA_PE_DEV
)
741 pdev
= pe
->pdev
->bus
->self
;
742 #ifdef CONFIG_PCI_IOV
743 else if (pe
->flags
& PNV_IODA_PE_VF
)
744 pdev
= pe
->parent_dev
;
745 #endif /* CONFIG_PCI_IOV */
747 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
748 struct pnv_ioda_pe
*parent
;
750 if (pdn
&& pdn
->pe_number
!= IODA_INVALID_PE
) {
751 parent
= &phb
->ioda
.pe_array
[pdn
->pe_number
];
752 ret
= pnv_ioda_set_one_peltv(phb
, parent
, pe
, is_add
);
757 pdev
= pdev
->bus
->self
;
763 static int pnv_ioda_deconfigure_pe(struct pnv_phb
*phb
, struct pnv_ioda_pe
*pe
)
765 struct pci_dev
*parent
;
766 uint8_t bcomp
, dcomp
, fcomp
;
770 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
774 dcomp
= OPAL_IGNORE_RID_DEVICE_NUMBER
;
775 fcomp
= OPAL_IGNORE_RID_FUNCTION_NUMBER
;
776 parent
= pe
->pbus
->self
;
777 if (pe
->flags
& PNV_IODA_PE_BUS_ALL
)
778 count
= pe
->pbus
->busn_res
.end
- pe
->pbus
->busn_res
.start
+ 1;
783 case 1: bcomp
= OpalPciBusAll
; break;
784 case 2: bcomp
= OpalPciBus7Bits
; break;
785 case 4: bcomp
= OpalPciBus6Bits
; break;
786 case 8: bcomp
= OpalPciBus5Bits
; break;
787 case 16: bcomp
= OpalPciBus4Bits
; break;
788 case 32: bcomp
= OpalPciBus3Bits
; break;
790 dev_err(&pe
->pbus
->dev
, "Number of subordinate buses %d unsupported\n",
792 /* Do an exact match only */
793 bcomp
= OpalPciBusAll
;
795 rid_end
= pe
->rid
+ (count
<< 8);
797 #ifdef CONFIG_PCI_IOV
798 if (pe
->flags
& PNV_IODA_PE_VF
)
799 parent
= pe
->parent_dev
;
802 parent
= pe
->pdev
->bus
->self
;
803 bcomp
= OpalPciBusAll
;
804 dcomp
= OPAL_COMPARE_RID_DEVICE_NUMBER
;
805 fcomp
= OPAL_COMPARE_RID_FUNCTION_NUMBER
;
806 rid_end
= pe
->rid
+ 1;
809 /* Clear the reverse map */
810 for (rid
= pe
->rid
; rid
< rid_end
; rid
++)
811 phb
->ioda
.pe_rmap
[rid
] = IODA_INVALID_PE
;
813 /* Release from all parents PELT-V */
815 struct pci_dn
*pdn
= pci_get_pdn(parent
);
816 if (pdn
&& pdn
->pe_number
!= IODA_INVALID_PE
) {
817 rc
= opal_pci_set_peltv(phb
->opal_id
, pdn
->pe_number
,
818 pe
->pe_number
, OPAL_REMOVE_PE_FROM_DOMAIN
);
819 /* XXX What to do in case of error ? */
821 parent
= parent
->bus
->self
;
824 opal_pci_eeh_freeze_clear(phb
->opal_id
, pe
->pe_number
,
825 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL
);
827 /* Disassociate PE in PELT */
828 rc
= opal_pci_set_peltv(phb
->opal_id
, pe
->pe_number
,
829 pe
->pe_number
, OPAL_REMOVE_PE_FROM_DOMAIN
);
831 pe_warn(pe
, "OPAL error %ld remove self from PELTV\n", rc
);
832 rc
= opal_pci_set_pe(phb
->opal_id
, pe
->pe_number
, pe
->rid
,
833 bcomp
, dcomp
, fcomp
, OPAL_UNMAP_PE
);
835 pe_err(pe
, "OPAL error %ld trying to setup PELT table\n", rc
);
839 #ifdef CONFIG_PCI_IOV
840 pe
->parent_dev
= NULL
;
846 static int pnv_ioda_configure_pe(struct pnv_phb
*phb
, struct pnv_ioda_pe
*pe
)
848 struct pci_dev
*parent
;
849 uint8_t bcomp
, dcomp
, fcomp
;
850 long rc
, rid_end
, rid
;
852 /* Bus validation ? */
856 dcomp
= OPAL_IGNORE_RID_DEVICE_NUMBER
;
857 fcomp
= OPAL_IGNORE_RID_FUNCTION_NUMBER
;
858 parent
= pe
->pbus
->self
;
859 if (pe
->flags
& PNV_IODA_PE_BUS_ALL
)
860 count
= pe
->pbus
->busn_res
.end
- pe
->pbus
->busn_res
.start
+ 1;
865 case 1: bcomp
= OpalPciBusAll
; break;
866 case 2: bcomp
= OpalPciBus7Bits
; break;
867 case 4: bcomp
= OpalPciBus6Bits
; break;
868 case 8: bcomp
= OpalPciBus5Bits
; break;
869 case 16: bcomp
= OpalPciBus4Bits
; break;
870 case 32: bcomp
= OpalPciBus3Bits
; break;
872 dev_err(&pe
->pbus
->dev
, "Number of subordinate buses %d unsupported\n",
874 /* Do an exact match only */
875 bcomp
= OpalPciBusAll
;
877 rid_end
= pe
->rid
+ (count
<< 8);
879 #ifdef CONFIG_PCI_IOV
880 if (pe
->flags
& PNV_IODA_PE_VF
)
881 parent
= pe
->parent_dev
;
883 #endif /* CONFIG_PCI_IOV */
884 parent
= pe
->pdev
->bus
->self
;
885 bcomp
= OpalPciBusAll
;
886 dcomp
= OPAL_COMPARE_RID_DEVICE_NUMBER
;
887 fcomp
= OPAL_COMPARE_RID_FUNCTION_NUMBER
;
888 rid_end
= pe
->rid
+ 1;
892 * Associate PE in PELT. We need add the PE into the
893 * corresponding PELT-V as well. Otherwise, the error
894 * originated from the PE might contribute to other
897 rc
= opal_pci_set_pe(phb
->opal_id
, pe
->pe_number
, pe
->rid
,
898 bcomp
, dcomp
, fcomp
, OPAL_MAP_PE
);
900 pe_err(pe
, "OPAL error %ld trying to setup PELT table\n", rc
);
905 * Configure PELTV. NPUs don't have a PELTV table so skip
906 * configuration on them.
908 if (phb
->type
!= PNV_PHB_NPU
)
909 pnv_ioda_set_peltv(phb
, pe
, true);
911 /* Setup reverse map */
912 for (rid
= pe
->rid
; rid
< rid_end
; rid
++)
913 phb
->ioda
.pe_rmap
[rid
] = pe
->pe_number
;
915 /* Setup one MVTs on IODA1 */
916 if (phb
->type
!= PNV_PHB_IODA1
) {
921 pe
->mve_number
= pe
->pe_number
;
922 rc
= opal_pci_set_mve(phb
->opal_id
, pe
->mve_number
, pe
->pe_number
);
923 if (rc
!= OPAL_SUCCESS
) {
924 pe_err(pe
, "OPAL error %ld setting up MVE %d\n",
928 rc
= opal_pci_set_mve_enable(phb
->opal_id
,
929 pe
->mve_number
, OPAL_ENABLE_MVE
);
931 pe_err(pe
, "OPAL error %ld enabling MVE %d\n",
941 #ifdef CONFIG_PCI_IOV
942 static int pnv_pci_vf_resource_shift(struct pci_dev
*dev
, int offset
)
944 struct pci_dn
*pdn
= pci_get_pdn(dev
);
946 struct resource
*res
, res2
;
947 resource_size_t size
;
954 * "offset" is in VFs. The M64 windows are sized so that when they
955 * are segmented, each segment is the same size as the IOV BAR.
956 * Each segment is in a separate PE, and the high order bits of the
957 * address are the PE number. Therefore, each VF's BAR is in a
958 * separate PE, and changing the IOV BAR start address changes the
959 * range of PEs the VFs are in.
961 num_vfs
= pdn
->num_vfs
;
962 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
963 res
= &dev
->resource
[i
+ PCI_IOV_RESOURCES
];
964 if (!res
->flags
|| !res
->parent
)
968 * The actual IOV BAR range is determined by the start address
969 * and the actual size for num_vfs VFs BAR. This check is to
970 * make sure that after shifting, the range will not overlap
971 * with another device.
973 size
= pci_iov_resource_size(dev
, i
+ PCI_IOV_RESOURCES
);
974 res2
.flags
= res
->flags
;
975 res2
.start
= res
->start
+ (size
* offset
);
976 res2
.end
= res2
.start
+ (size
* num_vfs
) - 1;
978 if (res2
.end
> res
->end
) {
979 dev_err(&dev
->dev
, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
980 i
, &res2
, res
, num_vfs
, offset
);
986 * After doing so, there would be a "hole" in the /proc/iomem when
987 * offset is a positive value. It looks like the device return some
988 * mmio back to the system, which actually no one could use it.
990 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
991 res
= &dev
->resource
[i
+ PCI_IOV_RESOURCES
];
992 if (!res
->flags
|| !res
->parent
)
995 size
= pci_iov_resource_size(dev
, i
+ PCI_IOV_RESOURCES
);
997 res
->start
+= size
* offset
;
999 dev_info(&dev
->dev
, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1000 i
, &res2
, res
, (offset
> 0) ? "En" : "Dis",
1002 pci_update_resource(dev
, i
+ PCI_IOV_RESOURCES
);
1006 #endif /* CONFIG_PCI_IOV */
1008 static struct pnv_ioda_pe
*pnv_ioda_setup_dev_PE(struct pci_dev
*dev
)
1010 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
1011 struct pnv_phb
*phb
= hose
->private_data
;
1012 struct pci_dn
*pdn
= pci_get_pdn(dev
);
1013 struct pnv_ioda_pe
*pe
;
1016 pr_err("%s: Device tree node not associated properly\n",
1020 if (pdn
->pe_number
!= IODA_INVALID_PE
)
1023 pe
= pnv_ioda_alloc_pe(phb
);
1025 pr_warning("%s: Not enough PE# available, disabling device\n",
1030 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
1031 * pointer in the PE data structure, both should be destroyed at the
1032 * same time. However, this needs to be looked at more closely again
1033 * once we actually start removing things (Hotplug, SR-IOV, ...)
1035 * At some point we want to remove the PDN completely anyways
1039 pdn
->pe_number
= pe
->pe_number
;
1040 pe
->flags
= PNV_IODA_PE_DEV
;
1043 pe
->mve_number
= -1;
1044 pe
->rid
= dev
->bus
->number
<< 8 | pdn
->devfn
;
1046 pe_info(pe
, "Associated device to PE\n");
1048 if (pnv_ioda_configure_pe(phb
, pe
)) {
1049 /* XXX What do we do here ? */
1050 pnv_ioda_free_pe(pe
);
1051 pdn
->pe_number
= IODA_INVALID_PE
;
1057 /* Put PE to the list */
1058 list_add_tail(&pe
->list
, &phb
->ioda
.pe_list
);
1063 static void pnv_ioda_setup_same_PE(struct pci_bus
*bus
, struct pnv_ioda_pe
*pe
)
1065 struct pci_dev
*dev
;
1067 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1068 struct pci_dn
*pdn
= pci_get_pdn(dev
);
1071 pr_warn("%s: No device node associated with device !\n",
1077 * In partial hotplug case, the PCI device might be still
1078 * associated with the PE and needn't attach it to the PE
1081 if (pdn
->pe_number
!= IODA_INVALID_PE
)
1086 pdn
->pe_number
= pe
->pe_number
;
1087 if ((pe
->flags
& PNV_IODA_PE_BUS_ALL
) && dev
->subordinate
)
1088 pnv_ioda_setup_same_PE(dev
->subordinate
, pe
);
1093 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1094 * single PCI bus. Another one that contains the primary PCI bus and its
1095 * subordinate PCI devices and buses. The second type of PE is normally
1096 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1098 static struct pnv_ioda_pe
*pnv_ioda_setup_bus_PE(struct pci_bus
*bus
, bool all
)
1100 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1101 struct pnv_phb
*phb
= hose
->private_data
;
1102 struct pnv_ioda_pe
*pe
= NULL
;
1103 unsigned int pe_num
;
1106 * In partial hotplug case, the PE instance might be still alive.
1107 * We should reuse it instead of allocating a new one.
1109 pe_num
= phb
->ioda
.pe_rmap
[bus
->number
<< 8];
1110 if (pe_num
!= IODA_INVALID_PE
) {
1111 pe
= &phb
->ioda
.pe_array
[pe_num
];
1112 pnv_ioda_setup_same_PE(bus
, pe
);
1116 /* PE number for root bus should have been reserved */
1117 if (pci_is_root_bus(bus
) &&
1118 phb
->ioda
.root_pe_idx
!= IODA_INVALID_PE
)
1119 pe
= &phb
->ioda
.pe_array
[phb
->ioda
.root_pe_idx
];
1121 /* Check if PE is determined by M64 */
1122 if (!pe
&& phb
->pick_m64_pe
)
1123 pe
= phb
->pick_m64_pe(bus
, all
);
1125 /* The PE number isn't pinned by M64 */
1127 pe
= pnv_ioda_alloc_pe(phb
);
1130 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1131 __func__
, pci_domain_nr(bus
), bus
->number
);
1135 pe
->flags
|= (all
? PNV_IODA_PE_BUS_ALL
: PNV_IODA_PE_BUS
);
1138 pe
->mve_number
= -1;
1139 pe
->rid
= bus
->busn_res
.start
<< 8;
1142 pe_info(pe
, "Secondary bus %d..%d associated with PE#%d\n",
1143 bus
->busn_res
.start
, bus
->busn_res
.end
, pe
->pe_number
);
1145 pe_info(pe
, "Secondary bus %d associated with PE#%d\n",
1146 bus
->busn_res
.start
, pe
->pe_number
);
1148 if (pnv_ioda_configure_pe(phb
, pe
)) {
1149 /* XXX What do we do here ? */
1150 pnv_ioda_free_pe(pe
);
1155 /* Associate it with all child devices */
1156 pnv_ioda_setup_same_PE(bus
, pe
);
1158 /* Put PE to the list */
1159 list_add_tail(&pe
->list
, &phb
->ioda
.pe_list
);
1164 static struct pnv_ioda_pe
*pnv_ioda_setup_npu_PE(struct pci_dev
*npu_pdev
)
1166 int pe_num
, found_pe
= false, rc
;
1168 struct pnv_ioda_pe
*pe
;
1169 struct pci_dev
*gpu_pdev
;
1170 struct pci_dn
*npu_pdn
;
1171 struct pci_controller
*hose
= pci_bus_to_host(npu_pdev
->bus
);
1172 struct pnv_phb
*phb
= hose
->private_data
;
1175 * Due to a hardware errata PE#0 on the NPU is reserved for
1176 * error handling. This means we only have three PEs remaining
1177 * which need to be assigned to four links, implying some
1178 * links must share PEs.
1180 * To achieve this we assign PEs such that NPUs linking the
1181 * same GPU get assigned the same PE.
1183 gpu_pdev
= pnv_pci_get_gpu_dev(npu_pdev
);
1184 for (pe_num
= 0; pe_num
< phb
->ioda
.total_pe_num
; pe_num
++) {
1185 pe
= &phb
->ioda
.pe_array
[pe_num
];
1189 if (pnv_pci_get_gpu_dev(pe
->pdev
) == gpu_pdev
) {
1191 * This device has the same peer GPU so should
1192 * be assigned the same PE as the existing
1195 dev_info(&npu_pdev
->dev
,
1196 "Associating to existing PE %d\n", pe_num
);
1197 pci_dev_get(npu_pdev
);
1198 npu_pdn
= pci_get_pdn(npu_pdev
);
1199 rid
= npu_pdev
->bus
->number
<< 8 | npu_pdn
->devfn
;
1200 npu_pdn
->pcidev
= npu_pdev
;
1201 npu_pdn
->pe_number
= pe_num
;
1202 phb
->ioda
.pe_rmap
[rid
] = pe
->pe_number
;
1204 /* Map the PE to this link */
1205 rc
= opal_pci_set_pe(phb
->opal_id
, pe_num
, rid
,
1207 OPAL_COMPARE_RID_DEVICE_NUMBER
,
1208 OPAL_COMPARE_RID_FUNCTION_NUMBER
,
1210 WARN_ON(rc
!= OPAL_SUCCESS
);
1218 * Could not find an existing PE so allocate a new
1221 return pnv_ioda_setup_dev_PE(npu_pdev
);
1226 static void pnv_ioda_setup_npu_PEs(struct pci_bus
*bus
)
1228 struct pci_dev
*pdev
;
1230 list_for_each_entry(pdev
, &bus
->devices
, bus_list
)
1231 pnv_ioda_setup_npu_PE(pdev
);
1234 static void pnv_pci_ioda_setup_PEs(void)
1236 struct pci_controller
*hose
, *tmp
;
1237 struct pnv_phb
*phb
;
1239 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
1240 phb
= hose
->private_data
;
1241 if (phb
->type
== PNV_PHB_NPU
) {
1242 /* PE#0 is needed for error reporting */
1243 pnv_ioda_reserve_pe(phb
, 0);
1244 pnv_ioda_setup_npu_PEs(hose
->bus
);
1249 #ifdef CONFIG_PCI_IOV
1250 static int pnv_pci_vf_release_m64(struct pci_dev
*pdev
, u16 num_vfs
)
1252 struct pci_bus
*bus
;
1253 struct pci_controller
*hose
;
1254 struct pnv_phb
*phb
;
1260 hose
= pci_bus_to_host(bus
);
1261 phb
= hose
->private_data
;
1262 pdn
= pci_get_pdn(pdev
);
1264 if (pdn
->m64_single_mode
)
1269 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++)
1270 for (j
= 0; j
< m64_bars
; j
++) {
1271 if (pdn
->m64_map
[j
][i
] == IODA_INVALID_M64
)
1273 opal_pci_phb_mmio_enable(phb
->opal_id
,
1274 OPAL_M64_WINDOW_TYPE
, pdn
->m64_map
[j
][i
], 0);
1275 clear_bit(pdn
->m64_map
[j
][i
], &phb
->ioda
.m64_bar_alloc
);
1276 pdn
->m64_map
[j
][i
] = IODA_INVALID_M64
;
1279 kfree(pdn
->m64_map
);
1283 static int pnv_pci_vf_assign_m64(struct pci_dev
*pdev
, u16 num_vfs
)
1285 struct pci_bus
*bus
;
1286 struct pci_controller
*hose
;
1287 struct pnv_phb
*phb
;
1290 struct resource
*res
;
1294 resource_size_t size
, start
;
1299 hose
= pci_bus_to_host(bus
);
1300 phb
= hose
->private_data
;
1301 pdn
= pci_get_pdn(pdev
);
1302 total_vfs
= pci_sriov_get_totalvfs(pdev
);
1304 if (pdn
->m64_single_mode
)
1309 pdn
->m64_map
= kmalloc(sizeof(*pdn
->m64_map
) * m64_bars
, GFP_KERNEL
);
1312 /* Initialize the m64_map to IODA_INVALID_M64 */
1313 for (i
= 0; i
< m64_bars
; i
++)
1314 for (j
= 0; j
< PCI_SRIOV_NUM_BARS
; j
++)
1315 pdn
->m64_map
[i
][j
] = IODA_INVALID_M64
;
1318 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
1319 res
= &pdev
->resource
[i
+ PCI_IOV_RESOURCES
];
1320 if (!res
->flags
|| !res
->parent
)
1323 for (j
= 0; j
< m64_bars
; j
++) {
1325 win
= find_next_zero_bit(&phb
->ioda
.m64_bar_alloc
,
1326 phb
->ioda
.m64_bar_idx
+ 1, 0);
1328 if (win
>= phb
->ioda
.m64_bar_idx
+ 1)
1330 } while (test_and_set_bit(win
, &phb
->ioda
.m64_bar_alloc
));
1332 pdn
->m64_map
[j
][i
] = win
;
1334 if (pdn
->m64_single_mode
) {
1335 size
= pci_iov_resource_size(pdev
,
1336 PCI_IOV_RESOURCES
+ i
);
1337 start
= res
->start
+ size
* j
;
1339 size
= resource_size(res
);
1343 /* Map the M64 here */
1344 if (pdn
->m64_single_mode
) {
1345 pe_num
= pdn
->pe_num_map
[j
];
1346 rc
= opal_pci_map_pe_mmio_window(phb
->opal_id
,
1347 pe_num
, OPAL_M64_WINDOW_TYPE
,
1348 pdn
->m64_map
[j
][i
], 0);
1351 rc
= opal_pci_set_phb_mem_window(phb
->opal_id
,
1352 OPAL_M64_WINDOW_TYPE
,
1359 if (rc
!= OPAL_SUCCESS
) {
1360 dev_err(&pdev
->dev
, "Failed to map M64 window #%d: %lld\n",
1365 if (pdn
->m64_single_mode
)
1366 rc
= opal_pci_phb_mmio_enable(phb
->opal_id
,
1367 OPAL_M64_WINDOW_TYPE
, pdn
->m64_map
[j
][i
], 2);
1369 rc
= opal_pci_phb_mmio_enable(phb
->opal_id
,
1370 OPAL_M64_WINDOW_TYPE
, pdn
->m64_map
[j
][i
], 1);
1372 if (rc
!= OPAL_SUCCESS
) {
1373 dev_err(&pdev
->dev
, "Failed to enable M64 window #%d: %llx\n",
1382 pnv_pci_vf_release_m64(pdev
, num_vfs
);
1386 static long pnv_pci_ioda2_unset_window(struct iommu_table_group
*table_group
,
1388 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe
*pe
, bool enable
);
1390 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev
*dev
, struct pnv_ioda_pe
*pe
)
1392 struct iommu_table
*tbl
;
1395 tbl
= pe
->table_group
.tables
[0];
1396 rc
= pnv_pci_ioda2_unset_window(&pe
->table_group
, 0);
1398 pe_warn(pe
, "OPAL error %ld release DMA window\n", rc
);
1400 pnv_pci_ioda2_set_bypass(pe
, false);
1401 if (pe
->table_group
.group
) {
1402 iommu_group_put(pe
->table_group
.group
);
1403 BUG_ON(pe
->table_group
.group
);
1405 pnv_pci_ioda2_table_free_pages(tbl
);
1406 iommu_free_table(tbl
, of_node_full_name(dev
->dev
.of_node
));
1409 static void pnv_ioda_release_vf_PE(struct pci_dev
*pdev
)
1411 struct pci_bus
*bus
;
1412 struct pci_controller
*hose
;
1413 struct pnv_phb
*phb
;
1414 struct pnv_ioda_pe
*pe
, *pe_n
;
1418 hose
= pci_bus_to_host(bus
);
1419 phb
= hose
->private_data
;
1420 pdn
= pci_get_pdn(pdev
);
1422 if (!pdev
->is_physfn
)
1425 list_for_each_entry_safe(pe
, pe_n
, &phb
->ioda
.pe_list
, list
) {
1426 if (pe
->parent_dev
!= pdev
)
1429 pnv_pci_ioda2_release_dma_pe(pdev
, pe
);
1431 /* Remove from list */
1432 mutex_lock(&phb
->ioda
.pe_list_mutex
);
1433 list_del(&pe
->list
);
1434 mutex_unlock(&phb
->ioda
.pe_list_mutex
);
1436 pnv_ioda_deconfigure_pe(phb
, pe
);
1438 pnv_ioda_free_pe(pe
);
1442 void pnv_pci_sriov_disable(struct pci_dev
*pdev
)
1444 struct pci_bus
*bus
;
1445 struct pci_controller
*hose
;
1446 struct pnv_phb
*phb
;
1447 struct pnv_ioda_pe
*pe
;
1449 struct pci_sriov
*iov
;
1453 hose
= pci_bus_to_host(bus
);
1454 phb
= hose
->private_data
;
1455 pdn
= pci_get_pdn(pdev
);
1457 num_vfs
= pdn
->num_vfs
;
1459 /* Release VF PEs */
1460 pnv_ioda_release_vf_PE(pdev
);
1462 if (phb
->type
== PNV_PHB_IODA2
) {
1463 if (!pdn
->m64_single_mode
)
1464 pnv_pci_vf_resource_shift(pdev
, -*pdn
->pe_num_map
);
1466 /* Release M64 windows */
1467 pnv_pci_vf_release_m64(pdev
, num_vfs
);
1469 /* Release PE numbers */
1470 if (pdn
->m64_single_mode
) {
1471 for (i
= 0; i
< num_vfs
; i
++) {
1472 if (pdn
->pe_num_map
[i
] == IODA_INVALID_PE
)
1475 pe
= &phb
->ioda
.pe_array
[pdn
->pe_num_map
[i
]];
1476 pnv_ioda_free_pe(pe
);
1479 bitmap_clear(phb
->ioda
.pe_alloc
, *pdn
->pe_num_map
, num_vfs
);
1480 /* Releasing pe_num_map */
1481 kfree(pdn
->pe_num_map
);
1485 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb
*phb
,
1486 struct pnv_ioda_pe
*pe
);
1487 static void pnv_ioda_setup_vf_PE(struct pci_dev
*pdev
, u16 num_vfs
)
1489 struct pci_bus
*bus
;
1490 struct pci_controller
*hose
;
1491 struct pnv_phb
*phb
;
1492 struct pnv_ioda_pe
*pe
;
1498 hose
= pci_bus_to_host(bus
);
1499 phb
= hose
->private_data
;
1500 pdn
= pci_get_pdn(pdev
);
1502 if (!pdev
->is_physfn
)
1505 /* Reserve PE for each VF */
1506 for (vf_index
= 0; vf_index
< num_vfs
; vf_index
++) {
1507 if (pdn
->m64_single_mode
)
1508 pe_num
= pdn
->pe_num_map
[vf_index
];
1510 pe_num
= *pdn
->pe_num_map
+ vf_index
;
1512 pe
= &phb
->ioda
.pe_array
[pe_num
];
1513 pe
->pe_number
= pe_num
;
1515 pe
->flags
= PNV_IODA_PE_VF
;
1517 pe
->parent_dev
= pdev
;
1518 pe
->mve_number
= -1;
1519 pe
->rid
= (pci_iov_virtfn_bus(pdev
, vf_index
) << 8) |
1520 pci_iov_virtfn_devfn(pdev
, vf_index
);
1522 pe_info(pe
, "VF %04d:%02d:%02d.%d associated with PE#%d\n",
1523 hose
->global_number
, pdev
->bus
->number
,
1524 PCI_SLOT(pci_iov_virtfn_devfn(pdev
, vf_index
)),
1525 PCI_FUNC(pci_iov_virtfn_devfn(pdev
, vf_index
)), pe_num
);
1527 if (pnv_ioda_configure_pe(phb
, pe
)) {
1528 /* XXX What do we do here ? */
1529 pnv_ioda_free_pe(pe
);
1534 /* Put PE to the list */
1535 mutex_lock(&phb
->ioda
.pe_list_mutex
);
1536 list_add_tail(&pe
->list
, &phb
->ioda
.pe_list
);
1537 mutex_unlock(&phb
->ioda
.pe_list_mutex
);
1539 pnv_pci_ioda2_setup_dma_pe(phb
, pe
);
1543 int pnv_pci_sriov_enable(struct pci_dev
*pdev
, u16 num_vfs
)
1545 struct pci_bus
*bus
;
1546 struct pci_controller
*hose
;
1547 struct pnv_phb
*phb
;
1548 struct pnv_ioda_pe
*pe
;
1554 hose
= pci_bus_to_host(bus
);
1555 phb
= hose
->private_data
;
1556 pdn
= pci_get_pdn(pdev
);
1558 if (phb
->type
== PNV_PHB_IODA2
) {
1559 if (!pdn
->vfs_expanded
) {
1560 dev_info(&pdev
->dev
, "don't support this SRIOV device"
1561 " with non 64bit-prefetchable IOV BAR\n");
1566 * When M64 BARs functions in Single PE mode, the number of VFs
1567 * could be enabled must be less than the number of M64 BARs.
1569 if (pdn
->m64_single_mode
&& num_vfs
> phb
->ioda
.m64_bar_idx
) {
1570 dev_info(&pdev
->dev
, "Not enough M64 BAR for VFs\n");
1574 /* Allocating pe_num_map */
1575 if (pdn
->m64_single_mode
)
1576 pdn
->pe_num_map
= kmalloc(sizeof(*pdn
->pe_num_map
) * num_vfs
,
1579 pdn
->pe_num_map
= kmalloc(sizeof(*pdn
->pe_num_map
), GFP_KERNEL
);
1581 if (!pdn
->pe_num_map
)
1584 if (pdn
->m64_single_mode
)
1585 for (i
= 0; i
< num_vfs
; i
++)
1586 pdn
->pe_num_map
[i
] = IODA_INVALID_PE
;
1588 /* Calculate available PE for required VFs */
1589 if (pdn
->m64_single_mode
) {
1590 for (i
= 0; i
< num_vfs
; i
++) {
1591 pe
= pnv_ioda_alloc_pe(phb
);
1597 pdn
->pe_num_map
[i
] = pe
->pe_number
;
1600 mutex_lock(&phb
->ioda
.pe_alloc_mutex
);
1601 *pdn
->pe_num_map
= bitmap_find_next_zero_area(
1602 phb
->ioda
.pe_alloc
, phb
->ioda
.total_pe_num
,
1604 if (*pdn
->pe_num_map
>= phb
->ioda
.total_pe_num
) {
1605 mutex_unlock(&phb
->ioda
.pe_alloc_mutex
);
1606 dev_info(&pdev
->dev
, "Failed to enable VF%d\n", num_vfs
);
1607 kfree(pdn
->pe_num_map
);
1610 bitmap_set(phb
->ioda
.pe_alloc
, *pdn
->pe_num_map
, num_vfs
);
1611 mutex_unlock(&phb
->ioda
.pe_alloc_mutex
);
1613 pdn
->num_vfs
= num_vfs
;
1615 /* Assign M64 window accordingly */
1616 ret
= pnv_pci_vf_assign_m64(pdev
, num_vfs
);
1618 dev_info(&pdev
->dev
, "Not enough M64 window resources\n");
1623 * When using one M64 BAR to map one IOV BAR, we need to shift
1624 * the IOV BAR according to the PE# allocated to the VFs.
1625 * Otherwise, the PE# for the VF will conflict with others.
1627 if (!pdn
->m64_single_mode
) {
1628 ret
= pnv_pci_vf_resource_shift(pdev
, *pdn
->pe_num_map
);
1635 pnv_ioda_setup_vf_PE(pdev
, num_vfs
);
1640 if (pdn
->m64_single_mode
) {
1641 for (i
= 0; i
< num_vfs
; i
++) {
1642 if (pdn
->pe_num_map
[i
] == IODA_INVALID_PE
)
1645 pe
= &phb
->ioda
.pe_array
[pdn
->pe_num_map
[i
]];
1646 pnv_ioda_free_pe(pe
);
1649 bitmap_clear(phb
->ioda
.pe_alloc
, *pdn
->pe_num_map
, num_vfs
);
1651 /* Releasing pe_num_map */
1652 kfree(pdn
->pe_num_map
);
1657 int pcibios_sriov_disable(struct pci_dev
*pdev
)
1659 pnv_pci_sriov_disable(pdev
);
1661 /* Release PCI data */
1662 remove_dev_pci_data(pdev
);
1666 int pcibios_sriov_enable(struct pci_dev
*pdev
, u16 num_vfs
)
1668 /* Allocate PCI data */
1669 add_dev_pci_data(pdev
);
1671 return pnv_pci_sriov_enable(pdev
, num_vfs
);
1673 #endif /* CONFIG_PCI_IOV */
1675 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb
*phb
, struct pci_dev
*pdev
)
1677 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
1678 struct pnv_ioda_pe
*pe
;
1681 * The function can be called while the PE#
1682 * hasn't been assigned. Do nothing for the
1685 if (!pdn
|| pdn
->pe_number
== IODA_INVALID_PE
)
1688 pe
= &phb
->ioda
.pe_array
[pdn
->pe_number
];
1689 WARN_ON(get_dma_ops(&pdev
->dev
) != &dma_iommu_ops
);
1690 set_dma_offset(&pdev
->dev
, pe
->tce_bypass_base
);
1691 set_iommu_table_base(&pdev
->dev
, pe
->table_group
.tables
[0]);
1693 * Note: iommu_add_device() will fail here as
1694 * for physical PE: the device is already added by now;
1695 * for virtual PE: sysfs entries are not ready yet and
1696 * tce_iommu_bus_notifier will add the device to a group later.
1700 static int pnv_pci_ioda_dma_set_mask(struct pci_dev
*pdev
, u64 dma_mask
)
1702 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
1703 struct pnv_phb
*phb
= hose
->private_data
;
1704 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
1705 struct pnv_ioda_pe
*pe
;
1707 bool bypass
= false;
1709 if (WARN_ON(!pdn
|| pdn
->pe_number
== IODA_INVALID_PE
))
1712 pe
= &phb
->ioda
.pe_array
[pdn
->pe_number
];
1713 if (pe
->tce_bypass_enabled
) {
1714 top
= pe
->tce_bypass_base
+ memblock_end_of_DRAM() - 1;
1715 bypass
= (dma_mask
>= top
);
1719 dev_info(&pdev
->dev
, "Using 64-bit DMA iommu bypass\n");
1720 set_dma_ops(&pdev
->dev
, &dma_direct_ops
);
1722 dev_info(&pdev
->dev
, "Using 32-bit DMA via iommu\n");
1723 set_dma_ops(&pdev
->dev
, &dma_iommu_ops
);
1725 *pdev
->dev
.dma_mask
= dma_mask
;
1727 /* Update peer npu devices */
1728 pnv_npu_try_dma_set_bypass(pdev
, bypass
);
1733 static u64
pnv_pci_ioda_dma_get_required_mask(struct pci_dev
*pdev
)
1735 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
1736 struct pnv_phb
*phb
= hose
->private_data
;
1737 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
1738 struct pnv_ioda_pe
*pe
;
1741 if (WARN_ON(!pdn
|| pdn
->pe_number
== IODA_INVALID_PE
))
1744 pe
= &phb
->ioda
.pe_array
[pdn
->pe_number
];
1745 if (!pe
->tce_bypass_enabled
)
1746 return __dma_get_required_mask(&pdev
->dev
);
1749 end
= pe
->tce_bypass_base
+ memblock_end_of_DRAM();
1750 mask
= 1ULL << (fls64(end
) - 1);
1756 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe
*pe
,
1757 struct pci_bus
*bus
)
1759 struct pci_dev
*dev
;
1761 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1762 set_iommu_table_base(&dev
->dev
, pe
->table_group
.tables
[0]);
1763 set_dma_offset(&dev
->dev
, pe
->tce_bypass_base
);
1764 iommu_add_device(&dev
->dev
);
1766 if ((pe
->flags
& PNV_IODA_PE_BUS_ALL
) && dev
->subordinate
)
1767 pnv_ioda_setup_bus_dma(pe
, dev
->subordinate
);
1771 static inline __be64 __iomem
*pnv_ioda_get_inval_reg(struct pnv_phb
*phb
,
1774 return real_mode
? (__be64 __iomem
*)(phb
->regs_phys
+ 0x210) :
1775 (phb
->regs
+ 0x210);
1778 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table
*tbl
,
1779 unsigned long index
, unsigned long npages
, bool rm
)
1781 struct iommu_table_group_link
*tgl
= list_first_entry_or_null(
1782 &tbl
->it_group_list
, struct iommu_table_group_link
,
1784 struct pnv_ioda_pe
*pe
= container_of(tgl
->table_group
,
1785 struct pnv_ioda_pe
, table_group
);
1786 __be64 __iomem
*invalidate
= pnv_ioda_get_inval_reg(pe
->phb
, rm
);
1787 unsigned long start
, end
, inc
;
1789 start
= __pa(((__be64
*)tbl
->it_base
) + index
- tbl
->it_offset
);
1790 end
= __pa(((__be64
*)tbl
->it_base
) + index
- tbl
->it_offset
+
1793 /* p7ioc-style invalidation, 2 TCEs per write */
1794 start
|= (1ull << 63);
1795 end
|= (1ull << 63);
1797 end
|= inc
- 1; /* round up end to be different than start */
1799 mb(); /* Ensure above stores are visible */
1800 while (start
<= end
) {
1802 __raw_rm_writeq(cpu_to_be64(start
), invalidate
);
1804 __raw_writeq(cpu_to_be64(start
), invalidate
);
1809 * The iommu layer will do another mb() for us on build()
1810 * and we don't care on free()
1814 static int pnv_ioda1_tce_build(struct iommu_table
*tbl
, long index
,
1815 long npages
, unsigned long uaddr
,
1816 enum dma_data_direction direction
,
1817 unsigned long attrs
)
1819 int ret
= pnv_tce_build(tbl
, index
, npages
, uaddr
, direction
,
1823 pnv_pci_p7ioc_tce_invalidate(tbl
, index
, npages
, false);
1828 #ifdef CONFIG_IOMMU_API
1829 static int pnv_ioda1_tce_xchg(struct iommu_table
*tbl
, long index
,
1830 unsigned long *hpa
, enum dma_data_direction
*direction
)
1832 long ret
= pnv_tce_xchg(tbl
, index
, hpa
, direction
);
1835 pnv_pci_p7ioc_tce_invalidate(tbl
, index
, 1, false);
1841 static void pnv_ioda1_tce_free(struct iommu_table
*tbl
, long index
,
1844 pnv_tce_free(tbl
, index
, npages
);
1846 pnv_pci_p7ioc_tce_invalidate(tbl
, index
, npages
, false);
1849 static struct iommu_table_ops pnv_ioda1_iommu_ops
= {
1850 .set
= pnv_ioda1_tce_build
,
1851 #ifdef CONFIG_IOMMU_API
1852 .exchange
= pnv_ioda1_tce_xchg
,
1854 .clear
= pnv_ioda1_tce_free
,
1858 #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0)
1859 #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1)
1860 #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2)
1862 void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb
*phb
, bool rm
)
1864 __be64 __iomem
*invalidate
= pnv_ioda_get_inval_reg(phb
, rm
);
1865 const unsigned long val
= PHB3_TCE_KILL_INVAL_ALL
;
1867 mb(); /* Ensure previous TCE table stores are visible */
1869 __raw_rm_writeq(cpu_to_be64(val
), invalidate
);
1871 __raw_writeq(cpu_to_be64(val
), invalidate
);
1874 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe
*pe
)
1876 /* 01xb - invalidate TCEs that match the specified PE# */
1877 __be64 __iomem
*invalidate
= pnv_ioda_get_inval_reg(pe
->phb
, false);
1878 unsigned long val
= PHB3_TCE_KILL_INVAL_PE
| (pe
->pe_number
& 0xFF);
1880 mb(); /* Ensure above stores are visible */
1881 __raw_writeq(cpu_to_be64(val
), invalidate
);
1884 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe
*pe
, bool rm
,
1885 unsigned shift
, unsigned long index
,
1886 unsigned long npages
)
1888 __be64 __iomem
*invalidate
= pnv_ioda_get_inval_reg(pe
->phb
, rm
);
1889 unsigned long start
, end
, inc
;
1891 /* We'll invalidate DMA address in PE scope */
1892 start
= PHB3_TCE_KILL_INVAL_ONE
;
1893 start
|= (pe
->pe_number
& 0xFF);
1896 /* Figure out the start, end and step */
1897 start
|= (index
<< shift
);
1898 end
|= ((index
+ npages
- 1) << shift
);
1899 inc
= (0x1ull
<< shift
);
1902 while (start
<= end
) {
1904 __raw_rm_writeq(cpu_to_be64(start
), invalidate
);
1906 __raw_writeq(cpu_to_be64(start
), invalidate
);
1911 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe
*pe
)
1913 struct pnv_phb
*phb
= pe
->phb
;
1915 if (phb
->model
== PNV_PHB_MODEL_PHB3
&& phb
->regs
)
1916 pnv_pci_phb3_tce_invalidate_pe(pe
);
1918 opal_pci_tce_kill(phb
->opal_id
, OPAL_PCI_TCE_KILL_PE
,
1919 pe
->pe_number
, 0, 0, 0);
1922 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table
*tbl
,
1923 unsigned long index
, unsigned long npages
, bool rm
)
1925 struct iommu_table_group_link
*tgl
;
1927 list_for_each_entry_rcu(tgl
, &tbl
->it_group_list
, next
) {
1928 struct pnv_ioda_pe
*pe
= container_of(tgl
->table_group
,
1929 struct pnv_ioda_pe
, table_group
);
1930 struct pnv_phb
*phb
= pe
->phb
;
1931 unsigned int shift
= tbl
->it_page_shift
;
1933 if (phb
->type
== PNV_PHB_NPU
) {
1935 * The NVLink hardware does not support TCE kill
1936 * per TCE entry so we have to invalidate
1937 * the entire cache for it.
1939 pnv_pci_phb3_tce_invalidate_entire(phb
, rm
);
1942 if (phb
->model
== PNV_PHB_MODEL_PHB3
&& phb
->regs
)
1943 pnv_pci_phb3_tce_invalidate(pe
, rm
, shift
,
1946 opal_rm_pci_tce_kill(phb
->opal_id
,
1947 OPAL_PCI_TCE_KILL_PAGES
,
1948 pe
->pe_number
, 1u << shift
,
1949 index
<< shift
, npages
);
1951 opal_pci_tce_kill(phb
->opal_id
,
1952 OPAL_PCI_TCE_KILL_PAGES
,
1953 pe
->pe_number
, 1u << shift
,
1954 index
<< shift
, npages
);
1958 static int pnv_ioda2_tce_build(struct iommu_table
*tbl
, long index
,
1959 long npages
, unsigned long uaddr
,
1960 enum dma_data_direction direction
,
1961 unsigned long attrs
)
1963 int ret
= pnv_tce_build(tbl
, index
, npages
, uaddr
, direction
,
1967 pnv_pci_ioda2_tce_invalidate(tbl
, index
, npages
, false);
1972 #ifdef CONFIG_IOMMU_API
1973 static int pnv_ioda2_tce_xchg(struct iommu_table
*tbl
, long index
,
1974 unsigned long *hpa
, enum dma_data_direction
*direction
)
1976 long ret
= pnv_tce_xchg(tbl
, index
, hpa
, direction
);
1979 pnv_pci_ioda2_tce_invalidate(tbl
, index
, 1, false);
1985 static void pnv_ioda2_tce_free(struct iommu_table
*tbl
, long index
,
1988 pnv_tce_free(tbl
, index
, npages
);
1990 pnv_pci_ioda2_tce_invalidate(tbl
, index
, npages
, false);
1993 static void pnv_ioda2_table_free(struct iommu_table
*tbl
)
1995 pnv_pci_ioda2_table_free_pages(tbl
);
1996 iommu_free_table(tbl
, "pnv");
1999 static struct iommu_table_ops pnv_ioda2_iommu_ops
= {
2000 .set
= pnv_ioda2_tce_build
,
2001 #ifdef CONFIG_IOMMU_API
2002 .exchange
= pnv_ioda2_tce_xchg
,
2004 .clear
= pnv_ioda2_tce_free
,
2006 .free
= pnv_ioda2_table_free
,
2009 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev
*dev
, void *data
)
2011 unsigned int *weight
= (unsigned int *)data
;
2013 /* This is quite simplistic. The "base" weight of a device
2014 * is 10. 0 means no DMA is to be accounted for it.
2016 if (dev
->hdr_type
!= PCI_HEADER_TYPE_NORMAL
)
2019 if (dev
->class == PCI_CLASS_SERIAL_USB_UHCI
||
2020 dev
->class == PCI_CLASS_SERIAL_USB_OHCI
||
2021 dev
->class == PCI_CLASS_SERIAL_USB_EHCI
)
2023 else if ((dev
->class >> 8) == PCI_CLASS_STORAGE_RAID
)
2031 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe
*pe
)
2033 unsigned int weight
= 0;
2035 /* SRIOV VF has same DMA32 weight as its PF */
2036 #ifdef CONFIG_PCI_IOV
2037 if ((pe
->flags
& PNV_IODA_PE_VF
) && pe
->parent_dev
) {
2038 pnv_pci_ioda_dev_dma_weight(pe
->parent_dev
, &weight
);
2043 if ((pe
->flags
& PNV_IODA_PE_DEV
) && pe
->pdev
) {
2044 pnv_pci_ioda_dev_dma_weight(pe
->pdev
, &weight
);
2045 } else if ((pe
->flags
& PNV_IODA_PE_BUS
) && pe
->pbus
) {
2046 struct pci_dev
*pdev
;
2048 list_for_each_entry(pdev
, &pe
->pbus
->devices
, bus_list
)
2049 pnv_pci_ioda_dev_dma_weight(pdev
, &weight
);
2050 } else if ((pe
->flags
& PNV_IODA_PE_BUS_ALL
) && pe
->pbus
) {
2051 pci_walk_bus(pe
->pbus
, pnv_pci_ioda_dev_dma_weight
, &weight
);
2057 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb
*phb
,
2058 struct pnv_ioda_pe
*pe
)
2061 struct page
*tce_mem
= NULL
;
2062 struct iommu_table
*tbl
;
2063 unsigned int weight
, total_weight
= 0;
2064 unsigned int tce32_segsz
, base
, segs
, avail
, i
;
2068 /* XXX FIXME: Handle 64-bit only DMA devices */
2069 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2070 /* XXX FIXME: Allocate multi-level tables on PHB3 */
2071 weight
= pnv_pci_ioda_pe_dma_weight(pe
);
2075 pci_walk_bus(phb
->hose
->bus
, pnv_pci_ioda_dev_dma_weight
,
2077 segs
= (weight
* phb
->ioda
.dma32_count
) / total_weight
;
2082 * Allocate contiguous DMA32 segments. We begin with the expected
2083 * number of segments. With one more attempt, the number of DMA32
2084 * segments to be allocated is decreased by one until one segment
2085 * is allocated successfully.
2088 for (base
= 0; base
<= phb
->ioda
.dma32_count
- segs
; base
++) {
2089 for (avail
= 0, i
= base
; i
< base
+ segs
; i
++) {
2090 if (phb
->ioda
.dma32_segmap
[i
] ==
2101 pe_warn(pe
, "No available DMA32 segments\n");
2106 tbl
= pnv_pci_table_alloc(phb
->hose
->node
);
2107 iommu_register_group(&pe
->table_group
, phb
->hose
->global_number
,
2109 pnv_pci_link_table_and_group(phb
->hose
->node
, 0, tbl
, &pe
->table_group
);
2111 /* Grab a 32-bit TCE table */
2112 pe_info(pe
, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2113 weight
, total_weight
, base
, segs
);
2114 pe_info(pe
, " Setting up 32-bit TCE table at %08x..%08x\n",
2115 base
* PNV_IODA1_DMA32_SEGSIZE
,
2116 (base
+ segs
) * PNV_IODA1_DMA32_SEGSIZE
- 1);
2118 /* XXX Currently, we allocate one big contiguous table for the
2119 * TCEs. We only really need one chunk per 256M of TCE space
2120 * (ie per segment) but that's an optimization for later, it
2121 * requires some added smarts with our get/put_tce implementation
2123 * Each TCE page is 4KB in size and each TCE entry occupies 8
2126 tce32_segsz
= PNV_IODA1_DMA32_SEGSIZE
>> (IOMMU_PAGE_SHIFT_4K
- 3);
2127 tce_mem
= alloc_pages_node(phb
->hose
->node
, GFP_KERNEL
,
2128 get_order(tce32_segsz
* segs
));
2130 pe_err(pe
, " Failed to allocate a 32-bit TCE memory\n");
2133 addr
= page_address(tce_mem
);
2134 memset(addr
, 0, tce32_segsz
* segs
);
2137 for (i
= 0; i
< segs
; i
++) {
2138 rc
= opal_pci_map_pe_dma_window(phb
->opal_id
,
2141 __pa(addr
) + tce32_segsz
* i
,
2142 tce32_segsz
, IOMMU_PAGE_SIZE_4K
);
2144 pe_err(pe
, " Failed to configure 32-bit TCE table,"
2150 /* Setup DMA32 segment mapping */
2151 for (i
= base
; i
< base
+ segs
; i
++)
2152 phb
->ioda
.dma32_segmap
[i
] = pe
->pe_number
;
2154 /* Setup linux iommu table */
2155 pnv_pci_setup_iommu_table(tbl
, addr
, tce32_segsz
* segs
,
2156 base
* PNV_IODA1_DMA32_SEGSIZE
,
2157 IOMMU_PAGE_SHIFT_4K
);
2159 tbl
->it_ops
= &pnv_ioda1_iommu_ops
;
2160 pe
->table_group
.tce32_start
= tbl
->it_offset
<< tbl
->it_page_shift
;
2161 pe
->table_group
.tce32_size
= tbl
->it_size
<< tbl
->it_page_shift
;
2162 iommu_init_table(tbl
, phb
->hose
->node
);
2164 if (pe
->flags
& PNV_IODA_PE_DEV
) {
2166 * Setting table base here only for carrying iommu_group
2167 * further down to let iommu_add_device() do the job.
2168 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2170 set_iommu_table_base(&pe
->pdev
->dev
, tbl
);
2171 iommu_add_device(&pe
->pdev
->dev
);
2172 } else if (pe
->flags
& (PNV_IODA_PE_BUS
| PNV_IODA_PE_BUS_ALL
))
2173 pnv_ioda_setup_bus_dma(pe
, pe
->pbus
);
2177 /* XXX Failure: Try to fallback to 64-bit only ? */
2179 __free_pages(tce_mem
, get_order(tce32_segsz
* segs
));
2181 pnv_pci_unlink_table_and_group(tbl
, &pe
->table_group
);
2182 iommu_free_table(tbl
, "pnv");
2186 static long pnv_pci_ioda2_set_window(struct iommu_table_group
*table_group
,
2187 int num
, struct iommu_table
*tbl
)
2189 struct pnv_ioda_pe
*pe
= container_of(table_group
, struct pnv_ioda_pe
,
2191 struct pnv_phb
*phb
= pe
->phb
;
2193 const unsigned long size
= tbl
->it_indirect_levels
?
2194 tbl
->it_level_size
: tbl
->it_size
;
2195 const __u64 start_addr
= tbl
->it_offset
<< tbl
->it_page_shift
;
2196 const __u64 win_size
= tbl
->it_size
<< tbl
->it_page_shift
;
2198 pe_info(pe
, "Setting up window#%d %llx..%llx pg=%x\n", num
,
2199 start_addr
, start_addr
+ win_size
- 1,
2200 IOMMU_PAGE_SIZE(tbl
));
2203 * Map TCE table through TVT. The TVE index is the PE number
2204 * shifted by 1 bit for 32-bits DMA space.
2206 rc
= opal_pci_map_pe_dma_window(phb
->opal_id
,
2208 (pe
->pe_number
<< 1) + num
,
2209 tbl
->it_indirect_levels
+ 1,
2212 IOMMU_PAGE_SIZE(tbl
));
2214 pe_err(pe
, "Failed to configure TCE table, err %ld\n", rc
);
2218 pnv_pci_link_table_and_group(phb
->hose
->node
, num
,
2219 tbl
, &pe
->table_group
);
2220 pnv_pci_phb3_tce_invalidate_pe(pe
);
2225 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe
*pe
, bool enable
)
2227 uint16_t window_id
= (pe
->pe_number
<< 1 ) + 1;
2230 pe_info(pe
, "%sabling 64-bit DMA bypass\n", enable
? "En" : "Dis");
2232 phys_addr_t top
= memblock_end_of_DRAM();
2234 top
= roundup_pow_of_two(top
);
2235 rc
= opal_pci_map_pe_dma_window_real(pe
->phb
->opal_id
,
2238 pe
->tce_bypass_base
,
2241 rc
= opal_pci_map_pe_dma_window_real(pe
->phb
->opal_id
,
2244 pe
->tce_bypass_base
,
2248 pe_err(pe
, "OPAL error %lld configuring bypass window\n", rc
);
2250 pe
->tce_bypass_enabled
= enable
;
2253 static long pnv_pci_ioda2_table_alloc_pages(int nid
, __u64 bus_offset
,
2254 __u32 page_shift
, __u64 window_size
, __u32 levels
,
2255 struct iommu_table
*tbl
);
2257 static long pnv_pci_ioda2_create_table(struct iommu_table_group
*table_group
,
2258 int num
, __u32 page_shift
, __u64 window_size
, __u32 levels
,
2259 struct iommu_table
**ptbl
)
2261 struct pnv_ioda_pe
*pe
= container_of(table_group
, struct pnv_ioda_pe
,
2263 int nid
= pe
->phb
->hose
->node
;
2264 __u64 bus_offset
= num
? pe
->tce_bypass_base
: table_group
->tce32_start
;
2266 struct iommu_table
*tbl
;
2268 tbl
= pnv_pci_table_alloc(nid
);
2272 ret
= pnv_pci_ioda2_table_alloc_pages(nid
,
2273 bus_offset
, page_shift
, window_size
,
2276 iommu_free_table(tbl
, "pnv");
2280 tbl
->it_ops
= &pnv_ioda2_iommu_ops
;
2287 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe
*pe
)
2289 struct iommu_table
*tbl
= NULL
;
2293 * crashkernel= specifies the kdump kernel's maximum memory at
2294 * some offset and there is no guaranteed the result is a power
2295 * of 2, which will cause errors later.
2297 const u64 max_memory
= __rounddown_pow_of_two(memory_hotplug_max());
2300 * In memory constrained environments, e.g. kdump kernel, the
2301 * DMA window can be larger than available memory, which will
2302 * cause errors later.
2304 const u64 window_size
= min((u64
)pe
->table_group
.tce32_size
, max_memory
);
2306 rc
= pnv_pci_ioda2_create_table(&pe
->table_group
, 0,
2307 IOMMU_PAGE_SHIFT_4K
,
2309 POWERNV_IOMMU_DEFAULT_LEVELS
, &tbl
);
2311 pe_err(pe
, "Failed to create 32-bit TCE table, err %ld",
2316 iommu_init_table(tbl
, pe
->phb
->hose
->node
);
2318 rc
= pnv_pci_ioda2_set_window(&pe
->table_group
, 0, tbl
);
2320 pe_err(pe
, "Failed to configure 32-bit TCE table, err %ld\n",
2322 pnv_ioda2_table_free(tbl
);
2326 if (!pnv_iommu_bypass_disabled
)
2327 pnv_pci_ioda2_set_bypass(pe
, true);
2330 * Setting table base here only for carrying iommu_group
2331 * further down to let iommu_add_device() do the job.
2332 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2334 if (pe
->flags
& PNV_IODA_PE_DEV
)
2335 set_iommu_table_base(&pe
->pdev
->dev
, tbl
);
2340 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2341 static long pnv_pci_ioda2_unset_window(struct iommu_table_group
*table_group
,
2344 struct pnv_ioda_pe
*pe
= container_of(table_group
, struct pnv_ioda_pe
,
2346 struct pnv_phb
*phb
= pe
->phb
;
2349 pe_info(pe
, "Removing DMA window #%d\n", num
);
2351 ret
= opal_pci_map_pe_dma_window(phb
->opal_id
, pe
->pe_number
,
2352 (pe
->pe_number
<< 1) + num
,
2353 0/* levels */, 0/* table address */,
2354 0/* table size */, 0/* page size */);
2356 pe_warn(pe
, "Unmapping failed, ret = %ld\n", ret
);
2358 pnv_pci_phb3_tce_invalidate_pe(pe
);
2360 pnv_pci_unlink_table_and_group(table_group
->tables
[num
], table_group
);
2366 #ifdef CONFIG_IOMMU_API
2367 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift
,
2368 __u64 window_size
, __u32 levels
)
2370 unsigned long bytes
= 0;
2371 const unsigned window_shift
= ilog2(window_size
);
2372 unsigned entries_shift
= window_shift
- page_shift
;
2373 unsigned table_shift
= entries_shift
+ 3;
2374 unsigned long tce_table_size
= max(0x1000UL
, 1UL << table_shift
);
2375 unsigned long direct_table_size
;
2377 if (!levels
|| (levels
> POWERNV_IOMMU_MAX_LEVELS
) ||
2378 (window_size
> memory_hotplug_max()) ||
2379 !is_power_of_2(window_size
))
2382 /* Calculate a direct table size from window_size and levels */
2383 entries_shift
= (entries_shift
+ levels
- 1) / levels
;
2384 table_shift
= entries_shift
+ 3;
2385 table_shift
= max_t(unsigned, table_shift
, PAGE_SHIFT
);
2386 direct_table_size
= 1UL << table_shift
;
2388 for ( ; levels
; --levels
) {
2389 bytes
+= _ALIGN_UP(tce_table_size
, direct_table_size
);
2391 tce_table_size
/= direct_table_size
;
2392 tce_table_size
<<= 3;
2393 tce_table_size
= _ALIGN_UP(tce_table_size
, direct_table_size
);
2399 static void pnv_ioda2_take_ownership(struct iommu_table_group
*table_group
)
2401 struct pnv_ioda_pe
*pe
= container_of(table_group
, struct pnv_ioda_pe
,
2403 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2404 struct iommu_table
*tbl
= pe
->table_group
.tables
[0];
2406 pnv_pci_ioda2_set_bypass(pe
, false);
2407 pnv_pci_ioda2_unset_window(&pe
->table_group
, 0);
2408 pnv_ioda2_table_free(tbl
);
2411 static void pnv_ioda2_release_ownership(struct iommu_table_group
*table_group
)
2413 struct pnv_ioda_pe
*pe
= container_of(table_group
, struct pnv_ioda_pe
,
2416 pnv_pci_ioda2_setup_default_config(pe
);
2419 static struct iommu_table_group_ops pnv_pci_ioda2_ops
= {
2420 .get_table_size
= pnv_pci_ioda2_get_table_size
,
2421 .create_table
= pnv_pci_ioda2_create_table
,
2422 .set_window
= pnv_pci_ioda2_set_window
,
2423 .unset_window
= pnv_pci_ioda2_unset_window
,
2424 .take_ownership
= pnv_ioda2_take_ownership
,
2425 .release_ownership
= pnv_ioda2_release_ownership
,
2428 static int gpe_table_group_to_npe_cb(struct device
*dev
, void *opaque
)
2430 struct pci_controller
*hose
;
2431 struct pnv_phb
*phb
;
2432 struct pnv_ioda_pe
**ptmppe
= opaque
;
2433 struct pci_dev
*pdev
= container_of(dev
, struct pci_dev
, dev
);
2434 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
2436 if (!pdn
|| pdn
->pe_number
== IODA_INVALID_PE
)
2439 hose
= pci_bus_to_host(pdev
->bus
);
2440 phb
= hose
->private_data
;
2441 if (phb
->type
!= PNV_PHB_NPU
)
2444 *ptmppe
= &phb
->ioda
.pe_array
[pdn
->pe_number
];
2450 * This returns PE of associated NPU.
2451 * This assumes that NPU is in the same IOMMU group with GPU and there is
2454 static struct pnv_ioda_pe
*gpe_table_group_to_npe(
2455 struct iommu_table_group
*table_group
)
2457 struct pnv_ioda_pe
*npe
= NULL
;
2458 int ret
= iommu_group_for_each_dev(table_group
->group
, &npe
,
2459 gpe_table_group_to_npe_cb
);
2461 BUG_ON(!ret
|| !npe
);
2466 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group
*table_group
,
2467 int num
, struct iommu_table
*tbl
)
2469 long ret
= pnv_pci_ioda2_set_window(table_group
, num
, tbl
);
2474 ret
= pnv_npu_set_window(gpe_table_group_to_npe(table_group
), num
, tbl
);
2476 pnv_pci_ioda2_unset_window(table_group
, num
);
2481 static long pnv_pci_ioda2_npu_unset_window(
2482 struct iommu_table_group
*table_group
,
2485 long ret
= pnv_pci_ioda2_unset_window(table_group
, num
);
2490 return pnv_npu_unset_window(gpe_table_group_to_npe(table_group
), num
);
2493 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group
*table_group
)
2496 * Detach NPU first as pnv_ioda2_take_ownership() will destroy
2497 * the iommu_table if 32bit DMA is enabled.
2499 pnv_npu_take_ownership(gpe_table_group_to_npe(table_group
));
2500 pnv_ioda2_take_ownership(table_group
);
2503 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops
= {
2504 .get_table_size
= pnv_pci_ioda2_get_table_size
,
2505 .create_table
= pnv_pci_ioda2_create_table
,
2506 .set_window
= pnv_pci_ioda2_npu_set_window
,
2507 .unset_window
= pnv_pci_ioda2_npu_unset_window
,
2508 .take_ownership
= pnv_ioda2_npu_take_ownership
,
2509 .release_ownership
= pnv_ioda2_release_ownership
,
2512 static void pnv_pci_ioda_setup_iommu_api(void)
2514 struct pci_controller
*hose
, *tmp
;
2515 struct pnv_phb
*phb
;
2516 struct pnv_ioda_pe
*pe
, *gpe
;
2519 * Now we have all PHBs discovered, time to add NPU devices to
2520 * the corresponding IOMMU groups.
2522 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
2523 phb
= hose
->private_data
;
2525 if (phb
->type
!= PNV_PHB_NPU
)
2528 list_for_each_entry(pe
, &phb
->ioda
.pe_list
, list
) {
2529 gpe
= pnv_pci_npu_setup_iommu(pe
);
2531 gpe
->table_group
.ops
= &pnv_pci_ioda2_npu_ops
;
2535 #else /* !CONFIG_IOMMU_API */
2536 static void pnv_pci_ioda_setup_iommu_api(void) { };
2539 static __be64
*pnv_pci_ioda2_table_do_alloc_pages(int nid
, unsigned shift
,
2540 unsigned levels
, unsigned long limit
,
2541 unsigned long *current_offset
, unsigned long *total_allocated
)
2543 struct page
*tce_mem
= NULL
;
2545 unsigned order
= max_t(unsigned, shift
, PAGE_SHIFT
) - PAGE_SHIFT
;
2546 unsigned long allocated
= 1UL << (order
+ PAGE_SHIFT
);
2547 unsigned entries
= 1UL << (shift
- 3);
2550 tce_mem
= alloc_pages_node(nid
, GFP_KERNEL
, order
);
2552 pr_err("Failed to allocate a TCE memory, order=%d\n", order
);
2555 addr
= page_address(tce_mem
);
2556 memset(addr
, 0, allocated
);
2557 *total_allocated
+= allocated
;
2561 *current_offset
+= allocated
;
2565 for (i
= 0; i
< entries
; ++i
) {
2566 tmp
= pnv_pci_ioda2_table_do_alloc_pages(nid
, shift
,
2567 levels
, limit
, current_offset
, total_allocated
);
2571 addr
[i
] = cpu_to_be64(__pa(tmp
) |
2572 TCE_PCI_READ
| TCE_PCI_WRITE
);
2574 if (*current_offset
>= limit
)
2581 static void pnv_pci_ioda2_table_do_free_pages(__be64
*addr
,
2582 unsigned long size
, unsigned level
);
2584 static long pnv_pci_ioda2_table_alloc_pages(int nid
, __u64 bus_offset
,
2585 __u32 page_shift
, __u64 window_size
, __u32 levels
,
2586 struct iommu_table
*tbl
)
2589 unsigned long offset
= 0, level_shift
, total_allocated
= 0;
2590 const unsigned window_shift
= ilog2(window_size
);
2591 unsigned entries_shift
= window_shift
- page_shift
;
2592 unsigned table_shift
= max_t(unsigned, entries_shift
+ 3, PAGE_SHIFT
);
2593 const unsigned long tce_table_size
= 1UL << table_shift
;
2595 if (!levels
|| (levels
> POWERNV_IOMMU_MAX_LEVELS
))
2598 if ((window_size
> memory_hotplug_max()) || !is_power_of_2(window_size
))
2601 /* Adjust direct table size from window_size and levels */
2602 entries_shift
= (entries_shift
+ levels
- 1) / levels
;
2603 level_shift
= entries_shift
+ 3;
2604 level_shift
= max_t(unsigned, level_shift
, PAGE_SHIFT
);
2606 /* Allocate TCE table */
2607 addr
= pnv_pci_ioda2_table_do_alloc_pages(nid
, level_shift
,
2608 levels
, tce_table_size
, &offset
, &total_allocated
);
2610 /* addr==NULL means that the first level allocation failed */
2615 * First level was allocated but some lower level failed as
2616 * we did not allocate as much as we wanted,
2617 * release partially allocated table.
2619 if (offset
< tce_table_size
) {
2620 pnv_pci_ioda2_table_do_free_pages(addr
,
2621 1ULL << (level_shift
- 3), levels
- 1);
2625 /* Setup linux iommu table */
2626 pnv_pci_setup_iommu_table(tbl
, addr
, tce_table_size
, bus_offset
,
2628 tbl
->it_level_size
= 1ULL << (level_shift
- 3);
2629 tbl
->it_indirect_levels
= levels
- 1;
2630 tbl
->it_allocated_size
= total_allocated
;
2632 pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n",
2633 window_size
, tce_table_size
, bus_offset
);
2638 static void pnv_pci_ioda2_table_do_free_pages(__be64
*addr
,
2639 unsigned long size
, unsigned level
)
2641 const unsigned long addr_ul
= (unsigned long) addr
&
2642 ~(TCE_PCI_READ
| TCE_PCI_WRITE
);
2646 u64
*tmp
= (u64
*) addr_ul
;
2648 for (i
= 0; i
< size
; ++i
) {
2649 unsigned long hpa
= be64_to_cpu(tmp
[i
]);
2651 if (!(hpa
& (TCE_PCI_READ
| TCE_PCI_WRITE
)))
2654 pnv_pci_ioda2_table_do_free_pages(__va(hpa
), size
,
2659 free_pages(addr_ul
, get_order(size
<< 3));
2662 static void pnv_pci_ioda2_table_free_pages(struct iommu_table
*tbl
)
2664 const unsigned long size
= tbl
->it_indirect_levels
?
2665 tbl
->it_level_size
: tbl
->it_size
;
2670 pnv_pci_ioda2_table_do_free_pages((__be64
*)tbl
->it_base
, size
,
2671 tbl
->it_indirect_levels
);
2674 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb
*phb
,
2675 struct pnv_ioda_pe
*pe
)
2679 if (!pnv_pci_ioda_pe_dma_weight(pe
))
2682 /* TVE #1 is selected by PCI address bit 59 */
2683 pe
->tce_bypass_base
= 1ull << 59;
2685 iommu_register_group(&pe
->table_group
, phb
->hose
->global_number
,
2688 /* The PE will reserve all possible 32-bits space */
2689 pe_info(pe
, "Setting up 32-bit TCE table at 0..%08x\n",
2690 phb
->ioda
.m32_pci_base
);
2692 /* Setup linux iommu table */
2693 pe
->table_group
.tce32_start
= 0;
2694 pe
->table_group
.tce32_size
= phb
->ioda
.m32_pci_base
;
2695 pe
->table_group
.max_dynamic_windows_supported
=
2696 IOMMU_TABLE_GROUP_MAX_TABLES
;
2697 pe
->table_group
.max_levels
= POWERNV_IOMMU_MAX_LEVELS
;
2698 pe
->table_group
.pgsizes
= SZ_4K
| SZ_64K
| SZ_16M
;
2699 #ifdef CONFIG_IOMMU_API
2700 pe
->table_group
.ops
= &pnv_pci_ioda2_ops
;
2703 rc
= pnv_pci_ioda2_setup_default_config(pe
);
2707 if (pe
->flags
& PNV_IODA_PE_DEV
)
2708 iommu_add_device(&pe
->pdev
->dev
);
2709 else if (pe
->flags
& (PNV_IODA_PE_BUS
| PNV_IODA_PE_BUS_ALL
))
2710 pnv_ioda_setup_bus_dma(pe
, pe
->pbus
);
2713 #ifdef CONFIG_PCI_MSI
2714 static void pnv_ioda2_msi_eoi(struct irq_data
*d
)
2716 unsigned int hw_irq
= (unsigned int)irqd_to_hwirq(d
);
2717 struct irq_chip
*chip
= irq_data_get_irq_chip(d
);
2718 struct pnv_phb
*phb
= container_of(chip
, struct pnv_phb
,
2722 rc
= opal_pci_msi_eoi(phb
->opal_id
, hw_irq
);
2729 void pnv_set_msi_irq_chip(struct pnv_phb
*phb
, unsigned int virq
)
2731 struct irq_data
*idata
;
2732 struct irq_chip
*ichip
;
2734 /* The MSI EOI OPAL call is only needed on PHB3 */
2735 if (phb
->model
!= PNV_PHB_MODEL_PHB3
)
2738 if (!phb
->ioda
.irq_chip_init
) {
2740 * First time we setup an MSI IRQ, we need to setup the
2741 * corresponding IRQ chip to route correctly.
2743 idata
= irq_get_irq_data(virq
);
2744 ichip
= irq_data_get_irq_chip(idata
);
2745 phb
->ioda
.irq_chip_init
= 1;
2746 phb
->ioda
.irq_chip
= *ichip
;
2747 phb
->ioda
.irq_chip
.irq_eoi
= pnv_ioda2_msi_eoi
;
2749 irq_set_chip(virq
, &phb
->ioda
.irq_chip
);
2752 static int pnv_pci_ioda_msi_setup(struct pnv_phb
*phb
, struct pci_dev
*dev
,
2753 unsigned int hwirq
, unsigned int virq
,
2754 unsigned int is_64
, struct msi_msg
*msg
)
2756 struct pnv_ioda_pe
*pe
= pnv_ioda_get_pe(dev
);
2757 unsigned int xive_num
= hwirq
- phb
->msi_base
;
2761 /* No PE assigned ? bail out ... no MSI for you ! */
2765 /* Check if we have an MVE */
2766 if (pe
->mve_number
< 0)
2769 /* Force 32-bit MSI on some broken devices */
2770 if (dev
->no_64bit_msi
)
2773 /* Assign XIVE to PE */
2774 rc
= opal_pci_set_xive_pe(phb
->opal_id
, pe
->pe_number
, xive_num
);
2776 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2777 pci_name(dev
), rc
, xive_num
);
2784 rc
= opal_get_msi_64(phb
->opal_id
, pe
->mve_number
, xive_num
, 1,
2787 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2791 msg
->address_hi
= be64_to_cpu(addr64
) >> 32;
2792 msg
->address_lo
= be64_to_cpu(addr64
) & 0xfffffffful
;
2796 rc
= opal_get_msi_32(phb
->opal_id
, pe
->mve_number
, xive_num
, 1,
2799 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2803 msg
->address_hi
= 0;
2804 msg
->address_lo
= be32_to_cpu(addr32
);
2806 msg
->data
= be32_to_cpu(data
);
2808 pnv_set_msi_irq_chip(phb
, virq
);
2810 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2811 " address=%x_%08x data=%x PE# %d\n",
2812 pci_name(dev
), is_64
? "64" : "32", hwirq
, xive_num
,
2813 msg
->address_hi
, msg
->address_lo
, data
, pe
->pe_number
);
2818 static void pnv_pci_init_ioda_msis(struct pnv_phb
*phb
)
2821 const __be32
*prop
= of_get_property(phb
->hose
->dn
,
2822 "ibm,opal-msi-ranges", NULL
);
2825 prop
= of_get_property(phb
->hose
->dn
, "msi-ranges", NULL
);
2830 phb
->msi_base
= be32_to_cpup(prop
);
2831 count
= be32_to_cpup(prop
+ 1);
2832 if (msi_bitmap_alloc(&phb
->msi_bmp
, count
, phb
->hose
->dn
)) {
2833 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2834 phb
->hose
->global_number
);
2838 phb
->msi_setup
= pnv_pci_ioda_msi_setup
;
2839 phb
->msi32_support
= 1;
2840 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2841 count
, phb
->msi_base
);
2844 static void pnv_pci_init_ioda_msis(struct pnv_phb
*phb
) { }
2845 #endif /* CONFIG_PCI_MSI */
2847 #ifdef CONFIG_PCI_IOV
2848 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev
*pdev
)
2850 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
2851 struct pnv_phb
*phb
= hose
->private_data
;
2852 const resource_size_t gate
= phb
->ioda
.m64_segsize
>> 2;
2853 struct resource
*res
;
2855 resource_size_t size
, total_vf_bar_sz
;
2859 if (!pdev
->is_physfn
|| pdev
->is_added
)
2862 pdn
= pci_get_pdn(pdev
);
2863 pdn
->vfs_expanded
= 0;
2864 pdn
->m64_single_mode
= false;
2866 total_vfs
= pci_sriov_get_totalvfs(pdev
);
2867 mul
= phb
->ioda
.total_pe_num
;
2868 total_vf_bar_sz
= 0;
2870 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
2871 res
= &pdev
->resource
[i
+ PCI_IOV_RESOURCES
];
2872 if (!res
->flags
|| res
->parent
)
2874 if (!pnv_pci_is_m64(phb
, res
)) {
2875 dev_warn(&pdev
->dev
, "Don't support SR-IOV with"
2876 " non M64 VF BAR%d: %pR. \n",
2881 total_vf_bar_sz
+= pci_iov_resource_size(pdev
,
2882 i
+ PCI_IOV_RESOURCES
);
2885 * If bigger than quarter of M64 segment size, just round up
2888 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
2889 * with other devices, IOV BAR size is expanded to be
2890 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64
2891 * segment size , the expanded size would equal to half of the
2892 * whole M64 space size, which will exhaust the M64 Space and
2893 * limit the system flexibility. This is a design decision to
2894 * set the boundary to quarter of the M64 segment size.
2896 if (total_vf_bar_sz
> gate
) {
2897 mul
= roundup_pow_of_two(total_vfs
);
2898 dev_info(&pdev
->dev
,
2899 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2900 total_vf_bar_sz
, gate
, mul
);
2901 pdn
->m64_single_mode
= true;
2906 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
2907 res
= &pdev
->resource
[i
+ PCI_IOV_RESOURCES
];
2908 if (!res
->flags
|| res
->parent
)
2911 size
= pci_iov_resource_size(pdev
, i
+ PCI_IOV_RESOURCES
);
2913 * On PHB3, the minimum size alignment of M64 BAR in single
2916 if (pdn
->m64_single_mode
&& (size
< SZ_32M
))
2918 dev_dbg(&pdev
->dev
, " Fixing VF BAR%d: %pR to\n", i
, res
);
2919 res
->end
= res
->start
+ size
* mul
- 1;
2920 dev_dbg(&pdev
->dev
, " %pR\n", res
);
2921 dev_info(&pdev
->dev
, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2924 pdn
->vfs_expanded
= mul
;
2929 /* To save MMIO space, IOV BAR is truncated. */
2930 for (i
= 0; i
< PCI_SRIOV_NUM_BARS
; i
++) {
2931 res
= &pdev
->resource
[i
+ PCI_IOV_RESOURCES
];
2933 res
->end
= res
->start
- 1;
2936 #endif /* CONFIG_PCI_IOV */
2938 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe
*pe
,
2939 struct resource
*res
)
2941 struct pnv_phb
*phb
= pe
->phb
;
2942 struct pci_bus_region region
;
2946 if (!res
|| !res
->flags
|| res
->start
> res
->end
)
2949 if (res
->flags
& IORESOURCE_IO
) {
2950 region
.start
= res
->start
- phb
->ioda
.io_pci_base
;
2951 region
.end
= res
->end
- phb
->ioda
.io_pci_base
;
2952 index
= region
.start
/ phb
->ioda
.io_segsize
;
2954 while (index
< phb
->ioda
.total_pe_num
&&
2955 region
.start
<= region
.end
) {
2956 phb
->ioda
.io_segmap
[index
] = pe
->pe_number
;
2957 rc
= opal_pci_map_pe_mmio_window(phb
->opal_id
,
2958 pe
->pe_number
, OPAL_IO_WINDOW_TYPE
, 0, index
);
2959 if (rc
!= OPAL_SUCCESS
) {
2960 pr_err("%s: Error %lld mapping IO segment#%d to PE#%d\n",
2961 __func__
, rc
, index
, pe
->pe_number
);
2965 region
.start
+= phb
->ioda
.io_segsize
;
2968 } else if ((res
->flags
& IORESOURCE_MEM
) &&
2969 !pnv_pci_is_m64(phb
, res
)) {
2970 region
.start
= res
->start
-
2971 phb
->hose
->mem_offset
[0] -
2972 phb
->ioda
.m32_pci_base
;
2973 region
.end
= res
->end
-
2974 phb
->hose
->mem_offset
[0] -
2975 phb
->ioda
.m32_pci_base
;
2976 index
= region
.start
/ phb
->ioda
.m32_segsize
;
2978 while (index
< phb
->ioda
.total_pe_num
&&
2979 region
.start
<= region
.end
) {
2980 phb
->ioda
.m32_segmap
[index
] = pe
->pe_number
;
2981 rc
= opal_pci_map_pe_mmio_window(phb
->opal_id
,
2982 pe
->pe_number
, OPAL_M32_WINDOW_TYPE
, 0, index
);
2983 if (rc
!= OPAL_SUCCESS
) {
2984 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%d",
2985 __func__
, rc
, index
, pe
->pe_number
);
2989 region
.start
+= phb
->ioda
.m32_segsize
;
2996 * This function is supposed to be called on basis of PE from top
2997 * to bottom style. So the the I/O or MMIO segment assigned to
2998 * parent PE could be overrided by its child PEs if necessary.
3000 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe
*pe
)
3002 struct pci_dev
*pdev
;
3006 * NOTE: We only care PCI bus based PE for now. For PCI
3007 * device based PE, for example SRIOV sensitive VF should
3008 * be figured out later.
3010 BUG_ON(!(pe
->flags
& (PNV_IODA_PE_BUS
| PNV_IODA_PE_BUS_ALL
)));
3012 list_for_each_entry(pdev
, &pe
->pbus
->devices
, bus_list
) {
3013 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
3014 pnv_ioda_setup_pe_res(pe
, &pdev
->resource
[i
]);
3017 * If the PE contains all subordinate PCI buses, the
3018 * windows of the child bridges should be mapped to
3021 if (!(pe
->flags
& PNV_IODA_PE_BUS_ALL
) || !pci_is_bridge(pdev
))
3023 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++)
3024 pnv_ioda_setup_pe_res(pe
,
3025 &pdev
->resource
[PCI_BRIDGE_RESOURCES
+ i
]);
3029 static void pnv_pci_ioda_create_dbgfs(void)
3031 #ifdef CONFIG_DEBUG_FS
3032 struct pci_controller
*hose
, *tmp
;
3033 struct pnv_phb
*phb
;
3036 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
) {
3037 phb
= hose
->private_data
;
3039 /* Notify initialization of PHB done */
3040 phb
->initialized
= 1;
3042 sprintf(name
, "PCI%04x", hose
->global_number
);
3043 phb
->dbgfs
= debugfs_create_dir(name
, powerpc_debugfs_root
);
3045 pr_warning("%s: Error on creating debugfs on PHB#%x\n",
3046 __func__
, hose
->global_number
);
3048 #endif /* CONFIG_DEBUG_FS */
3051 static void pnv_pci_ioda_fixup(void)
3053 pnv_pci_ioda_setup_PEs();
3054 pnv_pci_ioda_setup_iommu_api();
3055 pnv_pci_ioda_create_dbgfs();
3059 eeh_addr_cache_build();
3064 * Returns the alignment for I/O or memory windows for P2P
3065 * bridges. That actually depends on how PEs are segmented.
3066 * For now, we return I/O or M32 segment size for PE sensitive
3067 * P2P bridges. Otherwise, the default values (4KiB for I/O,
3068 * 1MiB for memory) will be returned.
3070 * The current PCI bus might be put into one PE, which was
3071 * create against the parent PCI bridge. For that case, we
3072 * needn't enlarge the alignment so that we can save some
3075 static resource_size_t
pnv_pci_window_alignment(struct pci_bus
*bus
,
3078 struct pci_dev
*bridge
;
3079 struct pci_controller
*hose
= pci_bus_to_host(bus
);
3080 struct pnv_phb
*phb
= hose
->private_data
;
3081 int num_pci_bridges
= 0;
3085 if (pci_pcie_type(bridge
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
3087 if (num_pci_bridges
>= 2)
3091 bridge
= bridge
->bus
->self
;
3095 * We fall back to M32 if M64 isn't supported. We enforce the M64
3096 * alignment for any 64-bit resource, PCIe doesn't care and
3097 * bridges only do 64-bit prefetchable anyway.
3099 if (phb
->ioda
.m64_segsize
&& (type
& IORESOURCE_MEM_64
))
3100 return phb
->ioda
.m64_segsize
;
3101 if (type
& IORESOURCE_MEM
)
3102 return phb
->ioda
.m32_segsize
;
3104 return phb
->ioda
.io_segsize
;
3108 * We are updating root port or the upstream port of the
3109 * bridge behind the root port with PHB's windows in order
3110 * to accommodate the changes on required resources during
3111 * PCI (slot) hotplug, which is connected to either root
3112 * port or the downstream ports of PCIe switch behind the
3115 static void pnv_pci_fixup_bridge_resources(struct pci_bus
*bus
,
3118 struct pci_controller
*hose
= pci_bus_to_host(bus
);
3119 struct pnv_phb
*phb
= hose
->private_data
;
3120 struct pci_dev
*bridge
= bus
->self
;
3121 struct resource
*r
, *w
;
3122 bool msi_region
= false;
3125 /* Check if we need apply fixup to the bridge's windows */
3126 if (!pci_is_root_bus(bridge
->bus
) &&
3127 !pci_is_root_bus(bridge
->bus
->self
->bus
))
3130 /* Fixup the resources */
3131 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++) {
3132 r
= &bridge
->resource
[PCI_BRIDGE_RESOURCES
+ i
];
3133 if (!r
->flags
|| !r
->parent
)
3137 if (r
->flags
& type
& IORESOURCE_IO
)
3138 w
= &hose
->io_resource
;
3139 else if (pnv_pci_is_m64(phb
, r
) &&
3140 (type
& IORESOURCE_PREFETCH
) &&
3141 phb
->ioda
.m64_segsize
)
3142 w
= &hose
->mem_resources
[1];
3143 else if (r
->flags
& type
& IORESOURCE_MEM
) {
3144 w
= &hose
->mem_resources
[0];
3148 r
->start
= w
->start
;
3151 /* The 64KB 32-bits MSI region shouldn't be included in
3152 * the 32-bits bridge window. Otherwise, we can see strange
3153 * issues. One of them is EEH error observed on Garrison.
3155 * Exclude top 1MB region which is the minimal alignment of
3156 * 32-bits bridge window.
3165 static void pnv_pci_setup_bridge(struct pci_bus
*bus
, unsigned long type
)
3167 struct pci_controller
*hose
= pci_bus_to_host(bus
);
3168 struct pnv_phb
*phb
= hose
->private_data
;
3169 struct pci_dev
*bridge
= bus
->self
;
3170 struct pnv_ioda_pe
*pe
;
3171 bool all
= (pci_pcie_type(bridge
) == PCI_EXP_TYPE_PCI_BRIDGE
);
3173 /* Extend bridge's windows if necessary */
3174 pnv_pci_fixup_bridge_resources(bus
, type
);
3176 /* The PE for root bus should be realized before any one else */
3177 if (!phb
->ioda
.root_pe_populated
) {
3178 pe
= pnv_ioda_setup_bus_PE(phb
->hose
->bus
, false);
3180 phb
->ioda
.root_pe_idx
= pe
->pe_number
;
3181 phb
->ioda
.root_pe_populated
= true;
3185 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3186 if (list_empty(&bus
->devices
))
3189 /* Reserve PEs according to used M64 resources */
3190 if (phb
->reserve_m64_pe
)
3191 phb
->reserve_m64_pe(bus
, NULL
, all
);
3194 * Assign PE. We might run here because of partial hotplug.
3195 * For the case, we just pick up the existing PE and should
3196 * not allocate resources again.
3198 pe
= pnv_ioda_setup_bus_PE(bus
, all
);
3202 pnv_ioda_setup_pe_seg(pe
);
3203 switch (phb
->type
) {
3205 pnv_pci_ioda1_setup_dma_pe(phb
, pe
);
3208 pnv_pci_ioda2_setup_dma_pe(phb
, pe
);
3211 pr_warn("%s: No DMA for PHB#%d (type %d)\n",
3212 __func__
, phb
->hose
->global_number
, phb
->type
);
3216 #ifdef CONFIG_PCI_IOV
3217 static resource_size_t
pnv_pci_iov_resource_alignment(struct pci_dev
*pdev
,
3220 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
3221 struct pnv_phb
*phb
= hose
->private_data
;
3222 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
3223 resource_size_t align
;
3226 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3227 * SR-IOV. While from hardware perspective, the range mapped by M64
3228 * BAR should be size aligned.
3230 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3231 * powernv-specific hardware restriction is gone. But if just use the
3232 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3233 * in one segment of M64 #15, which introduces the PE conflict between
3234 * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3237 * This function returns the total IOV BAR size if M64 BAR is in
3238 * Shared PE mode or just VF BAR size if not.
3239 * If the M64 BAR is in Single PE mode, return the VF BAR size or
3240 * M64 segment size if IOV BAR size is less.
3242 align
= pci_iov_resource_size(pdev
, resno
);
3243 if (!pdn
->vfs_expanded
)
3245 if (pdn
->m64_single_mode
)
3246 return max(align
, (resource_size_t
)phb
->ioda
.m64_segsize
);
3248 return pdn
->vfs_expanded
* align
;
3250 #endif /* CONFIG_PCI_IOV */
3252 /* Prevent enabling devices for which we couldn't properly
3255 bool pnv_pci_enable_device_hook(struct pci_dev
*dev
)
3257 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
3258 struct pnv_phb
*phb
= hose
->private_data
;
3261 /* The function is probably called while the PEs have
3262 * not be created yet. For example, resource reassignment
3263 * during PCI probe period. We just skip the check if
3266 if (!phb
->initialized
)
3269 pdn
= pci_get_pdn(dev
);
3270 if (!pdn
|| pdn
->pe_number
== IODA_INVALID_PE
)
3276 static long pnv_pci_ioda1_unset_window(struct iommu_table_group
*table_group
,
3279 struct pnv_ioda_pe
*pe
= container_of(table_group
,
3280 struct pnv_ioda_pe
, table_group
);
3281 struct pnv_phb
*phb
= pe
->phb
;
3285 pe_info(pe
, "Removing DMA window #%d\n", num
);
3286 for (idx
= 0; idx
< phb
->ioda
.dma32_count
; idx
++) {
3287 if (phb
->ioda
.dma32_segmap
[idx
] != pe
->pe_number
)
3290 rc
= opal_pci_map_pe_dma_window(phb
->opal_id
, pe
->pe_number
,
3291 idx
, 0, 0ul, 0ul, 0ul);
3292 if (rc
!= OPAL_SUCCESS
) {
3293 pe_warn(pe
, "Failure %ld unmapping DMA32 segment#%d\n",
3298 phb
->ioda
.dma32_segmap
[idx
] = IODA_INVALID_PE
;
3301 pnv_pci_unlink_table_and_group(table_group
->tables
[num
], table_group
);
3302 return OPAL_SUCCESS
;
3305 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe
*pe
)
3307 unsigned int weight
= pnv_pci_ioda_pe_dma_weight(pe
);
3308 struct iommu_table
*tbl
= pe
->table_group
.tables
[0];
3314 rc
= pnv_pci_ioda1_unset_window(&pe
->table_group
, 0);
3315 if (rc
!= OPAL_SUCCESS
)
3318 pnv_pci_p7ioc_tce_invalidate(tbl
, tbl
->it_offset
, tbl
->it_size
, false);
3319 if (pe
->table_group
.group
) {
3320 iommu_group_put(pe
->table_group
.group
);
3321 WARN_ON(pe
->table_group
.group
);
3324 free_pages(tbl
->it_base
, get_order(tbl
->it_size
<< 3));
3325 iommu_free_table(tbl
, "pnv");
3328 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe
*pe
)
3330 struct iommu_table
*tbl
= pe
->table_group
.tables
[0];
3331 unsigned int weight
= pnv_pci_ioda_pe_dma_weight(pe
);
3332 #ifdef CONFIG_IOMMU_API
3339 #ifdef CONFIG_IOMMU_API
3340 rc
= pnv_pci_ioda2_unset_window(&pe
->table_group
, 0);
3342 pe_warn(pe
, "OPAL error %ld release DMA window\n", rc
);
3345 pnv_pci_ioda2_set_bypass(pe
, false);
3346 if (pe
->table_group
.group
) {
3347 iommu_group_put(pe
->table_group
.group
);
3348 WARN_ON(pe
->table_group
.group
);
3351 pnv_pci_ioda2_table_free_pages(tbl
);
3352 iommu_free_table(tbl
, "pnv");
3355 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe
*pe
,
3359 struct pnv_phb
*phb
= pe
->phb
;
3363 for (idx
= 0; idx
< phb
->ioda
.total_pe_num
; idx
++) {
3364 if (map
[idx
] != pe
->pe_number
)
3367 if (win
== OPAL_M64_WINDOW_TYPE
)
3368 rc
= opal_pci_map_pe_mmio_window(phb
->opal_id
,
3369 phb
->ioda
.reserved_pe_idx
, win
,
3370 idx
/ PNV_IODA1_M64_SEGS
,
3371 idx
% PNV_IODA1_M64_SEGS
);
3373 rc
= opal_pci_map_pe_mmio_window(phb
->opal_id
,
3374 phb
->ioda
.reserved_pe_idx
, win
, 0, idx
);
3376 if (rc
!= OPAL_SUCCESS
)
3377 pe_warn(pe
, "Error %ld unmapping (%d) segment#%d\n",
3380 map
[idx
] = IODA_INVALID_PE
;
3384 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe
*pe
)
3386 struct pnv_phb
*phb
= pe
->phb
;
3388 if (phb
->type
== PNV_PHB_IODA1
) {
3389 pnv_ioda_free_pe_seg(pe
, OPAL_IO_WINDOW_TYPE
,
3390 phb
->ioda
.io_segmap
);
3391 pnv_ioda_free_pe_seg(pe
, OPAL_M32_WINDOW_TYPE
,
3392 phb
->ioda
.m32_segmap
);
3393 pnv_ioda_free_pe_seg(pe
, OPAL_M64_WINDOW_TYPE
,
3394 phb
->ioda
.m64_segmap
);
3395 } else if (phb
->type
== PNV_PHB_IODA2
) {
3396 pnv_ioda_free_pe_seg(pe
, OPAL_M32_WINDOW_TYPE
,
3397 phb
->ioda
.m32_segmap
);
3401 static void pnv_ioda_release_pe(struct pnv_ioda_pe
*pe
)
3403 struct pnv_phb
*phb
= pe
->phb
;
3404 struct pnv_ioda_pe
*slave
, *tmp
;
3406 list_del(&pe
->list
);
3407 switch (phb
->type
) {
3409 pnv_pci_ioda1_release_pe_dma(pe
);
3412 pnv_pci_ioda2_release_pe_dma(pe
);
3418 pnv_ioda_release_pe_seg(pe
);
3419 pnv_ioda_deconfigure_pe(pe
->phb
, pe
);
3421 /* Release slave PEs in the compound PE */
3422 if (pe
->flags
& PNV_IODA_PE_MASTER
) {
3423 list_for_each_entry_safe(slave
, tmp
, &pe
->slaves
, list
) {
3424 list_del(&slave
->list
);
3425 pnv_ioda_free_pe(slave
);
3429 pnv_ioda_free_pe(pe
);
3432 static void pnv_pci_release_device(struct pci_dev
*pdev
)
3434 struct pci_controller
*hose
= pci_bus_to_host(pdev
->bus
);
3435 struct pnv_phb
*phb
= hose
->private_data
;
3436 struct pci_dn
*pdn
= pci_get_pdn(pdev
);
3437 struct pnv_ioda_pe
*pe
;
3439 if (pdev
->is_virtfn
)
3442 if (!pdn
|| pdn
->pe_number
== IODA_INVALID_PE
)
3445 pe
= &phb
->ioda
.pe_array
[pdn
->pe_number
];
3446 WARN_ON(--pe
->device_count
< 0);
3447 if (pe
->device_count
== 0)
3448 pnv_ioda_release_pe(pe
);
3451 static void pnv_pci_ioda_shutdown(struct pci_controller
*hose
)
3453 struct pnv_phb
*phb
= hose
->private_data
;
3455 opal_pci_reset(phb
->opal_id
, OPAL_RESET_PCI_IODA_TABLE
,
3459 static const struct pci_controller_ops pnv_pci_ioda_controller_ops
= {
3460 .dma_dev_setup
= pnv_pci_dma_dev_setup
,
3461 .dma_bus_setup
= pnv_pci_dma_bus_setup
,
3462 #ifdef CONFIG_PCI_MSI
3463 .setup_msi_irqs
= pnv_setup_msi_irqs
,
3464 .teardown_msi_irqs
= pnv_teardown_msi_irqs
,
3466 .enable_device_hook
= pnv_pci_enable_device_hook
,
3467 .release_device
= pnv_pci_release_device
,
3468 .window_alignment
= pnv_pci_window_alignment
,
3469 .setup_bridge
= pnv_pci_setup_bridge
,
3470 .reset_secondary_bus
= pnv_pci_reset_secondary_bus
,
3471 .dma_set_mask
= pnv_pci_ioda_dma_set_mask
,
3472 .dma_get_required_mask
= pnv_pci_ioda_dma_get_required_mask
,
3473 .shutdown
= pnv_pci_ioda_shutdown
,
3476 static int pnv_npu_dma_set_mask(struct pci_dev
*npdev
, u64 dma_mask
)
3478 dev_err_once(&npdev
->dev
,
3479 "%s operation unsupported for NVLink devices\n",
3484 static const struct pci_controller_ops pnv_npu_ioda_controller_ops
= {
3485 .dma_dev_setup
= pnv_pci_dma_dev_setup
,
3486 #ifdef CONFIG_PCI_MSI
3487 .setup_msi_irqs
= pnv_setup_msi_irqs
,
3488 .teardown_msi_irqs
= pnv_teardown_msi_irqs
,
3490 .enable_device_hook
= pnv_pci_enable_device_hook
,
3491 .window_alignment
= pnv_pci_window_alignment
,
3492 .reset_secondary_bus
= pnv_pci_reset_secondary_bus
,
3493 .dma_set_mask
= pnv_npu_dma_set_mask
,
3494 .shutdown
= pnv_pci_ioda_shutdown
,
3497 #ifdef CONFIG_CXL_BASE
3498 const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops
= {
3499 .dma_dev_setup
= pnv_pci_dma_dev_setup
,
3500 .dma_bus_setup
= pnv_pci_dma_bus_setup
,
3501 #ifdef CONFIG_PCI_MSI
3502 .setup_msi_irqs
= pnv_cxl_cx4_setup_msi_irqs
,
3503 .teardown_msi_irqs
= pnv_cxl_cx4_teardown_msi_irqs
,
3505 .enable_device_hook
= pnv_cxl_enable_device_hook
,
3506 .disable_device
= pnv_cxl_disable_device
,
3507 .release_device
= pnv_pci_release_device
,
3508 .window_alignment
= pnv_pci_window_alignment
,
3509 .setup_bridge
= pnv_pci_setup_bridge
,
3510 .reset_secondary_bus
= pnv_pci_reset_secondary_bus
,
3511 .dma_set_mask
= pnv_pci_ioda_dma_set_mask
,
3512 .dma_get_required_mask
= pnv_pci_ioda_dma_get_required_mask
,
3513 .shutdown
= pnv_pci_ioda_shutdown
,
3517 static void __init
pnv_pci_init_ioda_phb(struct device_node
*np
,
3518 u64 hub_id
, int ioda_type
)
3520 struct pci_controller
*hose
;
3521 struct pnv_phb
*phb
;
3522 unsigned long size
, m64map_off
, m32map_off
, pemap_off
;
3523 unsigned long iomap_off
= 0, dma32map_off
= 0;
3525 const __be64
*prop64
;
3526 const __be32
*prop32
;
3533 if (!of_device_is_available(np
))
3536 pr_info("Initializing %s PHB (%s)\n",
3537 pnv_phb_names
[ioda_type
], of_node_full_name(np
));
3539 prop64
= of_get_property(np
, "ibm,opal-phbid", NULL
);
3541 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3544 phb_id
= be64_to_cpup(prop64
);
3545 pr_debug(" PHB-ID : 0x%016llx\n", phb_id
);
3547 phb
= memblock_virt_alloc(sizeof(struct pnv_phb
), 0);
3549 /* Allocate PCI controller */
3550 phb
->hose
= hose
= pcibios_alloc_controller(np
);
3552 pr_err(" Can't allocate PCI controller for %s\n",
3554 memblock_free(__pa(phb
), sizeof(struct pnv_phb
));
3558 spin_lock_init(&phb
->lock
);
3559 prop32
= of_get_property(np
, "bus-range", &len
);
3560 if (prop32
&& len
== 8) {
3561 hose
->first_busno
= be32_to_cpu(prop32
[0]);
3562 hose
->last_busno
= be32_to_cpu(prop32
[1]);
3564 pr_warn(" Broken <bus-range> on %s\n", np
->full_name
);
3565 hose
->first_busno
= 0;
3566 hose
->last_busno
= 0xff;
3568 hose
->private_data
= phb
;
3569 phb
->hub_id
= hub_id
;
3570 phb
->opal_id
= phb_id
;
3571 phb
->type
= ioda_type
;
3572 mutex_init(&phb
->ioda
.pe_alloc_mutex
);
3574 /* Detect specific models for error handling */
3575 if (of_device_is_compatible(np
, "ibm,p7ioc-pciex"))
3576 phb
->model
= PNV_PHB_MODEL_P7IOC
;
3577 else if (of_device_is_compatible(np
, "ibm,power8-pciex"))
3578 phb
->model
= PNV_PHB_MODEL_PHB3
;
3579 else if (of_device_is_compatible(np
, "ibm,power8-npu-pciex"))
3580 phb
->model
= PNV_PHB_MODEL_NPU
;
3582 phb
->model
= PNV_PHB_MODEL_UNKNOWN
;
3584 /* Parse 32-bit and IO ranges (if any) */
3585 pci_process_bridge_OF_ranges(hose
, np
, !hose
->global_number
);
3588 if (!of_address_to_resource(np
, 0, &r
)) {
3589 phb
->regs_phys
= r
.start
;
3590 phb
->regs
= ioremap(r
.start
, resource_size(&r
));
3591 if (phb
->regs
== NULL
)
3592 pr_err(" Failed to map registers !\n");
3595 /* Initialize more IODA stuff */
3596 phb
->ioda
.total_pe_num
= 1;
3597 prop32
= of_get_property(np
, "ibm,opal-num-pes", NULL
);
3599 phb
->ioda
.total_pe_num
= be32_to_cpup(prop32
);
3600 prop32
= of_get_property(np
, "ibm,opal-reserved-pe", NULL
);
3602 phb
->ioda
.reserved_pe_idx
= be32_to_cpup(prop32
);
3604 /* Invalidate RID to PE# mapping */
3605 for (segno
= 0; segno
< ARRAY_SIZE(phb
->ioda
.pe_rmap
); segno
++)
3606 phb
->ioda
.pe_rmap
[segno
] = IODA_INVALID_PE
;
3608 /* Parse 64-bit MMIO range */
3609 pnv_ioda_parse_m64_window(phb
);
3611 phb
->ioda
.m32_size
= resource_size(&hose
->mem_resources
[0]);
3612 /* FW Has already off top 64k of M32 space (MSI space) */
3613 phb
->ioda
.m32_size
+= 0x10000;
3615 phb
->ioda
.m32_segsize
= phb
->ioda
.m32_size
/ phb
->ioda
.total_pe_num
;
3616 phb
->ioda
.m32_pci_base
= hose
->mem_resources
[0].start
- hose
->mem_offset
[0];
3617 phb
->ioda
.io_size
= hose
->pci_io_size
;
3618 phb
->ioda
.io_segsize
= phb
->ioda
.io_size
/ phb
->ioda
.total_pe_num
;
3619 phb
->ioda
.io_pci_base
= 0; /* XXX calculate this ? */
3621 /* Calculate how many 32-bit TCE segments we have */
3622 phb
->ioda
.dma32_count
= phb
->ioda
.m32_pci_base
/
3623 PNV_IODA1_DMA32_SEGSIZE
;
3625 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3626 size
= _ALIGN_UP(max_t(unsigned, phb
->ioda
.total_pe_num
, 8) / 8,
3627 sizeof(unsigned long));
3629 size
+= phb
->ioda
.total_pe_num
* sizeof(phb
->ioda
.m64_segmap
[0]);
3631 size
+= phb
->ioda
.total_pe_num
* sizeof(phb
->ioda
.m32_segmap
[0]);
3632 if (phb
->type
== PNV_PHB_IODA1
) {
3634 size
+= phb
->ioda
.total_pe_num
* sizeof(phb
->ioda
.io_segmap
[0]);
3635 dma32map_off
= size
;
3636 size
+= phb
->ioda
.dma32_count
*
3637 sizeof(phb
->ioda
.dma32_segmap
[0]);
3640 size
+= phb
->ioda
.total_pe_num
* sizeof(struct pnv_ioda_pe
);
3641 aux
= memblock_virt_alloc(size
, 0);
3642 phb
->ioda
.pe_alloc
= aux
;
3643 phb
->ioda
.m64_segmap
= aux
+ m64map_off
;
3644 phb
->ioda
.m32_segmap
= aux
+ m32map_off
;
3645 for (segno
= 0; segno
< phb
->ioda
.total_pe_num
; segno
++) {
3646 phb
->ioda
.m64_segmap
[segno
] = IODA_INVALID_PE
;
3647 phb
->ioda
.m32_segmap
[segno
] = IODA_INVALID_PE
;
3649 if (phb
->type
== PNV_PHB_IODA1
) {
3650 phb
->ioda
.io_segmap
= aux
+ iomap_off
;
3651 for (segno
= 0; segno
< phb
->ioda
.total_pe_num
; segno
++)
3652 phb
->ioda
.io_segmap
[segno
] = IODA_INVALID_PE
;
3654 phb
->ioda
.dma32_segmap
= aux
+ dma32map_off
;
3655 for (segno
= 0; segno
< phb
->ioda
.dma32_count
; segno
++)
3656 phb
->ioda
.dma32_segmap
[segno
] = IODA_INVALID_PE
;
3658 phb
->ioda
.pe_array
= aux
+ pemap_off
;
3661 * Choose PE number for root bus, which shouldn't have
3662 * M64 resources consumed by its child devices. To pick
3663 * the PE number adjacent to the reserved one if possible.
3665 pnv_ioda_reserve_pe(phb
, phb
->ioda
.reserved_pe_idx
);
3666 if (phb
->ioda
.reserved_pe_idx
== 0) {
3667 phb
->ioda
.root_pe_idx
= 1;
3668 pnv_ioda_reserve_pe(phb
, phb
->ioda
.root_pe_idx
);
3669 } else if (phb
->ioda
.reserved_pe_idx
== (phb
->ioda
.total_pe_num
- 1)) {
3670 phb
->ioda
.root_pe_idx
= phb
->ioda
.reserved_pe_idx
- 1;
3671 pnv_ioda_reserve_pe(phb
, phb
->ioda
.root_pe_idx
);
3673 phb
->ioda
.root_pe_idx
= IODA_INVALID_PE
;
3676 INIT_LIST_HEAD(&phb
->ioda
.pe_list
);
3677 mutex_init(&phb
->ioda
.pe_list_mutex
);
3679 /* Calculate how many 32-bit TCE segments we have */
3680 phb
->ioda
.dma32_count
= phb
->ioda
.m32_pci_base
/
3681 PNV_IODA1_DMA32_SEGSIZE
;
3683 #if 0 /* We should really do that ... */
3684 rc
= opal_pci_set_phb_mem_window(opal
->phb_id
,
3687 starting_real_address
,
3688 starting_pci_address
,
3692 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3693 phb
->ioda
.total_pe_num
, phb
->ioda
.reserved_pe_idx
,
3694 phb
->ioda
.m32_size
, phb
->ioda
.m32_segsize
);
3695 if (phb
->ioda
.m64_size
)
3696 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3697 phb
->ioda
.m64_size
, phb
->ioda
.m64_segsize
);
3698 if (phb
->ioda
.io_size
)
3699 pr_info(" IO: 0x%x [segment=0x%x]\n",
3700 phb
->ioda
.io_size
, phb
->ioda
.io_segsize
);
3703 phb
->hose
->ops
= &pnv_pci_ops
;
3704 phb
->get_pe_state
= pnv_ioda_get_pe_state
;
3705 phb
->freeze_pe
= pnv_ioda_freeze_pe
;
3706 phb
->unfreeze_pe
= pnv_ioda_unfreeze_pe
;
3708 /* Setup MSI support */
3709 pnv_pci_init_ioda_msis(phb
);
3712 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3713 * to let the PCI core do resource assignment. It's supposed
3714 * that the PCI core will do correct I/O and MMIO alignment
3715 * for the P2P bridge bars so that each PCI bus (excluding
3716 * the child P2P bridges) can form individual PE.
3718 ppc_md
.pcibios_fixup
= pnv_pci_ioda_fixup
;
3720 if (phb
->type
== PNV_PHB_NPU
) {
3721 hose
->controller_ops
= pnv_npu_ioda_controller_ops
;
3723 phb
->dma_dev_setup
= pnv_pci_ioda_dma_dev_setup
;
3724 hose
->controller_ops
= pnv_pci_ioda_controller_ops
;
3727 #ifdef CONFIG_PCI_IOV
3728 ppc_md
.pcibios_fixup_sriov
= pnv_pci_ioda_fixup_iov_resources
;
3729 ppc_md
.pcibios_iov_resource_alignment
= pnv_pci_iov_resource_alignment
;
3732 pci_add_flags(PCI_REASSIGN_ALL_RSRC
);
3734 /* Reset IODA tables to a clean state */
3735 rc
= opal_pci_reset(phb_id
, OPAL_RESET_PCI_IODA_TABLE
, OPAL_ASSERT_RESET
);
3737 pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc
);
3739 /* If we're running in kdump kerenl, the previous kerenl never
3740 * shutdown PCI devices correctly. We already got IODA table
3741 * cleaned out. So we have to issue PHB reset to stop all PCI
3742 * transactions from previous kerenl.
3744 if (is_kdump_kernel()) {
3745 pr_info(" Issue PHB reset ...\n");
3746 pnv_eeh_phb_reset(hose
, EEH_RESET_FUNDAMENTAL
);
3747 pnv_eeh_phb_reset(hose
, EEH_RESET_DEACTIVATE
);
3750 /* Remove M64 resource if we can't configure it successfully */
3751 if (!phb
->init_m64
|| phb
->init_m64(phb
))
3752 hose
->mem_resources
[1].flags
= 0;
3755 void __init
pnv_pci_init_ioda2_phb(struct device_node
*np
)
3757 pnv_pci_init_ioda_phb(np
, 0, PNV_PHB_IODA2
);
3760 void __init
pnv_pci_init_npu_phb(struct device_node
*np
)
3762 pnv_pci_init_ioda_phb(np
, 0, PNV_PHB_NPU
);
3765 void __init
pnv_pci_init_ioda_hub(struct device_node
*np
)
3767 struct device_node
*phbn
;
3768 const __be64
*prop64
;
3771 pr_info("Probing IODA IO-Hub %s\n", np
->full_name
);
3773 prop64
= of_get_property(np
, "ibm,opal-hubid", NULL
);
3775 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3778 hub_id
= be64_to_cpup(prop64
);
3779 pr_devel(" HUB-ID : 0x%016llx\n", hub_id
);
3781 /* Count child PHBs */
3782 for_each_child_of_node(np
, phbn
) {
3783 /* Look for IODA1 PHBs */
3784 if (of_device_is_compatible(phbn
, "ibm,ioda-phb"))
3785 pnv_pci_init_ioda_phb(phbn
, hub_id
, PNV_PHB_IODA1
);