[PATCH] powerpc: Kill _machine and hard-coded platform numbers
[deliverable/linux.git] / arch / powerpc / platforms / pseries / eeh.c
1 /*
2 * eeh.c
3 * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/list.h>
23 #include <linux/pci.h>
24 #include <linux/proc_fs.h>
25 #include <linux/rbtree.h>
26 #include <linux/seq_file.h>
27 #include <linux/spinlock.h>
28 #include <asm/atomic.h>
29 #include <asm/eeh.h>
30 #include <asm/eeh_event.h>
31 #include <asm/io.h>
32 #include <asm/machdep.h>
33 #include <asm/ppc-pci.h>
34 #include <asm/rtas.h>
35
36 #undef DEBUG
37
38 /** Overview:
39 * EEH, or "Extended Error Handling" is a PCI bridge technology for
40 * dealing with PCI bus errors that can't be dealt with within the
41 * usual PCI framework, except by check-stopping the CPU. Systems
42 * that are designed for high-availability/reliability cannot afford
43 * to crash due to a "mere" PCI error, thus the need for EEH.
44 * An EEH-capable bridge operates by converting a detected error
45 * into a "slot freeze", taking the PCI adapter off-line, making
46 * the slot behave, from the OS'es point of view, as if the slot
47 * were "empty": all reads return 0xff's and all writes are silently
48 * ignored. EEH slot isolation events can be triggered by parity
49 * errors on the address or data busses (e.g. during posted writes),
50 * which in turn might be caused by low voltage on the bus, dust,
51 * vibration, humidity, radioactivity or plain-old failed hardware.
52 *
53 * Note, however, that one of the leading causes of EEH slot
54 * freeze events are buggy device drivers, buggy device microcode,
55 * or buggy device hardware. This is because any attempt by the
56 * device to bus-master data to a memory address that is not
57 * assigned to the device will trigger a slot freeze. (The idea
58 * is to prevent devices-gone-wild from corrupting system memory).
59 * Buggy hardware/drivers will have a miserable time co-existing
60 * with EEH.
61 *
62 * Ideally, a PCI device driver, when suspecting that an isolation
63 * event has occured (e.g. by reading 0xff's), will then ask EEH
64 * whether this is the case, and then take appropriate steps to
65 * reset the PCI slot, the PCI device, and then resume operations.
66 * However, until that day, the checking is done here, with the
67 * eeh_check_failure() routine embedded in the MMIO macros. If
68 * the slot is found to be isolated, an "EEH Event" is synthesized
69 * and sent out for processing.
70 */
71
72 /* If a device driver keeps reading an MMIO register in an interrupt
73 * handler after a slot isolation event has occurred, we assume it
74 * is broken and panic. This sets the threshold for how many read
75 * attempts we allow before panicking.
76 */
77 #define EEH_MAX_FAILS 100000
78
79 /* RTAS tokens */
80 static int ibm_set_eeh_option;
81 static int ibm_set_slot_reset;
82 static int ibm_read_slot_reset_state;
83 static int ibm_read_slot_reset_state2;
84 static int ibm_slot_error_detail;
85 static int ibm_get_config_addr_info;
86 static int ibm_configure_bridge;
87
88 int eeh_subsystem_enabled;
89 EXPORT_SYMBOL(eeh_subsystem_enabled);
90
91 /* Lock to avoid races due to multiple reports of an error */
92 static DEFINE_SPINLOCK(confirm_error_lock);
93
94 /* Buffer for reporting slot-error-detail rtas calls */
95 static unsigned char slot_errbuf[RTAS_ERROR_LOG_MAX];
96 static DEFINE_SPINLOCK(slot_errbuf_lock);
97 static int eeh_error_buf_size;
98
99 /* System monitoring statistics */
100 static unsigned long no_device;
101 static unsigned long no_dn;
102 static unsigned long no_cfg_addr;
103 static unsigned long ignored_check;
104 static unsigned long total_mmio_ffs;
105 static unsigned long false_positives;
106 static unsigned long ignored_failures;
107 static unsigned long slot_resets;
108
109 #define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE)
110
111 /* --------------------------------------------------------------- */
112 /* Below lies the EEH event infrastructure */
113
114 void eeh_slot_error_detail (struct pci_dn *pdn, int severity)
115 {
116 int config_addr;
117 unsigned long flags;
118 int rc;
119
120 /* Log the error with the rtas logger */
121 spin_lock_irqsave(&slot_errbuf_lock, flags);
122 memset(slot_errbuf, 0, eeh_error_buf_size);
123
124 /* Use PE configuration address, if present */
125 config_addr = pdn->eeh_config_addr;
126 if (pdn->eeh_pe_config_addr)
127 config_addr = pdn->eeh_pe_config_addr;
128
129 rc = rtas_call(ibm_slot_error_detail,
130 8, 1, NULL, config_addr,
131 BUID_HI(pdn->phb->buid),
132 BUID_LO(pdn->phb->buid), NULL, 0,
133 virt_to_phys(slot_errbuf),
134 eeh_error_buf_size,
135 severity);
136
137 if (rc == 0)
138 log_error(slot_errbuf, ERR_TYPE_RTAS_LOG, 0);
139 spin_unlock_irqrestore(&slot_errbuf_lock, flags);
140 }
141
142 /**
143 * read_slot_reset_state - Read the reset state of a device node's slot
144 * @dn: device node to read
145 * @rets: array to return results in
146 */
147 static int read_slot_reset_state(struct pci_dn *pdn, int rets[])
148 {
149 int token, outputs;
150 int config_addr;
151
152 if (ibm_read_slot_reset_state2 != RTAS_UNKNOWN_SERVICE) {
153 token = ibm_read_slot_reset_state2;
154 outputs = 4;
155 } else {
156 token = ibm_read_slot_reset_state;
157 rets[2] = 0; /* fake PE Unavailable info */
158 outputs = 3;
159 }
160
161 /* Use PE configuration address, if present */
162 config_addr = pdn->eeh_config_addr;
163 if (pdn->eeh_pe_config_addr)
164 config_addr = pdn->eeh_pe_config_addr;
165
166 return rtas_call(token, 3, outputs, rets, config_addr,
167 BUID_HI(pdn->phb->buid), BUID_LO(pdn->phb->buid));
168 }
169
170 /**
171 * eeh_token_to_phys - convert EEH address token to phys address
172 * @token i/o token, should be address in the form 0xA....
173 */
174 static inline unsigned long eeh_token_to_phys(unsigned long token)
175 {
176 pte_t *ptep;
177 unsigned long pa;
178
179 ptep = find_linux_pte(init_mm.pgd, token);
180 if (!ptep)
181 return token;
182 pa = pte_pfn(*ptep) << PAGE_SHIFT;
183
184 return pa | (token & (PAGE_SIZE-1));
185 }
186
187 /**
188 * Return the "partitionable endpoint" (pe) under which this device lies
189 */
190 struct device_node * find_device_pe(struct device_node *dn)
191 {
192 while ((dn->parent) && PCI_DN(dn->parent) &&
193 (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) {
194 dn = dn->parent;
195 }
196 return dn;
197 }
198
199 /** Mark all devices that are peers of this device as failed.
200 * Mark the device driver too, so that it can see the failure
201 * immediately; this is critical, since some drivers poll
202 * status registers in interrupts ... If a driver is polling,
203 * and the slot is frozen, then the driver can deadlock in
204 * an interrupt context, which is bad.
205 */
206
207 static void __eeh_mark_slot (struct device_node *dn, int mode_flag)
208 {
209 while (dn) {
210 if (PCI_DN(dn)) {
211 /* Mark the pci device driver too */
212 struct pci_dev *dev = PCI_DN(dn)->pcidev;
213
214 PCI_DN(dn)->eeh_mode |= mode_flag;
215
216 if (dev && dev->driver)
217 dev->error_state = pci_channel_io_frozen;
218
219 if (dn->child)
220 __eeh_mark_slot (dn->child, mode_flag);
221 }
222 dn = dn->sibling;
223 }
224 }
225
226 void eeh_mark_slot (struct device_node *dn, int mode_flag)
227 {
228 dn = find_device_pe (dn);
229
230 /* Back up one, since config addrs might be shared */
231 if (PCI_DN(dn) && PCI_DN(dn)->eeh_pe_config_addr)
232 dn = dn->parent;
233
234 PCI_DN(dn)->eeh_mode |= mode_flag;
235 __eeh_mark_slot (dn->child, mode_flag);
236 }
237
238 static void __eeh_clear_slot (struct device_node *dn, int mode_flag)
239 {
240 while (dn) {
241 if (PCI_DN(dn)) {
242 PCI_DN(dn)->eeh_mode &= ~mode_flag;
243 PCI_DN(dn)->eeh_check_count = 0;
244 if (dn->child)
245 __eeh_clear_slot (dn->child, mode_flag);
246 }
247 dn = dn->sibling;
248 }
249 }
250
251 void eeh_clear_slot (struct device_node *dn, int mode_flag)
252 {
253 unsigned long flags;
254 spin_lock_irqsave(&confirm_error_lock, flags);
255
256 dn = find_device_pe (dn);
257
258 /* Back up one, since config addrs might be shared */
259 if (PCI_DN(dn) && PCI_DN(dn)->eeh_pe_config_addr)
260 dn = dn->parent;
261
262 PCI_DN(dn)->eeh_mode &= ~mode_flag;
263 PCI_DN(dn)->eeh_check_count = 0;
264 __eeh_clear_slot (dn->child, mode_flag);
265 spin_unlock_irqrestore(&confirm_error_lock, flags);
266 }
267
268 /**
269 * eeh_dn_check_failure - check if all 1's data is due to EEH slot freeze
270 * @dn device node
271 * @dev pci device, if known
272 *
273 * Check for an EEH failure for the given device node. Call this
274 * routine if the result of a read was all 0xff's and you want to
275 * find out if this is due to an EEH slot freeze. This routine
276 * will query firmware for the EEH status.
277 *
278 * Returns 0 if there has not been an EEH error; otherwise returns
279 * a non-zero value and queues up a slot isolation event notification.
280 *
281 * It is safe to call this routine in an interrupt context.
282 */
283 int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
284 {
285 int ret;
286 int rets[3];
287 unsigned long flags;
288 struct pci_dn *pdn;
289 enum pci_channel_state state;
290 int rc = 0;
291
292 total_mmio_ffs++;
293
294 if (!eeh_subsystem_enabled)
295 return 0;
296
297 if (!dn) {
298 no_dn++;
299 return 0;
300 }
301 pdn = PCI_DN(dn);
302
303 /* Access to IO BARs might get this far and still not want checking. */
304 if (!(pdn->eeh_mode & EEH_MODE_SUPPORTED) ||
305 pdn->eeh_mode & EEH_MODE_NOCHECK) {
306 ignored_check++;
307 #ifdef DEBUG
308 printk ("EEH:ignored check (%x) for %s %s\n",
309 pdn->eeh_mode, pci_name (dev), dn->full_name);
310 #endif
311 return 0;
312 }
313
314 if (!pdn->eeh_config_addr && !pdn->eeh_pe_config_addr) {
315 no_cfg_addr++;
316 return 0;
317 }
318
319 /* If we already have a pending isolation event for this
320 * slot, we know it's bad already, we don't need to check.
321 * Do this checking under a lock; as multiple PCI devices
322 * in one slot might report errors simultaneously, and we
323 * only want one error recovery routine running.
324 */
325 spin_lock_irqsave(&confirm_error_lock, flags);
326 rc = 1;
327 if (pdn->eeh_mode & EEH_MODE_ISOLATED) {
328 pdn->eeh_check_count ++;
329 if (pdn->eeh_check_count >= EEH_MAX_FAILS) {
330 printk (KERN_ERR "EEH: Device driver ignored %d bad reads, panicing\n",
331 pdn->eeh_check_count);
332 dump_stack();
333
334 /* re-read the slot reset state */
335 if (read_slot_reset_state(pdn, rets) != 0)
336 rets[0] = -1; /* reset state unknown */
337
338 /* If we are here, then we hit an infinite loop. Stop. */
339 panic("EEH: MMIO halt (%d) on device:%s\n", rets[0], pci_name(dev));
340 }
341 goto dn_unlock;
342 }
343
344 /*
345 * Now test for an EEH failure. This is VERY expensive.
346 * Note that the eeh_config_addr may be a parent device
347 * in the case of a device behind a bridge, or it may be
348 * function zero of a multi-function device.
349 * In any case they must share a common PHB.
350 */
351 ret = read_slot_reset_state(pdn, rets);
352
353 /* If the call to firmware failed, punt */
354 if (ret != 0) {
355 printk(KERN_WARNING "EEH: read_slot_reset_state() failed; rc=%d dn=%s\n",
356 ret, dn->full_name);
357 false_positives++;
358 rc = 0;
359 goto dn_unlock;
360 }
361
362 /* If EEH is not supported on this device, punt. */
363 if (rets[1] != 1) {
364 printk(KERN_WARNING "EEH: event on unsupported device, rc=%d dn=%s\n",
365 ret, dn->full_name);
366 false_positives++;
367 rc = 0;
368 goto dn_unlock;
369 }
370
371 /* If not the kind of error we know about, punt. */
372 if (rets[0] != 2 && rets[0] != 4 && rets[0] != 5) {
373 false_positives++;
374 rc = 0;
375 goto dn_unlock;
376 }
377
378 /* Note that config-io to empty slots may fail;
379 * we recognize empty because they don't have children. */
380 if ((rets[0] == 5) && (dn->child == NULL)) {
381 false_positives++;
382 rc = 0;
383 goto dn_unlock;
384 }
385
386 slot_resets++;
387
388 /* Avoid repeated reports of this failure, including problems
389 * with other functions on this device, and functions under
390 * bridges. */
391 eeh_mark_slot (dn, EEH_MODE_ISOLATED);
392 spin_unlock_irqrestore(&confirm_error_lock, flags);
393
394 state = pci_channel_io_normal;
395 if ((rets[0] == 2) || (rets[0] == 4))
396 state = pci_channel_io_frozen;
397 if (rets[0] == 5)
398 state = pci_channel_io_perm_failure;
399 eeh_send_failure_event (dn, dev, state, rets[2]);
400
401 /* Most EEH events are due to device driver bugs. Having
402 * a stack trace will help the device-driver authors figure
403 * out what happened. So print that out. */
404 if (rets[0] != 5) dump_stack();
405 return 1;
406
407 dn_unlock:
408 spin_unlock_irqrestore(&confirm_error_lock, flags);
409 return rc;
410 }
411
412 EXPORT_SYMBOL_GPL(eeh_dn_check_failure);
413
414 /**
415 * eeh_check_failure - check if all 1's data is due to EEH slot freeze
416 * @token i/o token, should be address in the form 0xA....
417 * @val value, should be all 1's (XXX why do we need this arg??)
418 *
419 * Check for an EEH failure at the given token address. Call this
420 * routine if the result of a read was all 0xff's and you want to
421 * find out if this is due to an EEH slot freeze event. This routine
422 * will query firmware for the EEH status.
423 *
424 * Note this routine is safe to call in an interrupt context.
425 */
426 unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
427 {
428 unsigned long addr;
429 struct pci_dev *dev;
430 struct device_node *dn;
431
432 /* Finding the phys addr + pci device; this is pretty quick. */
433 addr = eeh_token_to_phys((unsigned long __force) token);
434 dev = pci_get_device_by_addr(addr);
435 if (!dev) {
436 no_device++;
437 return val;
438 }
439
440 dn = pci_device_to_OF_node(dev);
441 eeh_dn_check_failure (dn, dev);
442
443 pci_dev_put(dev);
444 return val;
445 }
446
447 EXPORT_SYMBOL(eeh_check_failure);
448
449 /* ------------------------------------------------------------- */
450 /* The code below deals with error recovery */
451
452 /** Return negative value if a permanent error, else return
453 * a number of milliseconds to wait until the PCI slot is
454 * ready to be used.
455 */
456 static int
457 eeh_slot_availability(struct pci_dn *pdn)
458 {
459 int rc;
460 int rets[3];
461
462 rc = read_slot_reset_state(pdn, rets);
463
464 if (rc) return rc;
465
466 if (rets[1] == 0) return -1; /* EEH is not supported */
467 if (rets[0] == 0) return 0; /* Oll Korrect */
468 if (rets[0] == 5) {
469 if (rets[2] == 0) return -1; /* permanently unavailable */
470 return rets[2]; /* number of millisecs to wait */
471 }
472 if (rets[0] == 1)
473 return 250;
474
475 printk (KERN_ERR "EEH: Slot unavailable: rc=%d, rets=%d %d %d\n",
476 rc, rets[0], rets[1], rets[2]);
477 return -1;
478 }
479
480 /** rtas_pci_slot_reset raises/lowers the pci #RST line
481 * state: 1/0 to raise/lower the #RST
482 *
483 * Clear the EEH-frozen condition on a slot. This routine
484 * asserts the PCI #RST line if the 'state' argument is '1',
485 * and drops the #RST line if 'state is '0'. This routine is
486 * safe to call in an interrupt context.
487 *
488 */
489
490 static void
491 rtas_pci_slot_reset(struct pci_dn *pdn, int state)
492 {
493 int config_addr;
494 int rc;
495
496 BUG_ON (pdn==NULL);
497
498 if (!pdn->phb) {
499 printk (KERN_WARNING "EEH: in slot reset, device node %s has no phb\n",
500 pdn->node->full_name);
501 return;
502 }
503
504 /* Use PE configuration address, if present */
505 config_addr = pdn->eeh_config_addr;
506 if (pdn->eeh_pe_config_addr)
507 config_addr = pdn->eeh_pe_config_addr;
508
509 rc = rtas_call(ibm_set_slot_reset,4,1, NULL,
510 config_addr,
511 BUID_HI(pdn->phb->buid),
512 BUID_LO(pdn->phb->buid),
513 state);
514 if (rc) {
515 printk (KERN_WARNING "EEH: Unable to reset the failed slot, (%d) #RST=%d dn=%s\n",
516 rc, state, pdn->node->full_name);
517 return;
518 }
519 }
520
521 /** rtas_set_slot_reset -- assert the pci #RST line for 1/4 second
522 * dn -- device node to be reset.
523 *
524 * Return 0 if success, else a non-zero value.
525 */
526
527 int
528 rtas_set_slot_reset(struct pci_dn *pdn)
529 {
530 int i, rc;
531
532 rtas_pci_slot_reset (pdn, 1);
533
534 /* The PCI bus requires that the reset be held high for at least
535 * a 100 milliseconds. We wait a bit longer 'just in case'. */
536
537 #define PCI_BUS_RST_HOLD_TIME_MSEC 250
538 msleep (PCI_BUS_RST_HOLD_TIME_MSEC);
539
540 /* We might get hit with another EEH freeze as soon as the
541 * pci slot reset line is dropped. Make sure we don't miss
542 * these, and clear the flag now. */
543 eeh_clear_slot (pdn->node, EEH_MODE_ISOLATED);
544
545 rtas_pci_slot_reset (pdn, 0);
546
547 /* After a PCI slot has been reset, the PCI Express spec requires
548 * a 1.5 second idle time for the bus to stabilize, before starting
549 * up traffic. */
550 #define PCI_BUS_SETTLE_TIME_MSEC 1800
551 msleep (PCI_BUS_SETTLE_TIME_MSEC);
552
553 /* Now double check with the firmware to make sure the device is
554 * ready to be used; if not, wait for recovery. */
555 for (i=0; i<10; i++) {
556 rc = eeh_slot_availability (pdn);
557 if (rc < 0)
558 printk (KERN_ERR "EEH: failed (%d) to reset slot %s\n", rc, pdn->node->full_name);
559 if (rc == 0)
560 return 0;
561 if (rc < 0)
562 return -1;
563
564 msleep (rc+100);
565 }
566
567 rc = eeh_slot_availability (pdn);
568 if (rc)
569 printk (KERN_ERR "EEH: timeout resetting slot %s\n", pdn->node->full_name);
570
571 return rc;
572 }
573
574 /* ------------------------------------------------------- */
575 /** Save and restore of PCI BARs
576 *
577 * Although firmware will set up BARs during boot, it doesn't
578 * set up device BAR's after a device reset, although it will,
579 * if requested, set up bridge configuration. Thus, we need to
580 * configure the PCI devices ourselves.
581 */
582
583 /**
584 * __restore_bars - Restore the Base Address Registers
585 * Loads the PCI configuration space base address registers,
586 * the expansion ROM base address, the latency timer, and etc.
587 * from the saved values in the device node.
588 */
589 static inline void __restore_bars (struct pci_dn *pdn)
590 {
591 int i;
592
593 if (NULL==pdn->phb) return;
594 for (i=4; i<10; i++) {
595 rtas_write_config(pdn, i*4, 4, pdn->config_space[i]);
596 }
597
598 /* 12 == Expansion ROM Address */
599 rtas_write_config(pdn, 12*4, 4, pdn->config_space[12]);
600
601 #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
602 #define SAVED_BYTE(OFF) (((u8 *)(pdn->config_space))[BYTE_SWAP(OFF)])
603
604 rtas_write_config (pdn, PCI_CACHE_LINE_SIZE, 1,
605 SAVED_BYTE(PCI_CACHE_LINE_SIZE));
606
607 rtas_write_config (pdn, PCI_LATENCY_TIMER, 1,
608 SAVED_BYTE(PCI_LATENCY_TIMER));
609
610 /* max latency, min grant, interrupt pin and line */
611 rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]);
612 }
613
614 /**
615 * eeh_restore_bars - restore the PCI config space info
616 *
617 * This routine performs a recursive walk to the children
618 * of this device as well.
619 */
620 void eeh_restore_bars(struct pci_dn *pdn)
621 {
622 struct device_node *dn;
623 if (!pdn)
624 return;
625
626 if ((pdn->eeh_mode & EEH_MODE_SUPPORTED) && !IS_BRIDGE(pdn->class_code))
627 __restore_bars (pdn);
628
629 dn = pdn->node->child;
630 while (dn) {
631 eeh_restore_bars (PCI_DN(dn));
632 dn = dn->sibling;
633 }
634 }
635
636 /**
637 * eeh_save_bars - save device bars
638 *
639 * Save the values of the device bars. Unlike the restore
640 * routine, this routine is *not* recursive. This is because
641 * PCI devices are added individuallly; but, for the restore,
642 * an entire slot is reset at a time.
643 */
644 static void eeh_save_bars(struct pci_dn *pdn)
645 {
646 int i;
647
648 if (!pdn )
649 return;
650
651 for (i = 0; i < 16; i++)
652 rtas_read_config(pdn, i * 4, 4, &pdn->config_space[i]);
653 }
654
655 void
656 rtas_configure_bridge(struct pci_dn *pdn)
657 {
658 int config_addr;
659 int rc;
660
661 /* Use PE configuration address, if present */
662 config_addr = pdn->eeh_config_addr;
663 if (pdn->eeh_pe_config_addr)
664 config_addr = pdn->eeh_pe_config_addr;
665
666 rc = rtas_call(ibm_configure_bridge,3,1, NULL,
667 config_addr,
668 BUID_HI(pdn->phb->buid),
669 BUID_LO(pdn->phb->buid));
670 if (rc) {
671 printk (KERN_WARNING "EEH: Unable to configure device bridge (%d) for %s\n",
672 rc, pdn->node->full_name);
673 }
674 }
675
676 /* ------------------------------------------------------------- */
677 /* The code below deals with enabling EEH for devices during the
678 * early boot sequence. EEH must be enabled before any PCI probing
679 * can be done.
680 */
681
682 #define EEH_ENABLE 1
683
684 struct eeh_early_enable_info {
685 unsigned int buid_hi;
686 unsigned int buid_lo;
687 };
688
689 /* Enable eeh for the given device node. */
690 static void *early_enable_eeh(struct device_node *dn, void *data)
691 {
692 struct eeh_early_enable_info *info = data;
693 int ret;
694 char *status = get_property(dn, "status", NULL);
695 u32 *class_code = (u32 *)get_property(dn, "class-code", NULL);
696 u32 *vendor_id = (u32 *)get_property(dn, "vendor-id", NULL);
697 u32 *device_id = (u32 *)get_property(dn, "device-id", NULL);
698 u32 *regs;
699 int enable;
700 struct pci_dn *pdn = PCI_DN(dn);
701
702 pdn->class_code = 0;
703 pdn->eeh_mode = 0;
704 pdn->eeh_check_count = 0;
705 pdn->eeh_freeze_count = 0;
706
707 if (status && strcmp(status, "ok") != 0)
708 return NULL; /* ignore devices with bad status */
709
710 /* Ignore bad nodes. */
711 if (!class_code || !vendor_id || !device_id)
712 return NULL;
713
714 /* There is nothing to check on PCI to ISA bridges */
715 if (dn->type && !strcmp(dn->type, "isa")) {
716 pdn->eeh_mode |= EEH_MODE_NOCHECK;
717 return NULL;
718 }
719 pdn->class_code = *class_code;
720
721 /*
722 * Now decide if we are going to "Disable" EEH checking
723 * for this device. We still run with the EEH hardware active,
724 * but we won't be checking for ff's. This means a driver
725 * could return bad data (very bad!), an interrupt handler could
726 * hang waiting on status bits that won't change, etc.
727 * But there are a few cases like display devices that make sense.
728 */
729 enable = 1; /* i.e. we will do checking */
730 #if 0
731 if ((*class_code >> 16) == PCI_BASE_CLASS_DISPLAY)
732 enable = 0;
733 #endif
734
735 if (!enable)
736 pdn->eeh_mode |= EEH_MODE_NOCHECK;
737
738 /* Ok... see if this device supports EEH. Some do, some don't,
739 * and the only way to find out is to check each and every one. */
740 regs = (u32 *)get_property(dn, "reg", NULL);
741 if (regs) {
742 /* First register entry is addr (00BBSS00) */
743 /* Try to enable eeh */
744 ret = rtas_call(ibm_set_eeh_option, 4, 1, NULL,
745 regs[0], info->buid_hi, info->buid_lo,
746 EEH_ENABLE);
747
748 if (ret == 0) {
749 eeh_subsystem_enabled = 1;
750 pdn->eeh_mode |= EEH_MODE_SUPPORTED;
751 pdn->eeh_config_addr = regs[0];
752
753 /* If the newer, better, ibm,get-config-addr-info is supported,
754 * then use that instead. */
755 pdn->eeh_pe_config_addr = 0;
756 if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) {
757 unsigned int rets[2];
758 ret = rtas_call (ibm_get_config_addr_info, 4, 2, rets,
759 pdn->eeh_config_addr,
760 info->buid_hi, info->buid_lo,
761 0);
762 if (ret == 0)
763 pdn->eeh_pe_config_addr = rets[0];
764 }
765 #ifdef DEBUG
766 printk(KERN_DEBUG "EEH: %s: eeh enabled, config=%x pe_config=%x\n",
767 dn->full_name, pdn->eeh_config_addr, pdn->eeh_pe_config_addr);
768 #endif
769 } else {
770
771 /* This device doesn't support EEH, but it may have an
772 * EEH parent, in which case we mark it as supported. */
773 if (dn->parent && PCI_DN(dn->parent)
774 && (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) {
775 /* Parent supports EEH. */
776 pdn->eeh_mode |= EEH_MODE_SUPPORTED;
777 pdn->eeh_config_addr = PCI_DN(dn->parent)->eeh_config_addr;
778 return NULL;
779 }
780 }
781 } else {
782 printk(KERN_WARNING "EEH: %s: unable to get reg property.\n",
783 dn->full_name);
784 }
785
786 eeh_save_bars(pdn);
787 return NULL;
788 }
789
790 /*
791 * Initialize EEH by trying to enable it for all of the adapters in the system.
792 * As a side effect we can determine here if eeh is supported at all.
793 * Note that we leave EEH on so failed config cycles won't cause a machine
794 * check. If a user turns off EEH for a particular adapter they are really
795 * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't
796 * grant access to a slot if EEH isn't enabled, and so we always enable
797 * EEH for all slots/all devices.
798 *
799 * The eeh-force-off option disables EEH checking globally, for all slots.
800 * Even if force-off is set, the EEH hardware is still enabled, so that
801 * newer systems can boot.
802 */
803 void __init eeh_init(void)
804 {
805 struct device_node *phb, *np;
806 struct eeh_early_enable_info info;
807
808 spin_lock_init(&confirm_error_lock);
809 spin_lock_init(&slot_errbuf_lock);
810
811 np = of_find_node_by_path("/rtas");
812 if (np == NULL)
813 return;
814
815 ibm_set_eeh_option = rtas_token("ibm,set-eeh-option");
816 ibm_set_slot_reset = rtas_token("ibm,set-slot-reset");
817 ibm_read_slot_reset_state2 = rtas_token("ibm,read-slot-reset-state2");
818 ibm_read_slot_reset_state = rtas_token("ibm,read-slot-reset-state");
819 ibm_slot_error_detail = rtas_token("ibm,slot-error-detail");
820 ibm_get_config_addr_info = rtas_token("ibm,get-config-addr-info");
821 ibm_configure_bridge = rtas_token ("ibm,configure-bridge");
822
823 if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE)
824 return;
825
826 eeh_error_buf_size = rtas_token("rtas-error-log-max");
827 if (eeh_error_buf_size == RTAS_UNKNOWN_SERVICE) {
828 eeh_error_buf_size = 1024;
829 }
830 if (eeh_error_buf_size > RTAS_ERROR_LOG_MAX) {
831 printk(KERN_WARNING "EEH: rtas-error-log-max is bigger than allocated "
832 "buffer ! (%d vs %d)", eeh_error_buf_size, RTAS_ERROR_LOG_MAX);
833 eeh_error_buf_size = RTAS_ERROR_LOG_MAX;
834 }
835
836 /* Enable EEH for all adapters. Note that eeh requires buid's */
837 for (phb = of_find_node_by_name(NULL, "pci"); phb;
838 phb = of_find_node_by_name(phb, "pci")) {
839 unsigned long buid;
840
841 buid = get_phb_buid(phb);
842 if (buid == 0 || PCI_DN(phb) == NULL)
843 continue;
844
845 info.buid_lo = BUID_LO(buid);
846 info.buid_hi = BUID_HI(buid);
847 traverse_pci_devices(phb, early_enable_eeh, &info);
848 }
849
850 if (eeh_subsystem_enabled)
851 printk(KERN_INFO "EEH: PCI Enhanced I/O Error Handling Enabled\n");
852 else
853 printk(KERN_WARNING "EEH: No capable adapters found\n");
854 }
855
856 /**
857 * eeh_add_device_early - enable EEH for the indicated device_node
858 * @dn: device node for which to set up EEH
859 *
860 * This routine must be used to perform EEH initialization for PCI
861 * devices that were added after system boot (e.g. hotplug, dlpar).
862 * This routine must be called before any i/o is performed to the
863 * adapter (inluding any config-space i/o).
864 * Whether this actually enables EEH or not for this device depends
865 * on the CEC architecture, type of the device, on earlier boot
866 * command-line arguments & etc.
867 */
868 void eeh_add_device_early(struct device_node *dn)
869 {
870 struct pci_controller *phb;
871 struct eeh_early_enable_info info;
872
873 if (!dn || !PCI_DN(dn))
874 return;
875 phb = PCI_DN(dn)->phb;
876
877 /* USB Bus children of PCI devices will not have BUID's */
878 if (NULL == phb || 0 == phb->buid)
879 return;
880
881 info.buid_hi = BUID_HI(phb->buid);
882 info.buid_lo = BUID_LO(phb->buid);
883 early_enable_eeh(dn, &info);
884 }
885 EXPORT_SYMBOL_GPL(eeh_add_device_early);
886
887 void eeh_add_device_tree_early(struct device_node *dn)
888 {
889 struct device_node *sib;
890 for (sib = dn->child; sib; sib = sib->sibling)
891 eeh_add_device_tree_early(sib);
892 eeh_add_device_early(dn);
893 }
894 EXPORT_SYMBOL_GPL(eeh_add_device_tree_early);
895
896 void eeh_add_device_tree_late(struct pci_bus *bus)
897 {
898 struct pci_dev *dev;
899
900 list_for_each_entry(dev, &bus->devices, bus_list) {
901 eeh_add_device_late(dev);
902 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
903 struct pci_bus *subbus = dev->subordinate;
904 if (subbus)
905 eeh_add_device_tree_late(subbus);
906 }
907 }
908 }
909
910 /**
911 * eeh_add_device_late - perform EEH initialization for the indicated pci device
912 * @dev: pci device for which to set up EEH
913 *
914 * This routine must be used to complete EEH initialization for PCI
915 * devices that were added after system boot (e.g. hotplug, dlpar).
916 */
917 void eeh_add_device_late(struct pci_dev *dev)
918 {
919 struct device_node *dn;
920 struct pci_dn *pdn;
921
922 if (!dev || !eeh_subsystem_enabled)
923 return;
924
925 #ifdef DEBUG
926 printk(KERN_DEBUG "EEH: adding device %s\n", pci_name(dev));
927 #endif
928
929 pci_dev_get (dev);
930 dn = pci_device_to_OF_node(dev);
931 pdn = PCI_DN(dn);
932 pdn->pcidev = dev;
933
934 pci_addr_cache_insert_device (dev);
935 }
936 EXPORT_SYMBOL_GPL(eeh_add_device_late);
937
938 /**
939 * eeh_remove_device - undo EEH setup for the indicated pci device
940 * @dev: pci device to be removed
941 *
942 * This routine should be when a device is removed from a running
943 * system (e.g. by hotplug or dlpar).
944 */
945 void eeh_remove_device(struct pci_dev *dev)
946 {
947 struct device_node *dn;
948 if (!dev || !eeh_subsystem_enabled)
949 return;
950
951 /* Unregister the device with the EEH/PCI address search system */
952 #ifdef DEBUG
953 printk(KERN_DEBUG "EEH: remove device %s\n", pci_name(dev));
954 #endif
955 pci_addr_cache_remove_device(dev);
956
957 dn = pci_device_to_OF_node(dev);
958 PCI_DN(dn)->pcidev = NULL;
959 pci_dev_put (dev);
960 }
961 EXPORT_SYMBOL_GPL(eeh_remove_device);
962
963 void eeh_remove_bus_device(struct pci_dev *dev)
964 {
965 eeh_remove_device(dev);
966 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
967 struct pci_bus *bus = dev->subordinate;
968 struct list_head *ln;
969 if (!bus)
970 return;
971 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
972 struct pci_dev *pdev = pci_dev_b(ln);
973 if (pdev)
974 eeh_remove_bus_device(pdev);
975 }
976 }
977 }
978 EXPORT_SYMBOL_GPL(eeh_remove_bus_device);
979
980 static int proc_eeh_show(struct seq_file *m, void *v)
981 {
982 if (0 == eeh_subsystem_enabled) {
983 seq_printf(m, "EEH Subsystem is globally disabled\n");
984 seq_printf(m, "eeh_total_mmio_ffs=%ld\n", total_mmio_ffs);
985 } else {
986 seq_printf(m, "EEH Subsystem is enabled\n");
987 seq_printf(m,
988 "no device=%ld\n"
989 "no device node=%ld\n"
990 "no config address=%ld\n"
991 "check not wanted=%ld\n"
992 "eeh_total_mmio_ffs=%ld\n"
993 "eeh_false_positives=%ld\n"
994 "eeh_ignored_failures=%ld\n"
995 "eeh_slot_resets=%ld\n",
996 no_device, no_dn, no_cfg_addr,
997 ignored_check, total_mmio_ffs,
998 false_positives, ignored_failures,
999 slot_resets);
1000 }
1001
1002 return 0;
1003 }
1004
1005 static int proc_eeh_open(struct inode *inode, struct file *file)
1006 {
1007 return single_open(file, proc_eeh_show, NULL);
1008 }
1009
1010 static struct file_operations proc_eeh_operations = {
1011 .open = proc_eeh_open,
1012 .read = seq_read,
1013 .llseek = seq_lseek,
1014 .release = single_release,
1015 };
1016
1017 static int __init eeh_init_proc(void)
1018 {
1019 struct proc_dir_entry *e;
1020
1021 if (machine_is(pseries)) {
1022 e = create_proc_entry("ppc64/eeh", 0, NULL);
1023 if (e)
1024 e->proc_fops = &proc_eeh_operations;
1025 }
1026
1027 return 0;
1028 }
1029 __initcall(eeh_init_proc);
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