2 * MPC85xx/86xx PCI/PCIE support routing.
4 * Copyright 2007 Freescale Semiconductor, Inc
6 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
7 * Recode: ZHANG WEI <wei.zhang@freescale.com>
8 * Rewrite the routing for Frescale PCI and PCI Express
9 * Roy Zang <tie-fei.zang@freescale.com>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/delay.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
25 #include <asm/pci-bridge.h>
26 #include <asm/machdep.h>
27 #include <sysdev/fsl_soc.h>
28 #include <sysdev/fsl_pci.h>
30 /* atmu setup for fsl pci/pcie controller */
31 void __init
setup_pci_atmu(struct pci_controller
*hose
, struct resource
*rsrc
)
33 struct ccsr_pci __iomem
*pci
;
36 pr_debug("PCI memory map start 0x%x, size 0x%x\n", rsrc
->start
,
37 rsrc
->end
- rsrc
->start
+ 1);
38 pci
= ioremap(rsrc
->start
, rsrc
->end
- rsrc
->start
+ 1);
40 /* Disable all windows (except powar0 since its ignored) */
41 for(i
= 1; i
< 5; i
++)
42 out_be32(&pci
->pow
[i
].powar
, 0);
43 for(i
= 0; i
< 3; i
++)
44 out_be32(&pci
->piw
[i
].piwar
, 0);
46 /* Setup outbound MEM window */
47 for(i
= 0; i
< 3; i
++)
48 if (hose
->mem_resources
[i
].flags
& IORESOURCE_MEM
){
49 pr_debug("PCI MEM resource start 0x%08x, size 0x%08x.\n",
50 hose
->mem_resources
[i
].start
,
51 hose
->mem_resources
[i
].end
52 - hose
->mem_resources
[i
].start
+ 1);
53 out_be32(&pci
->pow
[i
+1].potar
,
54 (hose
->mem_resources
[i
].start
>> 12)
56 out_be32(&pci
->pow
[i
+1].potear
, 0);
57 out_be32(&pci
->pow
[i
+1].powbar
,
58 (hose
->mem_resources
[i
].start
>> 12)
61 out_be32(&pci
->pow
[i
+1].powar
, 0x80044000
62 | (__ilog2(hose
->mem_resources
[i
].end
63 - hose
->mem_resources
[i
].start
+ 1) - 1));
66 /* Setup outbound IO window */
67 if (hose
->io_resource
.flags
& IORESOURCE_IO
){
68 pr_debug("PCI IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
69 hose
->io_resource
.start
,
70 hose
->io_resource
.end
- hose
->io_resource
.start
+ 1,
72 out_be32(&pci
->pow
[i
+1].potar
, (hose
->io_resource
.start
>> 12)
74 out_be32(&pci
->pow
[i
+1].potear
, 0);
75 out_be32(&pci
->pow
[i
+1].powbar
, (hose
->io_base_phys
>> 12)
78 out_be32(&pci
->pow
[i
+1].powar
, 0x80088000
79 | (__ilog2(hose
->io_resource
.end
80 - hose
->io_resource
.start
+ 1) - 1));
83 /* Setup 2G inbound Memory Window @ 1 */
84 out_be32(&pci
->piw
[2].pitar
, 0x00000000);
85 out_be32(&pci
->piw
[2].piwbar
,0x00000000);
86 out_be32(&pci
->piw
[2].piwar
, PIWAR_2G
);
89 void __init
setup_pci_cmd(struct pci_controller
*hose
)
92 early_read_config_word(hose
, 0, 0, PCI_COMMAND
, &cmd
);
93 cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
95 early_write_config_word(hose
, 0, 0, PCI_COMMAND
, cmd
);
96 early_write_config_byte(hose
, 0, 0, PCI_LATENCY_TIMER
, 0x80);
99 static void __devinit
quirk_fsl_pcie_transparent(struct pci_dev
*dev
)
101 struct resource
*res
;
102 int i
, res_idx
= PCI_BRIDGE_RESOURCES
;
103 struct pci_controller
*hose
;
105 /* if we aren't a PCIe don't bother */
106 if (!pci_find_capability(dev
, PCI_CAP_ID_EXP
))
110 * Make the bridge be transparent.
112 dev
->transparent
= 1;
114 hose
= pci_bus_to_host(dev
->bus
);
116 printk(KERN_ERR
"Can't find hose for bus %d\n",
121 /* Clear out any of the virtual P2P bridge registers */
122 pci_write_config_word(dev
, PCI_IO_BASE_UPPER16
, 0);
123 pci_write_config_word(dev
, PCI_IO_LIMIT_UPPER16
, 0);
124 pci_write_config_byte(dev
, PCI_IO_BASE
, 0x10);
125 pci_write_config_byte(dev
, PCI_IO_LIMIT
, 0);
126 pci_write_config_word(dev
, PCI_MEMORY_BASE
, 0x10);
127 pci_write_config_word(dev
, PCI_MEMORY_LIMIT
, 0);
128 pci_write_config_word(dev
, PCI_PREF_BASE_UPPER32
, 0x0);
129 pci_write_config_word(dev
, PCI_PREF_LIMIT_UPPER32
, 0x0);
130 pci_write_config_word(dev
, PCI_PREF_MEMORY_BASE
, 0x10);
131 pci_write_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, 0);
133 if (hose
->io_resource
.flags
) {
134 res
= &dev
->resource
[res_idx
++];
135 res
->start
= hose
->io_resource
.start
;
136 res
->end
= hose
->io_resource
.end
;
137 res
->flags
= hose
->io_resource
.flags
;
138 update_bridge_resource(dev
, res
);
141 for (i
= 0; i
< 3; i
++) {
142 res
= &dev
->resource
[res_idx
+ i
];
143 res
->start
= hose
->mem_resources
[i
].start
;
144 res
->end
= hose
->mem_resources
[i
].end
;
145 res
->flags
= hose
->mem_resources
[i
].flags
;
146 update_bridge_resource(dev
, res
);
150 int __init
fsl_pcie_check_link(struct pci_controller
*hose
)
153 early_read_config_word(hose
, 0, 0, PCIE_LTSSM
, &val
);
154 if (val
< PCIE_LTSSM_L0
)
159 void fsl_pcibios_fixup_bus(struct pci_bus
*bus
)
161 struct pci_controller
*hose
= (struct pci_controller
*) bus
->sysdata
;
164 /* deal with bogus pci_bus when we don't have anything connected on PCIe */
165 if (hose
->indirect_type
& PPC_INDIRECT_TYPE_NO_PCIE_LINK
) {
167 for (i
= 0; i
< 4; ++i
)
168 bus
->resource
[i
] = bus
->parent
->resource
[i
];
173 int __init
fsl_add_bridge(struct device_node
*dev
, int is_primary
)
176 struct pci_controller
*hose
;
177 struct resource rsrc
;
178 const int *bus_range
;
180 pr_debug("Adding PCI host bridge %s\n", dev
->full_name
);
182 /* Fetch host bridge registers address */
183 if (of_address_to_resource(dev
, 0, &rsrc
)) {
184 printk(KERN_WARNING
"Can't get pci register base!");
188 /* Get bus range if any */
189 bus_range
= of_get_property(dev
, "bus-range", &len
);
190 if (bus_range
== NULL
|| len
< 2 * sizeof(int))
191 printk(KERN_WARNING
"Can't get bus-range for %s, assume"
192 " bus 0\n", dev
->full_name
);
194 pci_assign_all_buses
= 1;
195 hose
= pcibios_alloc_controller(dev
);
199 hose
->first_busno
= bus_range
? bus_range
[0] : 0x0;
200 hose
->last_busno
= bus_range
? bus_range
[1] : 0xff;
202 setup_indirect_pci(hose
, rsrc
.start
, rsrc
.start
+ 0x4,
203 PPC_INDIRECT_TYPE_BIG_ENDIAN
);
206 /* check PCI express link status */
207 if (early_find_capability(hose
, 0, 0, PCI_CAP_ID_EXP
)) {
208 hose
->indirect_type
= PPC_INDIRECT_TYPE_EXT_REG
|
209 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS
;
210 if (fsl_pcie_check_link(hose
))
211 hose
->indirect_type
|= PPC_INDIRECT_TYPE_NO_PCIE_LINK
;
214 printk(KERN_INFO
"Found FSL PCI host bridge at 0x%016llx."
215 "Firmware bus number: %d->%d\n",
216 (unsigned long long)rsrc
.start
, hose
->first_busno
,
219 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
220 hose
, hose
->cfg_addr
, hose
->cfg_data
);
222 /* Interpret the "ranges" property */
223 /* This also maps the I/O region and sets isa_io/mem_base */
224 pci_process_bridge_OF_ranges(hose
, dev
, is_primary
);
226 /* Setup PEX window registers */
227 setup_pci_atmu(hose
, &rsrc
);
232 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0012, quirk_fsl_pcie_transparent
);
233 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0013, quirk_fsl_pcie_transparent
);
234 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0014, quirk_fsl_pcie_transparent
);
235 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0015, quirk_fsl_pcie_transparent
);
236 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0018, quirk_fsl_pcie_transparent
);
237 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0019, quirk_fsl_pcie_transparent
);
238 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x001a, quirk_fsl_pcie_transparent
);
239 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0020, quirk_fsl_pcie_transparent
);
240 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0021, quirk_fsl_pcie_transparent
);
241 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0024, quirk_fsl_pcie_transparent
);
242 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0025, quirk_fsl_pcie_transparent
);
243 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0030, quirk_fsl_pcie_transparent
);
244 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x0031, quirk_fsl_pcie_transparent
);
245 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent
);
246 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent
);