projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
powerpc/fsl_rio: move machine_check handler
[deliverable/linux.git] / arch / powerpc / sysdev / fsl_rio.c
1 /*
2 * Freescale MPC85xx/MPC86xx RapidIO support
3 *
4 * Copyright 2009 Sysgo AG
5 * Thomas Moll <thomas.moll@sysgo.com>
6 * - fixed maintenance access routines, check for aligned access
7 *
8 * Copyright 2009 Integrated Device Technology, Inc.
9 * Alex Bounine <alexandre.bounine@idt.com>
10 * - Added Port-Write message handling
11 * - Added Machine Check exception handling
12 *
13 * Copyright (C) 2007, 2008 Freescale Semiconductor, Inc.
14 * Zhang Wei <wei.zhang@freescale.com>
15 *
16 * Copyright 2005 MontaVista Software, Inc.
17 * Matt Porter <mporter@kernel.crashing.org>
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2 of the License, or (at your
22 * option) any later version.
23 */
24
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/interrupt.h>
30 #include <linux/device.h>
31 #include <linux/rio.h>
32 #include <linux/rio_drv.h>
33 #include <linux/of_platform.h>
34 #include <linux/delay.h>
35 #include <linux/slab.h>
36 #include <linux/kfifo.h>
37
38 #include <asm/io.h>
39 #include <asm/machdep.h>
40 #include <asm/uaccess.h>
41
42 #undef DEBUG_PW /* Port-Write debugging */
43
44 /* RapidIO definition irq, which read from OF-tree */
45 #define IRQ_RIO_BELL(m) (((struct rio_priv *)(m->priv))->bellirq)
46 #define IRQ_RIO_TX(m) (((struct rio_priv *)(m->priv))->txirq)
47 #define IRQ_RIO_RX(m) (((struct rio_priv *)(m->priv))->rxirq)
48 #define IRQ_RIO_PW(m) (((struct rio_priv *)(m->priv))->pwirq)
49
50 #define RIO_ATMU_REGS_OFFSET 0x10c00
51 #define RIO_P_MSG_REGS_OFFSET 0x11000
52 #define RIO_S_MSG_REGS_OFFSET 0x13000
53 #define RIO_GCCSR 0x13c
54 #define RIO_ESCSR 0x158
55 #define RIO_CCSR 0x15c
56 #define RIO_LTLEDCSR 0x0608
57 #define RIO_LTLEDCSR_IER 0x80000000
58 #define RIO_LTLEDCSR_PRT 0x01000000
59 #define RIO_LTLEECSR 0x060c
60 #define RIO_EPWISR 0x10010
61 #define RIO_ISR_AACR 0x10120
62 #define RIO_ISR_AACR_AA 0x1 /* Accept All ID */
63 #define RIO_MAINT_WIN_SIZE 0x400000
64 #define RIO_DBELL_WIN_SIZE 0x1000
65
66 #define RIO_MSG_OMR_MUI 0x00000002
67 #define RIO_MSG_OSR_TE 0x00000080
68 #define RIO_MSG_OSR_QOI 0x00000020
69 #define RIO_MSG_OSR_QFI 0x00000010
70 #define RIO_MSG_OSR_MUB 0x00000004
71 #define RIO_MSG_OSR_EOMI 0x00000002
72 #define RIO_MSG_OSR_QEI 0x00000001
73
74 #define RIO_MSG_IMR_MI 0x00000002
75 #define RIO_MSG_ISR_TE 0x00000080
76 #define RIO_MSG_ISR_QFI 0x00000010
77 #define RIO_MSG_ISR_DIQI 0x00000001
78
79 #define RIO_IPWMR_SEN 0x00100000
80 #define RIO_IPWMR_QFIE 0x00000100
81 #define RIO_IPWMR_EIE 0x00000020
82 #define RIO_IPWMR_CQ 0x00000002
83 #define RIO_IPWMR_PWE 0x00000001
84
85 #define RIO_IPWSR_QF 0x00100000
86 #define RIO_IPWSR_TE 0x00000080
87 #define RIO_IPWSR_QFI 0x00000010
88 #define RIO_IPWSR_PWD 0x00000008
89 #define RIO_IPWSR_PWB 0x00000004
90
91 #define RIO_EPWISR_PINT 0x80000000
92 #define RIO_EPWISR_PW 0x00000001
93
94 #define RIO_MSG_DESC_SIZE 32
95 #define RIO_MSG_BUFFER_SIZE 4096
96 #define RIO_MIN_TX_RING_SIZE 2
97 #define RIO_MAX_TX_RING_SIZE 2048
98 #define RIO_MIN_RX_RING_SIZE 2
99 #define RIO_MAX_RX_RING_SIZE 2048
100
101 #define DOORBELL_DMR_DI 0x00000002
102 #define DOORBELL_DSR_TE 0x00000080
103 #define DOORBELL_DSR_QFI 0x00000010
104 #define DOORBELL_DSR_DIQI 0x00000001
105 #define DOORBELL_TID_OFFSET 0x02
106 #define DOORBELL_SID_OFFSET 0x04
107 #define DOORBELL_INFO_OFFSET 0x06
108
109 #define DOORBELL_MESSAGE_SIZE 0x08
110 #define DBELL_SID(x) (*(u16 *)(x + DOORBELL_SID_OFFSET))
111 #define DBELL_TID(x) (*(u16 *)(x + DOORBELL_TID_OFFSET))
112 #define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET))
113
114 struct rio_atmu_regs {
115 u32 rowtar;
116 u32 rowtear;
117 u32 rowbar;
118 u32 pad2;
119 u32 rowar;
120 u32 pad3[3];
121 };
122
123 struct rio_msg_regs {
124 u32 omr; /* 0xD_3000 - Outbound message 0 mode register */
125 u32 osr; /* 0xD_3004 - Outbound message 0 status register */
126 u32 pad1;
127 u32 odqdpar; /* 0xD_300C - Outbound message 0 descriptor queue
128 dequeue pointer address register */
129 u32 pad2;
130 u32 osar; /* 0xD_3014 - Outbound message 0 source address
131 register */
132 u32 odpr; /* 0xD_3018 - Outbound message 0 destination port
133 register */
134 u32 odatr; /* 0xD_301C - Outbound message 0 destination attributes
135 Register*/
136 u32 odcr; /* 0xD_3020 - Outbound message 0 double-word count
137 register */
138 u32 pad3;
139 u32 odqepar; /* 0xD_3028 - Outbound message 0 descriptor queue
140 enqueue pointer address register */
141 u32 pad4[13];
142 u32 imr; /* 0xD_3060 - Inbound message 0 mode register */
143 u32 isr; /* 0xD_3064 - Inbound message 0 status register */
144 u32 pad5;
145 u32 ifqdpar; /* 0xD_306C - Inbound message 0 frame queue dequeue
146 pointer address register*/
147 u32 pad6;
148 u32 ifqepar; /* 0xD_3074 - Inbound message 0 frame queue enqueue
149 pointer address register */
150 u32 pad7[226];
151 u32 odmr; /* 0xD_3400 - Outbound doorbell mode register */
152 u32 odsr; /* 0xD_3404 - Outbound doorbell status register */
153 u32 res0[4];
154 u32 oddpr; /* 0xD_3418 - Outbound doorbell destination port
155 register */
156 u32 oddatr; /* 0xD_341c - Outbound doorbell destination attributes
157 register */
158 u32 res1[3];
159 u32 odretcr; /* 0xD_342C - Outbound doorbell retry error threshold
160 configuration register */
161 u32 res2[12];
162 u32 dmr; /* 0xD_3460 - Inbound doorbell mode register */
163 u32 dsr; /* 0xD_3464 - Inbound doorbell status register */
164 u32 pad8;
165 u32 dqdpar; /* 0xD_346C - Inbound doorbell queue dequeue Pointer
166 address register */
167 u32 pad9;
168 u32 dqepar; /* 0xD_3474 - Inbound doorbell Queue enqueue pointer
169 address register */
170 u32 pad10[26];
171 u32 pwmr; /* 0xD_34E0 - Inbound port-write mode register */
172 u32 pwsr; /* 0xD_34E4 - Inbound port-write status register */
173 u32 epwqbar; /* 0xD_34E8 - Extended Port-Write Queue Base Address
174 register */
175 u32 pwqbar; /* 0xD_34EC - Inbound port-write queue base address
176 register */
177 };
178
179 struct rio_tx_desc {
180 u32 res1;
181 u32 saddr;
182 u32 dport;
183 u32 dattr;
184 u32 res2;
185 u32 res3;
186 u32 dwcnt;
187 u32 res4;
188 };
189
190 struct rio_dbell_ring {
191 void *virt;
192 dma_addr_t phys;
193 };
194
195 struct rio_msg_tx_ring {
196 void *virt;
197 dma_addr_t phys;
198 void *virt_buffer[RIO_MAX_TX_RING_SIZE];
199 dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
200 int tx_slot;
201 int size;
202 void *dev_id;
203 };
204
205 struct rio_msg_rx_ring {
206 void *virt;
207 dma_addr_t phys;
208 void *virt_buffer[RIO_MAX_RX_RING_SIZE];
209 int rx_slot;
210 int size;
211 void *dev_id;
212 };
213
214 struct rio_port_write_msg {
215 void *virt;
216 dma_addr_t phys;
217 u32 msg_count;
218 u32 err_count;
219 u32 discard_count;
220 };
221
222 struct rio_priv {
223 struct device *dev;
224 void __iomem *regs_win;
225 struct rio_atmu_regs __iomem *atmu_regs;
226 struct rio_atmu_regs __iomem *maint_atmu_regs;
227 struct rio_atmu_regs __iomem *dbell_atmu_regs;
228 void __iomem *dbell_win;
229 void __iomem *maint_win;
230 struct rio_msg_regs __iomem *msg_regs;
231 struct rio_dbell_ring dbell_ring;
232 struct rio_msg_tx_ring msg_tx_ring;
233 struct rio_msg_rx_ring msg_rx_ring;
234 struct rio_port_write_msg port_write_msg;
235 int bellirq;
236 int txirq;
237 int rxirq;
238 int pwirq;
239 struct work_struct pw_work;
240 struct kfifo pw_fifo;
241 spinlock_t pw_fifo_lock;
242 };
243
244 #define __fsl_read_rio_config(x, addr, err, op) \
245 __asm__ __volatile__( \
246 "1: "op" %1,0(%2)\n" \
247 " eieio\n" \
248 "2:\n" \
249 ".section .fixup,\"ax\"\n" \
250 "3: li %1,-1\n" \
251 " li %0,%3\n" \
252 " b 2b\n" \
253 ".section __ex_table,\"a\"\n" \
254 " .align 2\n" \
255 " .long 1b,3b\n" \
256 ".text" \
257 : "=r" (err), "=r" (x) \
258 : "b" (addr), "i" (-EFAULT), "0" (err))
259
260 static void __iomem *rio_regs_win;
261
262 #ifdef CONFIG_E500
263 int fsl_rio_mcheck_exception(struct pt_regs *regs)
264 {
265 const struct exception_table_entry *entry = NULL;
266 unsigned long reason = mfspr(SPRN_MCSR);
267
268 if (reason & MCSR_BUS_RBERR) {
269 reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
270 if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) {
271 /* Check if we are prepared to handle this fault */
272 entry = search_exception_tables(regs->nip);
273 if (entry) {
274 pr_debug("RIO: %s - MC Exception handled\n",
275 __func__);
276 out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR),
277 0);
278 regs->msr |= MSR_RI;
279 regs->nip = entry->fixup;
280 return 1;
281 }
282 }
283 }
284
285 return 0;
286 }
287 EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception);
288 #endif
289
290 /**
291 * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
292 * @mport: RapidIO master port info
293 * @index: ID of RapidIO interface
294 * @destid: Destination ID of target device
295 * @data: 16-bit info field of RapidIO doorbell message
296 *
297 * Sends a MPC85xx doorbell message. Returns %0 on success or
298 * %-EINVAL on failure.
299 */
300 static int fsl_rio_doorbell_send(struct rio_mport *mport,
301 int index, u16 destid, u16 data)
302 {
303 struct rio_priv *priv = mport->priv;
304 pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
305 index, destid, data);
306 switch (mport->phy_type) {
307 case RIO_PHY_PARALLEL:
308 out_be32(&priv->dbell_atmu_regs->rowtar, destid << 22);
309 out_be16(priv->dbell_win, data);
310 break;
311 case RIO_PHY_SERIAL:
312 /* In the serial version silicons, such as MPC8548, MPC8641,
313 * below operations is must be.
314 */
315 out_be32(&priv->msg_regs->odmr, 0x00000000);
316 out_be32(&priv->msg_regs->odretcr, 0x00000004);
317 out_be32(&priv->msg_regs->oddpr, destid << 16);
318 out_be32(&priv->msg_regs->oddatr, data);
319 out_be32(&priv->msg_regs->odmr, 0x00000001);
320 break;
321 }
322
323 return 0;
324 }
325
326 /**
327 * fsl_local_config_read - Generate a MPC85xx local config space read
328 * @mport: RapidIO master port info
329 * @index: ID of RapdiIO interface
330 * @offset: Offset into configuration space
331 * @len: Length (in bytes) of the maintenance transaction
332 * @data: Value to be read into
333 *
334 * Generates a MPC85xx local configuration space read. Returns %0 on
335 * success or %-EINVAL on failure.
336 */
337 static int fsl_local_config_read(struct rio_mport *mport,
338 int index, u32 offset, int len, u32 *data)
339 {
340 struct rio_priv *priv = mport->priv;
341 pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
342 offset);
343 *data = in_be32(priv->regs_win + offset);
344
345 return 0;
346 }
347
348 /**
349 * fsl_local_config_write - Generate a MPC85xx local config space write
350 * @mport: RapidIO master port info
351 * @index: ID of RapdiIO interface
352 * @offset: Offset into configuration space
353 * @len: Length (in bytes) of the maintenance transaction
354 * @data: Value to be written
355 *
356 * Generates a MPC85xx local configuration space write. Returns %0 on
357 * success or %-EINVAL on failure.
358 */
359 static int fsl_local_config_write(struct rio_mport *mport,
360 int index, u32 offset, int len, u32 data)
361 {
362 struct rio_priv *priv = mport->priv;
363 pr_debug
364 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
365 index, offset, data);
366 out_be32(priv->regs_win + offset, data);
367
368 return 0;
369 }
370
371 /**
372 * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
373 * @mport: RapidIO master port info
374 * @index: ID of RapdiIO interface
375 * @destid: Destination ID of transaction
376 * @hopcount: Number of hops to target device
377 * @offset: Offset into configuration space
378 * @len: Length (in bytes) of the maintenance transaction
379 * @val: Location to be read into
380 *
381 * Generates a MPC85xx read maintenance transaction. Returns %0 on
382 * success or %-EINVAL on failure.
383 */
384 static int
385 fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
386 u8 hopcount, u32 offset, int len, u32 *val)
387 {
388 struct rio_priv *priv = mport->priv;
389 u8 *data;
390 u32 rval, err = 0;
391
392 pr_debug
393 ("fsl_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n",
394 index, destid, hopcount, offset, len);
395
396 /* 16MB maintenance window possible */
397 /* allow only aligned access to maintenance registers */
398 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
399 return -EINVAL;
400
401 out_be32(&priv->maint_atmu_regs->rowtar,
402 (destid << 22) | (hopcount << 12) | (offset >> 12));
403 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
404
405 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
406 switch (len) {
407 case 1:
408 __fsl_read_rio_config(rval, data, err, "lbz");
409 break;
410 case 2:
411 __fsl_read_rio_config(rval, data, err, "lhz");
412 break;
413 case 4:
414 __fsl_read_rio_config(rval, data, err, "lwz");
415 break;
416 default:
417 return -EINVAL;
418 }
419
420 if (err) {
421 pr_debug("RIO: cfg_read error %d for %x:%x:%x\n",
422 err, destid, hopcount, offset);
423 }
424
425 *val = rval;
426
427 return err;
428 }
429
430 /**
431 * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
432 * @mport: RapidIO master port info
433 * @index: ID of RapdiIO interface
434 * @destid: Destination ID of transaction
435 * @hopcount: Number of hops to target device
436 * @offset: Offset into configuration space
437 * @len: Length (in bytes) of the maintenance transaction
438 * @val: Value to be written
439 *
440 * Generates an MPC85xx write maintenance transaction. Returns %0 on
441 * success or %-EINVAL on failure.
442 */
443 static int
444 fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
445 u8 hopcount, u32 offset, int len, u32 val)
446 {
447 struct rio_priv *priv = mport->priv;
448 u8 *data;
449 pr_debug
450 ("fsl_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
451 index, destid, hopcount, offset, len, val);
452
453 /* 16MB maintenance windows possible */
454 /* allow only aligned access to maintenance registers */
455 if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
456 return -EINVAL;
457
458 out_be32(&priv->maint_atmu_regs->rowtar,
459 (destid << 22) | (hopcount << 12) | (offset >> 12));
460 out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
461
462 data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
463 switch (len) {
464 case 1:
465 out_8((u8 *) data, val);
466 break;
467 case 2:
468 out_be16((u16 *) data, val);
469 break;
470 case 4:
471 out_be32((u32 *) data, val);
472 break;
473 default:
474 return -EINVAL;
475 }
476
477 return 0;
478 }
479
480 /**
481 * fsl_add_outb_message - Add message to the MPC85xx outbound message queue
482 * @mport: Master port with outbound message queue
483 * @rdev: Target of outbound message
484 * @mbox: Outbound mailbox
485 * @buffer: Message to add to outbound queue
486 * @len: Length of message
487 *
488 * Adds the @buffer message to the MPC85xx outbound message queue. Returns
489 * %0 on success or %-EINVAL on failure.
490 */
491 static int
492 fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
493 void *buffer, size_t len)
494 {
495 struct rio_priv *priv = mport->priv;
496 u32 omr;
497 struct rio_tx_desc *desc = (struct rio_tx_desc *)priv->msg_tx_ring.virt
498 + priv->msg_tx_ring.tx_slot;
499 int ret = 0;
500
501 pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \
502 "%8.8x len %8.8x\n", rdev->destid, mbox, (int)buffer, len);
503
504 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
505 ret = -EINVAL;
506 goto out;
507 }
508
509 /* Copy and clear rest of buffer */
510 memcpy(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot], buffer,
511 len);
512 if (len < (RIO_MAX_MSG_SIZE - 4))
513 memset(priv->msg_tx_ring.virt_buffer[priv->msg_tx_ring.tx_slot]
514 + len, 0, RIO_MAX_MSG_SIZE - len);
515
516 switch (mport->phy_type) {
517 case RIO_PHY_PARALLEL:
518 /* Set mbox field for message */
519 desc->dport = mbox & 0x3;
520
521 /* Enable EOMI interrupt, set priority, and set destid */
522 desc->dattr = 0x28000000 | (rdev->destid << 2);
523 break;
524 case RIO_PHY_SERIAL:
525 /* Set mbox field for message, and set destid */
526 desc->dport = (rdev->destid << 16) | (mbox & 0x3);
527
528 /* Enable EOMI interrupt and priority */
529 desc->dattr = 0x28000000;
530 break;
531 }
532
533 /* Set transfer size aligned to next power of 2 (in double words) */
534 desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
535
536 /* Set snooping and source buffer address */
537 desc->saddr = 0x00000004
538 | priv->msg_tx_ring.phys_buffer[priv->msg_tx_ring.tx_slot];
539
540 /* Increment enqueue pointer */
541 omr = in_be32(&priv->msg_regs->omr);
542 out_be32(&priv->msg_regs->omr, omr | RIO_MSG_OMR_MUI);
543
544 /* Go to next descriptor */
545 if (++priv->msg_tx_ring.tx_slot == priv->msg_tx_ring.size)
546 priv->msg_tx_ring.tx_slot = 0;
547
548 out:
549 return ret;
550 }
551
552 /**
553 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
554 * @irq: Linux interrupt number
555 * @dev_instance: Pointer to interrupt-specific data
556 *
557 * Handles outbound message interrupts. Executes a register outbound
558 * mailbox event handler and acks the interrupt occurrence.
559 */
560 static irqreturn_t
561 fsl_rio_tx_handler(int irq, void *dev_instance)
562 {
563 int osr;
564 struct rio_mport *port = (struct rio_mport *)dev_instance;
565 struct rio_priv *priv = port->priv;
566
567 osr = in_be32(&priv->msg_regs->osr);
568
569 if (osr & RIO_MSG_OSR_TE) {
570 pr_info("RIO: outbound message transmission error\n");
571 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_TE);
572 goto out;
573 }
574
575 if (osr & RIO_MSG_OSR_QOI) {
576 pr_info("RIO: outbound message queue overflow\n");
577 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_QOI);
578 goto out;
579 }
580
581 if (osr & RIO_MSG_OSR_EOMI) {
582 u32 dqp = in_be32(&priv->msg_regs->odqdpar);
583 int slot = (dqp - priv->msg_tx_ring.phys) >> 5;
584 port->outb_msg[0].mcback(port, priv->msg_tx_ring.dev_id, -1,
585 slot);
586
587 /* Ack the end-of-message interrupt */
588 out_be32(&priv->msg_regs->osr, RIO_MSG_OSR_EOMI);
589 }
590
591 out:
592 return IRQ_HANDLED;
593 }
594
595 /**
596 * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox
597 * @mport: Master port implementing the outbound message unit
598 * @dev_id: Device specific pointer to pass on event
599 * @mbox: Mailbox to open
600 * @entries: Number of entries in the outbound mailbox ring
601 *
602 * Initializes buffer ring, request the outbound message interrupt,
603 * and enables the outbound message unit. Returns %0 on success and
604 * %-EINVAL or %-ENOMEM on failure.
605 */
606 static int
607 fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
608 {
609 int i, j, rc = 0;
610 struct rio_priv *priv = mport->priv;
611
612 if ((entries < RIO_MIN_TX_RING_SIZE) ||
613 (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
614 rc = -EINVAL;
615 goto out;
616 }
617
618 /* Initialize shadow copy ring */
619 priv->msg_tx_ring.dev_id = dev_id;
620 priv->msg_tx_ring.size = entries;
621
622 for (i = 0; i < priv->msg_tx_ring.size; i++) {
623 priv->msg_tx_ring.virt_buffer[i] =
624 dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
625 &priv->msg_tx_ring.phys_buffer[i], GFP_KERNEL);
626 if (!priv->msg_tx_ring.virt_buffer[i]) {
627 rc = -ENOMEM;
628 for (j = 0; j < priv->msg_tx_ring.size; j++)
629 if (priv->msg_tx_ring.virt_buffer[j])
630 dma_free_coherent(priv->dev,
631 RIO_MSG_BUFFER_SIZE,
632 priv->msg_tx_ring.
633 virt_buffer[j],
634 priv->msg_tx_ring.
635 phys_buffer[j]);
636 goto out;
637 }
638 }
639
640 /* Initialize outbound message descriptor ring */
641 priv->msg_tx_ring.virt = dma_alloc_coherent(priv->dev,
642 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
643 &priv->msg_tx_ring.phys, GFP_KERNEL);
644 if (!priv->msg_tx_ring.virt) {
645 rc = -ENOMEM;
646 goto out_dma;
647 }
648 memset(priv->msg_tx_ring.virt, 0,
649 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE);
650 priv->msg_tx_ring.tx_slot = 0;
651
652 /* Point dequeue/enqueue pointers at first entry in ring */
653 out_be32(&priv->msg_regs->odqdpar, priv->msg_tx_ring.phys);
654 out_be32(&priv->msg_regs->odqepar, priv->msg_tx_ring.phys);
655
656 /* Configure for snooping */
657 out_be32(&priv->msg_regs->osar, 0x00000004);
658
659 /* Clear interrupt status */
660 out_be32(&priv->msg_regs->osr, 0x000000b3);
661
662 /* Hook up outbound message handler */
663 rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0,
664 "msg_tx", (void *)mport);
665 if (rc < 0)
666 goto out_irq;
667
668 /*
669 * Configure outbound message unit
670 * Snooping
671 * Interrupts (all enabled, except QEIE)
672 * Chaining mode
673 * Disable
674 */
675 out_be32(&priv->msg_regs->omr, 0x00100220);
676
677 /* Set number of entries */
678 out_be32(&priv->msg_regs->omr,
679 in_be32(&priv->msg_regs->omr) |
680 ((get_bitmask_order(entries) - 2) << 12));
681
682 /* Now enable the unit */
683 out_be32(&priv->msg_regs->omr, in_be32(&priv->msg_regs->omr) | 0x1);
684
685 out:
686 return rc;
687
688 out_irq:
689 dma_free_coherent(priv->dev,
690 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
691 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
692
693 out_dma:
694 for (i = 0; i < priv->msg_tx_ring.size; i++)
695 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
696 priv->msg_tx_ring.virt_buffer[i],
697 priv->msg_tx_ring.phys_buffer[i]);
698
699 return rc;
700 }
701
702 /**
703 * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox
704 * @mport: Master port implementing the outbound message unit
705 * @mbox: Mailbox to close
706 *
707 * Disables the outbound message unit, free all buffers, and
708 * frees the outbound message interrupt.
709 */
710 static void fsl_close_outb_mbox(struct rio_mport *mport, int mbox)
711 {
712 struct rio_priv *priv = mport->priv;
713 /* Disable inbound message unit */
714 out_be32(&priv->msg_regs->omr, 0);
715
716 /* Free ring */
717 dma_free_coherent(priv->dev,
718 priv->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
719 priv->msg_tx_ring.virt, priv->msg_tx_ring.phys);
720
721 /* Free interrupt */
722 free_irq(IRQ_RIO_TX(mport), (void *)mport);
723 }
724
725 /**
726 * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
727 * @irq: Linux interrupt number
728 * @dev_instance: Pointer to interrupt-specific data
729 *
730 * Handles inbound message interrupts. Executes a registered inbound
731 * mailbox event handler and acks the interrupt occurrence.
732 */
733 static irqreturn_t
734 fsl_rio_rx_handler(int irq, void *dev_instance)
735 {
736 int isr;
737 struct rio_mport *port = (struct rio_mport *)dev_instance;
738 struct rio_priv *priv = port->priv;
739
740 isr = in_be32(&priv->msg_regs->isr);
741
742 if (isr & RIO_MSG_ISR_TE) {
743 pr_info("RIO: inbound message reception error\n");
744 out_be32((void *)&priv->msg_regs->isr, RIO_MSG_ISR_TE);
745 goto out;
746 }
747
748 /* XXX Need to check/dispatch until queue empty */
749 if (isr & RIO_MSG_ISR_DIQI) {
750 /*
751 * We implement *only* mailbox 0, but can receive messages
752 * for any mailbox/letter to that mailbox destination. So,
753 * make the callback with an unknown/invalid mailbox number
754 * argument.
755 */
756 port->inb_msg[0].mcback(port, priv->msg_rx_ring.dev_id, -1, -1);
757
758 /* Ack the queueing interrupt */
759 out_be32(&priv->msg_regs->isr, RIO_MSG_ISR_DIQI);
760 }
761
762 out:
763 return IRQ_HANDLED;
764 }
765
766 /**
767 * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox
768 * @mport: Master port implementing the inbound message unit
769 * @dev_id: Device specific pointer to pass on event
770 * @mbox: Mailbox to open
771 * @entries: Number of entries in the inbound mailbox ring
772 *
773 * Initializes buffer ring, request the inbound message interrupt,
774 * and enables the inbound message unit. Returns %0 on success
775 * and %-EINVAL or %-ENOMEM on failure.
776 */
777 static int
778 fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
779 {
780 int i, rc = 0;
781 struct rio_priv *priv = mport->priv;
782
783 if ((entries < RIO_MIN_RX_RING_SIZE) ||
784 (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
785 rc = -EINVAL;
786 goto out;
787 }
788
789 /* Initialize client buffer ring */
790 priv->msg_rx_ring.dev_id = dev_id;
791 priv->msg_rx_ring.size = entries;
792 priv->msg_rx_ring.rx_slot = 0;
793 for (i = 0; i < priv->msg_rx_ring.size; i++)
794 priv->msg_rx_ring.virt_buffer[i] = NULL;
795
796 /* Initialize inbound message ring */
797 priv->msg_rx_ring.virt = dma_alloc_coherent(priv->dev,
798 priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
799 &priv->msg_rx_ring.phys, GFP_KERNEL);
800 if (!priv->msg_rx_ring.virt) {
801 rc = -ENOMEM;
802 goto out;
803 }
804
805 /* Point dequeue/enqueue pointers at first entry in ring */
806 out_be32(&priv->msg_regs->ifqdpar, (u32) priv->msg_rx_ring.phys);
807 out_be32(&priv->msg_regs->ifqepar, (u32) priv->msg_rx_ring.phys);
808
809 /* Clear interrupt status */
810 out_be32(&priv->msg_regs->isr, 0x00000091);
811
812 /* Hook up inbound message handler */
813 rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
814 "msg_rx", (void *)mport);
815 if (rc < 0) {
816 dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
817 priv->msg_tx_ring.virt_buffer[i],
818 priv->msg_tx_ring.phys_buffer[i]);
819 goto out;
820 }
821
822 /*
823 * Configure inbound message unit:
824 * Snooping
825 * 4KB max message size
826 * Unmask all interrupt sources
827 * Disable
828 */
829 out_be32(&priv->msg_regs->imr, 0x001b0060);
830
831 /* Set number of queue entries */
832 setbits32(&priv->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
833
834 /* Now enable the unit */
835 setbits32(&priv->msg_regs->imr, 0x1);
836
837 out:
838 return rc;
839 }
840
841 /**
842 * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox
843 * @mport: Master port implementing the inbound message unit
844 * @mbox: Mailbox to close
845 *
846 * Disables the inbound message unit, free all buffers, and
847 * frees the inbound message interrupt.
848 */
849 static void fsl_close_inb_mbox(struct rio_mport *mport, int mbox)
850 {
851 struct rio_priv *priv = mport->priv;
852 /* Disable inbound message unit */
853 out_be32(&priv->msg_regs->imr, 0);
854
855 /* Free ring */
856 dma_free_coherent(priv->dev, priv->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
857 priv->msg_rx_ring.virt, priv->msg_rx_ring.phys);
858
859 /* Free interrupt */
860 free_irq(IRQ_RIO_RX(mport), (void *)mport);
861 }
862
863 /**
864 * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
865 * @mport: Master port implementing the inbound message unit
866 * @mbox: Inbound mailbox number
867 * @buf: Buffer to add to inbound queue
868 *
869 * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
870 * %0 on success or %-EINVAL on failure.
871 */
872 static int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
873 {
874 int rc = 0;
875 struct rio_priv *priv = mport->priv;
876
877 pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
878 priv->msg_rx_ring.rx_slot);
879
880 if (priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot]) {
881 printk(KERN_ERR
882 "RIO: error adding inbound buffer %d, buffer exists\n",
883 priv->msg_rx_ring.rx_slot);
884 rc = -EINVAL;
885 goto out;
886 }
887
888 priv->msg_rx_ring.virt_buffer[priv->msg_rx_ring.rx_slot] = buf;
889 if (++priv->msg_rx_ring.rx_slot == priv->msg_rx_ring.size)
890 priv->msg_rx_ring.rx_slot = 0;
891
892 out:
893 return rc;
894 }
895
896 /**
897 * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit
898 * @mport: Master port implementing the inbound message unit
899 * @mbox: Inbound mailbox number
900 *
901 * Gets the next available inbound message from the inbound message queue.
902 * A pointer to the message is returned on success or NULL on failure.
903 */
904 static void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
905 {
906 struct rio_priv *priv = mport->priv;
907 u32 phys_buf, virt_buf;
908 void *buf = NULL;
909 int buf_idx;
910
911 phys_buf = in_be32(&priv->msg_regs->ifqdpar);
912
913 /* If no more messages, then bail out */
914 if (phys_buf == in_be32(&priv->msg_regs->ifqepar))
915 goto out2;
916
917 virt_buf = (u32) priv->msg_rx_ring.virt + (phys_buf
918 - priv->msg_rx_ring.phys);
919 buf_idx = (phys_buf - priv->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
920 buf = priv->msg_rx_ring.virt_buffer[buf_idx];
921
922 if (!buf) {
923 printk(KERN_ERR
924 "RIO: inbound message copy failed, no buffers\n");
925 goto out1;
926 }
927
928 /* Copy max message size, caller is expected to allocate that big */
929 memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE);
930
931 /* Clear the available buffer */
932 priv->msg_rx_ring.virt_buffer[buf_idx] = NULL;
933
934 out1:
935 setbits32(&priv->msg_regs->imr, RIO_MSG_IMR_MI);
936
937 out2:
938 return buf;
939 }
940
941 /**
942 * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
943 * @irq: Linux interrupt number
944 * @dev_instance: Pointer to interrupt-specific data
945 *
946 * Handles doorbell interrupts. Parses a list of registered
947 * doorbell event handlers and executes a matching event handler.
948 */
949 static irqreturn_t
950 fsl_rio_dbell_handler(int irq, void *dev_instance)
951 {
952 int dsr;
953 struct rio_mport *port = (struct rio_mport *)dev_instance;
954 struct rio_priv *priv = port->priv;
955
956 dsr = in_be32(&priv->msg_regs->dsr);
957
958 if (dsr & DOORBELL_DSR_TE) {
959 pr_info("RIO: doorbell reception error\n");
960 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_TE);
961 goto out;
962 }
963
964 if (dsr & DOORBELL_DSR_QFI) {
965 pr_info("RIO: doorbell queue full\n");
966 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI);
967 }
968
969 /* XXX Need to check/dispatch until queue empty */
970 if (dsr & DOORBELL_DSR_DIQI) {
971 u32 dmsg =
972 (u32) priv->dbell_ring.virt +
973 (in_be32(&priv->msg_regs->dqdpar) & 0xfff);
974 struct rio_dbell *dbell;
975 int found = 0;
976
977 pr_debug
978 ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n",
979 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
980
981 list_for_each_entry(dbell, &port->dbells, node) {
982 if ((dbell->res->start <= DBELL_INF(dmsg)) &&
983 (dbell->res->end >= DBELL_INF(dmsg))) {
984 found = 1;
985 break;
986 }
987 }
988 if (found) {
989 dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg),
990 DBELL_INF(dmsg));
991 } else {
992 pr_debug
993 ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n",
994 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg));
995 }
996 setbits32(&priv->msg_regs->dmr, DOORBELL_DMR_DI);
997 out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_DIQI);
998 }
999
1000 out:
1001 return IRQ_HANDLED;
1002 }
1003
1004 /**
1005 * fsl_rio_doorbell_init - MPC85xx doorbell interface init
1006 * @mport: Master port implementing the inbound doorbell unit
1007 *
1008 * Initializes doorbell unit hardware and inbound DMA buffer
1009 * ring. Called from fsl_rio_setup(). Returns %0 on success
1010 * or %-ENOMEM on failure.
1011 */
1012 static int fsl_rio_doorbell_init(struct rio_mport *mport)
1013 {
1014 struct rio_priv *priv = mport->priv;
1015 int rc = 0;
1016
1017 /* Map outbound doorbell window immediately after maintenance window */
1018 priv->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE,
1019 RIO_DBELL_WIN_SIZE);
1020 if (!priv->dbell_win) {
1021 printk(KERN_ERR
1022 "RIO: unable to map outbound doorbell window\n");
1023 rc = -ENOMEM;
1024 goto out;
1025 }
1026
1027 /* Initialize inbound doorbells */
1028 priv->dbell_ring.virt = dma_alloc_coherent(priv->dev, 512 *
1029 DOORBELL_MESSAGE_SIZE, &priv->dbell_ring.phys, GFP_KERNEL);
1030 if (!priv->dbell_ring.virt) {
1031 printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
1032 rc = -ENOMEM;
1033 iounmap(priv->dbell_win);
1034 goto out;
1035 }
1036
1037 /* Point dequeue/enqueue pointers at first entry in ring */
1038 out_be32(&priv->msg_regs->dqdpar, (u32) priv->dbell_ring.phys);
1039 out_be32(&priv->msg_regs->dqepar, (u32) priv->dbell_ring.phys);
1040
1041 /* Clear interrupt status */
1042 out_be32(&priv->msg_regs->dsr, 0x00000091);
1043
1044 /* Hook up doorbell handler */
1045 rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0,
1046 "dbell_rx", (void *)mport);
1047 if (rc < 0) {
1048 iounmap(priv->dbell_win);
1049 dma_free_coherent(priv->dev, 512 * DOORBELL_MESSAGE_SIZE,
1050 priv->dbell_ring.virt, priv->dbell_ring.phys);
1051 printk(KERN_ERR
1052 "MPC85xx RIO: unable to request inbound doorbell irq");
1053 goto out;
1054 }
1055
1056 /* Configure doorbells for snooping, 512 entries, and enable */
1057 out_be32(&priv->msg_regs->dmr, 0x00108161);
1058
1059 out:
1060 return rc;
1061 }
1062
1063 /**
1064 * fsl_rio_port_write_handler - MPC85xx port write interrupt handler
1065 * @irq: Linux interrupt number
1066 * @dev_instance: Pointer to interrupt-specific data
1067 *
1068 * Handles port write interrupts. Parses a list of registered
1069 * port write event handlers and executes a matching event handler.
1070 */
1071 static irqreturn_t
1072 fsl_rio_port_write_handler(int irq, void *dev_instance)
1073 {
1074 u32 ipwmr, ipwsr;
1075 struct rio_mport *port = (struct rio_mport *)dev_instance;
1076 struct rio_priv *priv = port->priv;
1077 u32 epwisr, tmp;
1078
1079 epwisr = in_be32(priv->regs_win + RIO_EPWISR);
1080 if (!(epwisr & RIO_EPWISR_PW))
1081 goto pw_done;
1082
1083 ipwmr = in_be32(&priv->msg_regs->pwmr);
1084 ipwsr = in_be32(&priv->msg_regs->pwsr);
1085
1086 #ifdef DEBUG_PW
1087 pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr);
1088 if (ipwsr & RIO_IPWSR_QF)
1089 pr_debug(" QF");
1090 if (ipwsr & RIO_IPWSR_TE)
1091 pr_debug(" TE");
1092 if (ipwsr & RIO_IPWSR_QFI)
1093 pr_debug(" QFI");
1094 if (ipwsr & RIO_IPWSR_PWD)
1095 pr_debug(" PWD");
1096 if (ipwsr & RIO_IPWSR_PWB)
1097 pr_debug(" PWB");
1098 pr_debug(" )\n");
1099 #endif
1100 /* Schedule deferred processing if PW was received */
1101 if (ipwsr & RIO_IPWSR_QFI) {
1102 /* Save PW message (if there is room in FIFO),
1103 * otherwise discard it.
1104 */
1105 if (kfifo_avail(&priv->pw_fifo) >= RIO_PW_MSG_SIZE) {
1106 priv->port_write_msg.msg_count++;
1107 kfifo_in(&priv->pw_fifo, priv->port_write_msg.virt,
1108 RIO_PW_MSG_SIZE);
1109 } else {
1110 priv->port_write_msg.discard_count++;
1111 pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n",
1112 priv->port_write_msg.discard_count);
1113 }
1114 /* Clear interrupt and issue Clear Queue command. This allows
1115 * another port-write to be received.
1116 */
1117 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_QFI);
1118 out_be32(&priv->msg_regs->pwmr, ipwmr | RIO_IPWMR_CQ);
1119
1120 schedule_work(&priv->pw_work);
1121 }
1122
1123 if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) {
1124 priv->port_write_msg.err_count++;
1125 pr_debug("RIO: Port-Write Transaction Err (%d)\n",
1126 priv->port_write_msg.err_count);
1127 /* Clear Transaction Error: port-write controller should be
1128 * disabled when clearing this error
1129 */
1130 out_be32(&priv->msg_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE);
1131 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_TE);
1132 out_be32(&priv->msg_regs->pwmr, ipwmr);
1133 }
1134
1135 if (ipwsr & RIO_IPWSR_PWD) {
1136 priv->port_write_msg.discard_count++;
1137 pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n",
1138 priv->port_write_msg.discard_count);
1139 out_be32(&priv->msg_regs->pwsr, RIO_IPWSR_PWD);
1140 }
1141
1142 pw_done:
1143 if (epwisr & RIO_EPWISR_PINT) {
1144 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
1145 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
1146 out_be32(priv->regs_win + RIO_LTLEDCSR, 0);
1147 }
1148
1149 return IRQ_HANDLED;
1150 }
1151
1152 static void fsl_pw_dpc(struct work_struct *work)
1153 {
1154 struct rio_priv *priv = container_of(work, struct rio_priv, pw_work);
1155 unsigned long flags;
1156 u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)];
1157
1158 /*
1159 * Process port-write messages
1160 */
1161 spin_lock_irqsave(&priv->pw_fifo_lock, flags);
1162 while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer,
1163 RIO_PW_MSG_SIZE)) {
1164 /* Process one message */
1165 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
1166 #ifdef DEBUG_PW
1167 {
1168 u32 i;
1169 pr_debug("%s : Port-Write Message:", __func__);
1170 for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) {
1171 if ((i%4) == 0)
1172 pr_debug("\n0x%02x: 0x%08x", i*4,
1173 msg_buffer[i]);
1174 else
1175 pr_debug(" 0x%08x", msg_buffer[i]);
1176 }
1177 pr_debug("\n");
1178 }
1179 #endif
1180 /* Pass the port-write message to RIO core for processing */
1181 rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer);
1182 spin_lock_irqsave(&priv->pw_fifo_lock, flags);
1183 }
1184 spin_unlock_irqrestore(&priv->pw_fifo_lock, flags);
1185 }
1186
1187 /**
1188 * fsl_rio_pw_enable - enable/disable port-write interface init
1189 * @mport: Master port implementing the port write unit
1190 * @enable: 1=enable; 0=disable port-write message handling
1191 */
1192 static int fsl_rio_pw_enable(struct rio_mport *mport, int enable)
1193 {
1194 struct rio_priv *priv = mport->priv;
1195 u32 rval;
1196
1197 rval = in_be32(&priv->msg_regs->pwmr);
1198
1199 if (enable)
1200 rval |= RIO_IPWMR_PWE;
1201 else
1202 rval &= ~RIO_IPWMR_PWE;
1203
1204 out_be32(&priv->msg_regs->pwmr, rval);
1205
1206 return 0;
1207 }
1208
1209 /**
1210 * fsl_rio_port_write_init - MPC85xx port write interface init
1211 * @mport: Master port implementing the port write unit
1212 *
1213 * Initializes port write unit hardware and DMA buffer
1214 * ring. Called from fsl_rio_setup(). Returns %0 on success
1215 * or %-ENOMEM on failure.
1216 */
1217 static int fsl_rio_port_write_init(struct rio_mport *mport)
1218 {
1219 struct rio_priv *priv = mport->priv;
1220 int rc = 0;
1221
1222 /* Following configurations require a disabled port write controller */
1223 out_be32(&priv->msg_regs->pwmr,
1224 in_be32(&priv->msg_regs->pwmr) & ~RIO_IPWMR_PWE);
1225
1226 /* Initialize port write */
1227 priv->port_write_msg.virt = dma_alloc_coherent(priv->dev,
1228 RIO_PW_MSG_SIZE,
1229 &priv->port_write_msg.phys, GFP_KERNEL);
1230 if (!priv->port_write_msg.virt) {
1231 pr_err("RIO: unable allocate port write queue\n");
1232 return -ENOMEM;
1233 }
1234
1235 priv->port_write_msg.err_count = 0;
1236 priv->port_write_msg.discard_count = 0;
1237
1238 /* Point dequeue/enqueue pointers at first entry */
1239 out_be32(&priv->msg_regs->epwqbar, 0);
1240 out_be32(&priv->msg_regs->pwqbar, (u32) priv->port_write_msg.phys);
1241
1242 pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n",
1243 in_be32(&priv->msg_regs->epwqbar),
1244 in_be32(&priv->msg_regs->pwqbar));
1245
1246 /* Clear interrupt status IPWSR */
1247 out_be32(&priv->msg_regs->pwsr,
1248 (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD));
1249
1250 /* Configure port write contoller for snooping enable all reporting,
1251 clear queue full */
1252 out_be32(&priv->msg_regs->pwmr,
1253 RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ);
1254
1255
1256 /* Hook up port-write handler */
1257 rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler, 0,
1258 "port-write", (void *)mport);
1259 if (rc < 0) {
1260 pr_err("MPC85xx RIO: unable to request inbound doorbell irq");
1261 goto err_out;
1262 }
1263
1264 INIT_WORK(&priv->pw_work, fsl_pw_dpc);
1265 spin_lock_init(&priv->pw_fifo_lock);
1266 if (kfifo_alloc(&priv->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
1267 pr_err("FIFO allocation failed\n");
1268 rc = -ENOMEM;
1269 goto err_out_irq;
1270 }
1271
1272 pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n",
1273 in_be32(&priv->msg_regs->pwmr),
1274 in_be32(&priv->msg_regs->pwsr));
1275
1276 return rc;
1277
1278 err_out_irq:
1279 free_irq(IRQ_RIO_PW(mport), (void *)mport);
1280 err_out:
1281 dma_free_coherent(priv->dev, RIO_PW_MSG_SIZE,
1282 priv->port_write_msg.virt,
1283 priv->port_write_msg.phys);
1284 return rc;
1285 }
1286
1287 static inline void fsl_rio_info(struct device *dev, u32 ccsr)
1288 {
1289 const char *str;
1290 if (ccsr & 1) {
1291 /* Serial phy */
1292 switch (ccsr >> 30) {
1293 case 0:
1294 str = "1";
1295 break;
1296 case 1:
1297 str = "4";
1298 break;
1299 default:
1300 str = "Unknown";
1301 break;
1302 }
1303 dev_info(dev, "Hardware port width: %s\n", str);
1304
1305 switch ((ccsr >> 27) & 7) {
1306 case 0:
1307 str = "Single-lane 0";
1308 break;
1309 case 1:
1310 str = "Single-lane 2";
1311 break;
1312 case 2:
1313 str = "Four-lane";
1314 break;
1315 default:
1316 str = "Unknown";
1317 break;
1318 }
1319 dev_info(dev, "Training connection status: %s\n", str);
1320 } else {
1321 /* Parallel phy */
1322 if (!(ccsr & 0x80000000))
1323 dev_info(dev, "Output port operating in 8-bit mode\n");
1324 if (!(ccsr & 0x08000000))
1325 dev_info(dev, "Input port operating in 8-bit mode\n");
1326 }
1327 }
1328
1329 /**
1330 * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
1331 * @dev: platform_device pointer
1332 *
1333 * Initializes MPC85xx RapidIO hardware interface, configures
1334 * master port with system-specific info, and registers the
1335 * master port with the RapidIO subsystem.
1336 */
1337 int fsl_rio_setup(struct platform_device *dev)
1338 {
1339 struct rio_ops *ops;
1340 struct rio_mport *port;
1341 struct rio_priv *priv;
1342 int rc = 0;
1343 const u32 *dt_range, *cell;
1344 struct resource regs;
1345 int rlen;
1346 u32 ccsr;
1347 u64 law_start, law_size;
1348 int paw, aw, sw;
1349
1350 if (!dev->dev.of_node) {
1351 dev_err(&dev->dev, "Device OF-Node is NULL");
1352 return -EFAULT;
1353 }
1354
1355 rc = of_address_to_resource(dev->dev.of_node, 0, &regs);
1356 if (rc) {
1357 dev_err(&dev->dev, "Can't get %s property 'reg'\n",
1358 dev->dev.of_node->full_name);
1359 return -EFAULT;
1360 }
1361 dev_info(&dev->dev, "Of-device full name %s\n", dev->dev.of_node->full_name);
1362 dev_info(&dev->dev, "Regs: %pR\n", &regs);
1363
1364 dt_range = of_get_property(dev->dev.of_node, "ranges", &rlen);
1365 if (!dt_range) {
1366 dev_err(&dev->dev, "Can't get %s property 'ranges'\n",
1367 dev->dev.of_node->full_name);
1368 return -EFAULT;
1369 }
1370
1371 /* Get node address wide */
1372 cell = of_get_property(dev->dev.of_node, "#address-cells", NULL);
1373 if (cell)
1374 aw = *cell;
1375 else
1376 aw = of_n_addr_cells(dev->dev.of_node);
1377 /* Get node size wide */
1378 cell = of_get_property(dev->dev.of_node, "#size-cells", NULL);
1379 if (cell)
1380 sw = *cell;
1381 else
1382 sw = of_n_size_cells(dev->dev.of_node);
1383 /* Get parent address wide wide */
1384 paw = of_n_addr_cells(dev->dev.of_node);
1385
1386 law_start = of_read_number(dt_range + aw, paw);
1387 law_size = of_read_number(dt_range + aw + paw, sw);
1388
1389 dev_info(&dev->dev, "LAW start 0x%016llx, size 0x%016llx.\n",
1390 law_start, law_size);
1391
1392 ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
1393 if (!ops) {
1394 rc = -ENOMEM;
1395 goto err_ops;
1396 }
1397 ops->lcread = fsl_local_config_read;
1398 ops->lcwrite = fsl_local_config_write;
1399 ops->cread = fsl_rio_config_read;
1400 ops->cwrite = fsl_rio_config_write;
1401 ops->dsend = fsl_rio_doorbell_send;
1402 ops->pwenable = fsl_rio_pw_enable;
1403 ops->open_outb_mbox = fsl_open_outb_mbox;
1404 ops->open_inb_mbox = fsl_open_inb_mbox;
1405 ops->close_outb_mbox = fsl_close_outb_mbox;
1406 ops->close_inb_mbox = fsl_close_inb_mbox;
1407 ops->add_outb_message = fsl_add_outb_message;
1408 ops->add_inb_buffer = fsl_add_inb_buffer;
1409 ops->get_inb_message = fsl_get_inb_message;
1410
1411 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
1412 if (!port) {
1413 rc = -ENOMEM;
1414 goto err_port;
1415 }
1416 port->index = 0;
1417
1418 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
1419 if (!priv) {
1420 printk(KERN_ERR "Can't alloc memory for 'priv'\n");
1421 rc = -ENOMEM;
1422 goto err_priv;
1423 }
1424
1425 INIT_LIST_HEAD(&port->dbells);
1426 port->iores.start = law_start;
1427 port->iores.end = law_start + law_size - 1;
1428 port->iores.flags = IORESOURCE_MEM;
1429 port->iores.name = "rio_io_win";
1430
1431 if (request_resource(&iomem_resource, &port->iores) < 0) {
1432 dev_err(&dev->dev, "RIO: Error requesting master port region"
1433 " 0x%016llx-0x%016llx\n",
1434 (u64)port->iores.start, (u64)port->iores.end);
1435 rc = -ENOMEM;
1436 goto err_res;
1437 }
1438
1439 priv->pwirq = irq_of_parse_and_map(dev->dev.of_node, 0);
1440 priv->bellirq = irq_of_parse_and_map(dev->dev.of_node, 2);
1441 priv->txirq = irq_of_parse_and_map(dev->dev.of_node, 3);
1442 priv->rxirq = irq_of_parse_and_map(dev->dev.of_node, 4);
1443 dev_info(&dev->dev, "pwirq: %d, bellirq: %d, txirq: %d, rxirq %d\n",
1444 priv->pwirq, priv->bellirq, priv->txirq, priv->rxirq);
1445
1446 rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
1447 rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
1448 rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
1449 strcpy(port->name, "RIO0 mport");
1450
1451 priv->dev = &dev->dev;
1452
1453 port->ops = ops;
1454 port->priv = priv;
1455 port->phys_efptr = 0x100;
1456
1457 priv->regs_win = ioremap(regs.start, regs.end - regs.start + 1);
1458 rio_regs_win = priv->regs_win;
1459
1460 /* Probe the master port phy type */
1461 ccsr = in_be32(priv->regs_win + RIO_CCSR);
1462 port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL;
1463 dev_info(&dev->dev, "RapidIO PHY type: %s\n",
1464 (port->phy_type == RIO_PHY_PARALLEL) ? "parallel" :
1465 ((port->phy_type == RIO_PHY_SERIAL) ? "serial" :
1466 "unknown"));
1467 /* Checking the port training status */
1468 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
1469 dev_err(&dev->dev, "Port is not ready. "
1470 "Try to restart connection...\n");
1471 switch (port->phy_type) {
1472 case RIO_PHY_SERIAL:
1473 /* Disable ports */
1474 out_be32(priv->regs_win + RIO_CCSR, 0);
1475 /* Set 1x lane */
1476 setbits32(priv->regs_win + RIO_CCSR, 0x02000000);
1477 /* Enable ports */
1478 setbits32(priv->regs_win + RIO_CCSR, 0x00600000);
1479 break;
1480 case RIO_PHY_PARALLEL:
1481 /* Disable ports */
1482 out_be32(priv->regs_win + RIO_CCSR, 0x22000000);
1483 /* Enable ports */
1484 out_be32(priv->regs_win + RIO_CCSR, 0x44000000);
1485 break;
1486 }
1487 msleep(100);
1488 if (in_be32((priv->regs_win + RIO_ESCSR)) & 1) {
1489 dev_err(&dev->dev, "Port restart failed.\n");
1490 rc = -ENOLINK;
1491 goto err;
1492 }
1493 dev_info(&dev->dev, "Port restart success!\n");
1494 }
1495 fsl_rio_info(&dev->dev, ccsr);
1496
1497 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
1498 & RIO_PEF_CTLS) >> 4;
1499 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
1500 port->sys_size ? 65536 : 256);
1501
1502 if (rio_register_mport(port))
1503 goto err;
1504
1505 if (port->host_deviceid >= 0)
1506 out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST |
1507 RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
1508 else
1509 out_be32(priv->regs_win + RIO_GCCSR, 0x00000000);
1510
1511 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
1512 + RIO_ATMU_REGS_OFFSET);
1513 priv->maint_atmu_regs = priv->atmu_regs + 1;
1514 priv->dbell_atmu_regs = priv->atmu_regs + 2;
1515 priv->msg_regs = (struct rio_msg_regs *)(priv->regs_win +
1516 ((port->phy_type == RIO_PHY_SERIAL) ?
1517 RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET));
1518
1519 /* Set to receive any dist ID for serial RapidIO controller. */
1520 if (port->phy_type == RIO_PHY_SERIAL)
1521 out_be32((priv->regs_win + RIO_ISR_AACR), RIO_ISR_AACR_AA);
1522
1523 /* Configure maintenance transaction window */
1524 out_be32(&priv->maint_atmu_regs->rowbar, law_start >> 12);
1525 out_be32(&priv->maint_atmu_regs->rowar,
1526 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
1527
1528 priv->maint_win = ioremap(law_start, RIO_MAINT_WIN_SIZE);
1529
1530 /* Configure outbound doorbell window */
1531 out_be32(&priv->dbell_atmu_regs->rowbar,
1532 (law_start + RIO_MAINT_WIN_SIZE) >> 12);
1533 out_be32(&priv->dbell_atmu_regs->rowar, 0x8004200b); /* 4k */
1534 fsl_rio_doorbell_init(port);
1535 fsl_rio_port_write_init(port);
1536
1537 return 0;
1538 err:
1539 iounmap(priv->regs_win);
1540 err_res:
1541 kfree(priv);
1542 err_priv:
1543 kfree(port);
1544 err_port:
1545 kfree(ops);
1546 err_ops:
1547 return rc;
1548 }
1549
1550 /* The probe function for RapidIO peer-to-peer network.
1551 */
1552 static int __devinit fsl_of_rio_rpn_probe(struct platform_device *dev)
1553 {
1554 printk(KERN_INFO "Setting up RapidIO peer-to-peer network %s\n",
1555 dev->dev.of_node->full_name);
1556
1557 return fsl_rio_setup(dev);
1558 };
1559
1560 static const struct of_device_id fsl_of_rio_rpn_ids[] = {
1561 {
1562 .compatible = "fsl,rapidio-delta",
1563 },
1564 {},
1565 };
1566
1567 static struct platform_driver fsl_of_rio_rpn_driver = {
1568 .driver = {
1569 .name = "fsl-of-rio",
1570 .owner = THIS_MODULE,
1571 .of_match_table = fsl_of_rio_rpn_ids,
1572 },
1573 .probe = fsl_of_rio_rpn_probe,
1574 };
1575
1576 static __init int fsl_of_rio_rpn_init(void)
1577 {
1578 return platform_driver_register(&fsl_of_rio_rpn_driver);
1579 }
1580
1581 subsys_initcall(fsl_of_rio_rpn_init);
Linux kernel - Deliverables
This page took 0.320599 seconds and 5 git commands to generate.