2 * arch/powerpc/kernel/mpic.c
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/irq.h>
24 #include <linux/smp.h>
25 #include <linux/interrupt.h>
26 #include <linux/bootmem.h>
27 #include <linux/spinlock.h>
28 #include <linux/pci.h>
30 #include <asm/ptrace.h>
31 #include <asm/signal.h>
33 #include <asm/pgtable.h>
35 #include <asm/machdep.h>
42 #define DBG(fmt...) printk(fmt)
47 static struct mpic
*mpics
;
48 static struct mpic
*mpic_primary
;
49 static DEFINE_SPINLOCK(mpic_lock
);
51 #ifdef CONFIG_PPC32 /* XXX for now */
52 #ifdef CONFIG_IRQ_ALL_CPUS
53 #define distribute_irqs (1)
55 #define distribute_irqs (0)
59 #ifdef CONFIG_MPIC_WEIRD
60 static u32 mpic_infos
[][MPIC_IDX_END
] = {
61 [0] = { /* Original OpenPIC compatible MPIC */
64 MPIC_GREG_GLOBAL_CONF_0
,
66 MPIC_GREG_IPI_VECTOR_PRI_0
,
73 MPIC_TIMER_CURRENT_CNT
,
75 MPIC_TIMER_VECTOR_PRI
,
76 MPIC_TIMER_DESTINATION
,
80 MPIC_CPU_IPI_DISPATCH_0
,
81 MPIC_CPU_IPI_DISPATCH_STRIDE
,
82 MPIC_CPU_CURRENT_TASK_PRI
,
90 MPIC_VECPRI_VECTOR_MASK
,
91 MPIC_VECPRI_POLARITY_POSITIVE
,
92 MPIC_VECPRI_POLARITY_NEGATIVE
,
93 MPIC_VECPRI_SENSE_LEVEL
,
94 MPIC_VECPRI_SENSE_EDGE
,
95 MPIC_VECPRI_POLARITY_MASK
,
96 MPIC_VECPRI_SENSE_MASK
,
99 [1] = { /* Tsi108/109 PIC */
101 TSI108_GREG_FEATURE_0
,
102 TSI108_GREG_GLOBAL_CONF_0
,
103 TSI108_GREG_VENDOR_ID
,
104 TSI108_GREG_IPI_VECTOR_PRI_0
,
105 TSI108_GREG_IPI_STRIDE
,
106 TSI108_GREG_SPURIOUS
,
107 TSI108_GREG_TIMER_FREQ
,
111 TSI108_TIMER_CURRENT_CNT
,
112 TSI108_TIMER_BASE_CNT
,
113 TSI108_TIMER_VECTOR_PRI
,
114 TSI108_TIMER_DESTINATION
,
118 TSI108_CPU_IPI_DISPATCH_0
,
119 TSI108_CPU_IPI_DISPATCH_STRIDE
,
120 TSI108_CPU_CURRENT_TASK_PRI
,
127 TSI108_IRQ_VECTOR_PRI
,
128 TSI108_VECPRI_VECTOR_MASK
,
129 TSI108_VECPRI_POLARITY_POSITIVE
,
130 TSI108_VECPRI_POLARITY_NEGATIVE
,
131 TSI108_VECPRI_SENSE_LEVEL
,
132 TSI108_VECPRI_SENSE_EDGE
,
133 TSI108_VECPRI_POLARITY_MASK
,
134 TSI108_VECPRI_SENSE_MASK
,
135 TSI108_IRQ_DESTINATION
139 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
141 #else /* CONFIG_MPIC_WEIRD */
143 #define MPIC_INFO(name) MPIC_##name
145 #endif /* CONFIG_MPIC_WEIRD */
148 * Register accessor functions
152 static inline u32
_mpic_read(enum mpic_reg_type type
,
153 struct mpic_reg_bank
*rb
,
157 #ifdef CONFIG_PPC_DCR
158 case mpic_access_dcr
:
159 return dcr_read(rb
->dhost
,
160 rb
->dbase
+ reg
+ rb
->doff
);
162 case mpic_access_mmio_be
:
163 return in_be32(rb
->base
+ (reg
>> 2));
164 case mpic_access_mmio_le
:
166 return in_le32(rb
->base
+ (reg
>> 2));
170 static inline void _mpic_write(enum mpic_reg_type type
,
171 struct mpic_reg_bank
*rb
,
172 unsigned int reg
, u32 value
)
175 #ifdef CONFIG_PPC_DCR
176 case mpic_access_dcr
:
177 return dcr_write(rb
->dhost
,
178 rb
->dbase
+ reg
+ rb
->doff
, value
);
180 case mpic_access_mmio_be
:
181 return out_be32(rb
->base
+ (reg
>> 2), value
);
182 case mpic_access_mmio_le
:
184 return out_le32(rb
->base
+ (reg
>> 2), value
);
188 static inline u32
_mpic_ipi_read(struct mpic
*mpic
, unsigned int ipi
)
190 enum mpic_reg_type type
= mpic
->reg_type
;
191 unsigned int offset
= MPIC_INFO(GREG_IPI_VECTOR_PRI_0
) +
192 (ipi
* MPIC_INFO(GREG_IPI_STRIDE
));
194 if ((mpic
->flags
& MPIC_BROKEN_IPI
) && type
== mpic_access_mmio_le
)
195 type
= mpic_access_mmio_be
;
196 return _mpic_read(type
, &mpic
->gregs
, offset
);
199 static inline void _mpic_ipi_write(struct mpic
*mpic
, unsigned int ipi
, u32 value
)
201 unsigned int offset
= MPIC_INFO(GREG_IPI_VECTOR_PRI_0
) +
202 (ipi
* MPIC_INFO(GREG_IPI_STRIDE
));
204 _mpic_write(mpic
->reg_type
, &mpic
->gregs
, offset
, value
);
207 static inline u32
_mpic_cpu_read(struct mpic
*mpic
, unsigned int reg
)
209 unsigned int cpu
= 0;
211 if (mpic
->flags
& MPIC_PRIMARY
)
212 cpu
= hard_smp_processor_id();
213 return _mpic_read(mpic
->reg_type
, &mpic
->cpuregs
[cpu
], reg
);
216 static inline void _mpic_cpu_write(struct mpic
*mpic
, unsigned int reg
, u32 value
)
218 unsigned int cpu
= 0;
220 if (mpic
->flags
& MPIC_PRIMARY
)
221 cpu
= hard_smp_processor_id();
223 _mpic_write(mpic
->reg_type
, &mpic
->cpuregs
[cpu
], reg
, value
);
226 static inline u32
_mpic_irq_read(struct mpic
*mpic
, unsigned int src_no
, unsigned int reg
)
228 unsigned int isu
= src_no
>> mpic
->isu_shift
;
229 unsigned int idx
= src_no
& mpic
->isu_mask
;
231 return _mpic_read(mpic
->reg_type
, &mpic
->isus
[isu
],
232 reg
+ (idx
* MPIC_INFO(IRQ_STRIDE
)));
235 static inline void _mpic_irq_write(struct mpic
*mpic
, unsigned int src_no
,
236 unsigned int reg
, u32 value
)
238 unsigned int isu
= src_no
>> mpic
->isu_shift
;
239 unsigned int idx
= src_no
& mpic
->isu_mask
;
241 _mpic_write(mpic
->reg_type
, &mpic
->isus
[isu
],
242 reg
+ (idx
* MPIC_INFO(IRQ_STRIDE
)), value
);
245 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
246 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
247 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
248 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
249 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
250 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
251 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
252 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
256 * Low level utility functions
260 static void _mpic_map_mmio(struct mpic
*mpic
, unsigned long phys_addr
,
261 struct mpic_reg_bank
*rb
, unsigned int offset
,
264 rb
->base
= ioremap(phys_addr
+ offset
, size
);
265 BUG_ON(rb
->base
== NULL
);
268 #ifdef CONFIG_PPC_DCR
269 static void _mpic_map_dcr(struct mpic
*mpic
, struct mpic_reg_bank
*rb
,
270 unsigned int offset
, unsigned int size
)
272 rb
->dbase
= mpic
->dcr_base
;
274 rb
->dhost
= dcr_map(mpic
->of_node
, rb
->dbase
+ rb
->doff
, size
);
275 BUG_ON(!DCR_MAP_OK(rb
->dhost
));
278 static inline void mpic_map(struct mpic
*mpic
, unsigned long phys_addr
,
279 struct mpic_reg_bank
*rb
, unsigned int offset
,
282 if (mpic
->flags
& MPIC_USES_DCR
)
283 _mpic_map_dcr(mpic
, rb
, offset
, size
);
285 _mpic_map_mmio(mpic
, phys_addr
, rb
, offset
, size
);
287 #else /* CONFIG_PPC_DCR */
288 #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
289 #endif /* !CONFIG_PPC_DCR */
293 /* Check if we have one of those nice broken MPICs with a flipped endian on
294 * reads from IPI registers
296 static void __init
mpic_test_broken_ipi(struct mpic
*mpic
)
300 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_IPI_VECTOR_PRI_0
), MPIC_VECPRI_MASK
);
301 r
= mpic_read(mpic
->gregs
, MPIC_INFO(GREG_IPI_VECTOR_PRI_0
));
303 if (r
== le32_to_cpu(MPIC_VECPRI_MASK
)) {
304 printk(KERN_INFO
"mpic: Detected reversed IPI registers\n");
305 mpic
->flags
|= MPIC_BROKEN_IPI
;
309 #ifdef CONFIG_MPIC_U3_HT_IRQS
311 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
312 * to force the edge setting on the MPIC and do the ack workaround.
314 static inline int mpic_is_ht_interrupt(struct mpic
*mpic
, unsigned int source
)
316 if (source
>= 128 || !mpic
->fixups
)
318 return mpic
->fixups
[source
].base
!= NULL
;
322 static inline void mpic_ht_end_irq(struct mpic
*mpic
, unsigned int source
)
324 struct mpic_irq_fixup
*fixup
= &mpic
->fixups
[source
];
326 if (fixup
->applebase
) {
327 unsigned int soff
= (fixup
->index
>> 3) & ~3;
328 unsigned int mask
= 1U << (fixup
->index
& 0x1f);
329 writel(mask
, fixup
->applebase
+ soff
);
331 spin_lock(&mpic
->fixup_lock
);
332 writeb(0x11 + 2 * fixup
->index
, fixup
->base
+ 2);
333 writel(fixup
->data
, fixup
->base
+ 4);
334 spin_unlock(&mpic
->fixup_lock
);
338 static void mpic_startup_ht_interrupt(struct mpic
*mpic
, unsigned int source
,
339 unsigned int irqflags
)
341 struct mpic_irq_fixup
*fixup
= &mpic
->fixups
[source
];
345 if (fixup
->base
== NULL
)
348 DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
349 source
, irqflags
, fixup
->index
);
350 spin_lock_irqsave(&mpic
->fixup_lock
, flags
);
351 /* Enable and configure */
352 writeb(0x10 + 2 * fixup
->index
, fixup
->base
+ 2);
353 tmp
= readl(fixup
->base
+ 4);
355 if (irqflags
& IRQ_LEVEL
)
357 writel(tmp
, fixup
->base
+ 4);
358 spin_unlock_irqrestore(&mpic
->fixup_lock
, flags
);
361 /* use the lowest bit inverted to the actual HW,
362 * set if this fixup was enabled, clear otherwise */
363 mpic
->save_data
[source
].fixup_data
= tmp
| 1;
367 static void mpic_shutdown_ht_interrupt(struct mpic
*mpic
, unsigned int source
,
368 unsigned int irqflags
)
370 struct mpic_irq_fixup
*fixup
= &mpic
->fixups
[source
];
374 if (fixup
->base
== NULL
)
377 DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source
, irqflags
);
380 spin_lock_irqsave(&mpic
->fixup_lock
, flags
);
381 writeb(0x10 + 2 * fixup
->index
, fixup
->base
+ 2);
382 tmp
= readl(fixup
->base
+ 4);
384 writel(tmp
, fixup
->base
+ 4);
385 spin_unlock_irqrestore(&mpic
->fixup_lock
, flags
);
388 /* use the lowest bit inverted to the actual HW,
389 * set if this fixup was enabled, clear otherwise */
390 mpic
->save_data
[source
].fixup_data
= tmp
& ~1;
394 #ifdef CONFIG_PCI_MSI
395 static void __init
mpic_scan_ht_msi(struct mpic
*mpic
, u8 __iomem
*devbase
,
402 for (pos
= readb(devbase
+ PCI_CAPABILITY_LIST
); pos
!= 0;
403 pos
= readb(devbase
+ pos
+ PCI_CAP_LIST_NEXT
)) {
404 u8 id
= readb(devbase
+ pos
+ PCI_CAP_LIST_ID
);
405 if (id
== PCI_CAP_ID_HT
) {
406 id
= readb(devbase
+ pos
+ 3);
407 if ((id
& HT_5BIT_CAP_MASK
) == HT_CAPTYPE_MSI_MAPPING
)
415 base
= devbase
+ pos
;
417 flags
= readb(base
+ HT_MSI_FLAGS
);
418 if (!(flags
& HT_MSI_FLAGS_FIXED
)) {
419 addr
= readl(base
+ HT_MSI_ADDR_LO
) & HT_MSI_ADDR_LO_MASK
;
420 addr
= addr
| ((u64
)readl(base
+ HT_MSI_ADDR_HI
) << 32);
423 printk(KERN_DEBUG
"mpic: - HT:%02x.%x %s MSI mapping found @ 0x%lx\n",
424 PCI_SLOT(devfn
), PCI_FUNC(devfn
),
425 flags
& HT_MSI_FLAGS_ENABLE
? "enabled" : "disabled", addr
);
427 if (!(flags
& HT_MSI_FLAGS_ENABLE
))
428 writeb(flags
| HT_MSI_FLAGS_ENABLE
, base
+ HT_MSI_FLAGS
);
431 static void __init
mpic_scan_ht_msi(struct mpic
*mpic
, u8 __iomem
*devbase
,
438 static void __init
mpic_scan_ht_pic(struct mpic
*mpic
, u8 __iomem
*devbase
,
439 unsigned int devfn
, u32 vdid
)
446 for (pos
= readb(devbase
+ PCI_CAPABILITY_LIST
); pos
!= 0;
447 pos
= readb(devbase
+ pos
+ PCI_CAP_LIST_NEXT
)) {
448 u8 id
= readb(devbase
+ pos
+ PCI_CAP_LIST_ID
);
449 if (id
== PCI_CAP_ID_HT
) {
450 id
= readb(devbase
+ pos
+ 3);
451 if ((id
& HT_5BIT_CAP_MASK
) == HT_CAPTYPE_IRQ
)
458 base
= devbase
+ pos
;
459 writeb(0x01, base
+ 2);
460 n
= (readl(base
+ 4) >> 16) & 0xff;
462 printk(KERN_INFO
"mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
464 devfn
>> 3, devfn
& 0x7, pos
, vdid
& 0xffff, vdid
>> 16, n
+ 1);
466 for (i
= 0; i
<= n
; i
++) {
467 writeb(0x10 + 2 * i
, base
+ 2);
468 tmp
= readl(base
+ 4);
469 irq
= (tmp
>> 16) & 0xff;
470 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i
, irq
, tmp
);
471 /* mask it , will be unmasked later */
473 writel(tmp
, base
+ 4);
474 mpic
->fixups
[irq
].index
= i
;
475 mpic
->fixups
[irq
].base
= base
;
476 /* Apple HT PIC has a non-standard way of doing EOIs */
477 if ((vdid
& 0xffff) == 0x106b)
478 mpic
->fixups
[irq
].applebase
= devbase
+ 0x60;
480 mpic
->fixups
[irq
].applebase
= NULL
;
481 writeb(0x11 + 2 * i
, base
+ 2);
482 mpic
->fixups
[irq
].data
= readl(base
+ 4) | 0x80000000;
487 static void __init
mpic_scan_ht_pics(struct mpic
*mpic
)
490 u8 __iomem
*cfgspace
;
492 printk(KERN_INFO
"mpic: Setting up HT PICs workarounds for U3/U4\n");
494 /* Allocate fixups array */
495 mpic
->fixups
= alloc_bootmem(128 * sizeof(struct mpic_irq_fixup
));
496 BUG_ON(mpic
->fixups
== NULL
);
497 memset(mpic
->fixups
, 0, 128 * sizeof(struct mpic_irq_fixup
));
500 spin_lock_init(&mpic
->fixup_lock
);
502 /* Map U3 config space. We assume all IO-APICs are on the primary bus
503 * so we only need to map 64kB.
505 cfgspace
= ioremap(0xf2000000, 0x10000);
506 BUG_ON(cfgspace
== NULL
);
508 /* Now we scan all slots. We do a very quick scan, we read the header
509 * type, vendor ID and device ID only, that's plenty enough
511 for (devfn
= 0; devfn
< 0x100; devfn
++) {
512 u8 __iomem
*devbase
= cfgspace
+ (devfn
<< 8);
513 u8 hdr_type
= readb(devbase
+ PCI_HEADER_TYPE
);
514 u32 l
= readl(devbase
+ PCI_VENDOR_ID
);
517 DBG("devfn %x, l: %x\n", devfn
, l
);
519 /* If no device, skip */
520 if (l
== 0xffffffff || l
== 0x00000000 ||
521 l
== 0x0000ffff || l
== 0xffff0000)
523 /* Check if is supports capability lists */
524 s
= readw(devbase
+ PCI_STATUS
);
525 if (!(s
& PCI_STATUS_CAP_LIST
))
528 mpic_scan_ht_pic(mpic
, devbase
, devfn
, l
);
529 mpic_scan_ht_msi(mpic
, devbase
, devfn
);
532 /* next device, if function 0 */
533 if (PCI_FUNC(devfn
) == 0 && (hdr_type
& 0x80) == 0)
538 #else /* CONFIG_MPIC_U3_HT_IRQS */
540 static inline int mpic_is_ht_interrupt(struct mpic
*mpic
, unsigned int source
)
545 static void __init
mpic_scan_ht_pics(struct mpic
*mpic
)
549 #endif /* CONFIG_MPIC_U3_HT_IRQS */
552 #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
554 /* Find an mpic associated with a given linux interrupt */
555 static struct mpic
*mpic_find(unsigned int irq
, unsigned int *is_ipi
)
557 unsigned int src
= mpic_irq_to_hw(irq
);
560 if (irq
< NUM_ISA_INTERRUPTS
)
563 mpic
= irq_desc
[irq
].chip_data
;
566 *is_ipi
= (src
>= mpic
->ipi_vecs
[0] &&
567 src
<= mpic
->ipi_vecs
[3]);
572 /* Convert a cpu mask from logical to physical cpu numbers. */
573 static inline u32
mpic_physmask(u32 cpumask
)
578 for (i
= 0; i
< NR_CPUS
; ++i
, cpumask
>>= 1)
579 mask
|= (cpumask
& 1) << get_hard_smp_processor_id(i
);
584 /* Get the mpic structure from the IPI number */
585 static inline struct mpic
* mpic_from_ipi(unsigned int ipi
)
587 return irq_desc
[ipi
].chip_data
;
591 /* Get the mpic structure from the irq number */
592 static inline struct mpic
* mpic_from_irq(unsigned int irq
)
594 return irq_desc
[irq
].chip_data
;
598 static inline void mpic_eoi(struct mpic
*mpic
)
600 mpic_cpu_write(MPIC_INFO(CPU_EOI
), 0);
601 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI
));
605 static irqreturn_t
mpic_ipi_action(int irq
, void *dev_id
)
609 mpic
= mpic_find(irq
, NULL
);
610 smp_message_recv(mpic_irq_to_hw(irq
) - mpic
->ipi_vecs
[0]);
614 #endif /* CONFIG_SMP */
617 * Linux descriptor level callbacks
621 void mpic_unmask_irq(unsigned int irq
)
623 unsigned int loops
= 100000;
624 struct mpic
*mpic
= mpic_from_irq(irq
);
625 unsigned int src
= mpic_irq_to_hw(irq
);
627 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic
, mpic
->name
, irq
, src
);
629 mpic_irq_write(src
, MPIC_INFO(IRQ_VECTOR_PRI
),
630 mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
)) &
632 /* make sure mask gets to controller before we return to user */
635 printk(KERN_ERR
"mpic_enable_irq timeout\n");
638 } while(mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
)) & MPIC_VECPRI_MASK
);
641 void mpic_mask_irq(unsigned int irq
)
643 unsigned int loops
= 100000;
644 struct mpic
*mpic
= mpic_from_irq(irq
);
645 unsigned int src
= mpic_irq_to_hw(irq
);
647 DBG("%s: disable_irq: %d (src %d)\n", mpic
->name
, irq
, src
);
649 mpic_irq_write(src
, MPIC_INFO(IRQ_VECTOR_PRI
),
650 mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
)) |
653 /* make sure mask gets to controller before we return to user */
656 printk(KERN_ERR
"mpic_enable_irq timeout\n");
659 } while(!(mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
)) & MPIC_VECPRI_MASK
));
662 void mpic_end_irq(unsigned int irq
)
664 struct mpic
*mpic
= mpic_from_irq(irq
);
667 DBG("%s: end_irq: %d\n", mpic
->name
, irq
);
669 /* We always EOI on end_irq() even for edge interrupts since that
670 * should only lower the priority, the MPIC should have properly
671 * latched another edge interrupt coming in anyway
677 #ifdef CONFIG_MPIC_U3_HT_IRQS
679 static void mpic_unmask_ht_irq(unsigned int irq
)
681 struct mpic
*mpic
= mpic_from_irq(irq
);
682 unsigned int src
= mpic_irq_to_hw(irq
);
684 mpic_unmask_irq(irq
);
686 if (irq_desc
[irq
].status
& IRQ_LEVEL
)
687 mpic_ht_end_irq(mpic
, src
);
690 static unsigned int mpic_startup_ht_irq(unsigned int irq
)
692 struct mpic
*mpic
= mpic_from_irq(irq
);
693 unsigned int src
= mpic_irq_to_hw(irq
);
695 mpic_unmask_irq(irq
);
696 mpic_startup_ht_interrupt(mpic
, src
, irq_desc
[irq
].status
);
701 static void mpic_shutdown_ht_irq(unsigned int irq
)
703 struct mpic
*mpic
= mpic_from_irq(irq
);
704 unsigned int src
= mpic_irq_to_hw(irq
);
706 mpic_shutdown_ht_interrupt(mpic
, src
, irq_desc
[irq
].status
);
710 static void mpic_end_ht_irq(unsigned int irq
)
712 struct mpic
*mpic
= mpic_from_irq(irq
);
713 unsigned int src
= mpic_irq_to_hw(irq
);
716 DBG("%s: end_irq: %d\n", mpic
->name
, irq
);
718 /* We always EOI on end_irq() even for edge interrupts since that
719 * should only lower the priority, the MPIC should have properly
720 * latched another edge interrupt coming in anyway
723 if (irq_desc
[irq
].status
& IRQ_LEVEL
)
724 mpic_ht_end_irq(mpic
, src
);
727 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
731 static void mpic_unmask_ipi(unsigned int irq
)
733 struct mpic
*mpic
= mpic_from_ipi(irq
);
734 unsigned int src
= mpic_irq_to_hw(irq
) - mpic
->ipi_vecs
[0];
736 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic
->name
, irq
, src
);
737 mpic_ipi_write(src
, mpic_ipi_read(src
) & ~MPIC_VECPRI_MASK
);
740 static void mpic_mask_ipi(unsigned int irq
)
742 /* NEVER disable an IPI... that's just plain wrong! */
745 static void mpic_end_ipi(unsigned int irq
)
747 struct mpic
*mpic
= mpic_from_ipi(irq
);
750 * IPIs are marked IRQ_PER_CPU. This has the side effect of
751 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
752 * applying to them. We EOI them late to avoid re-entering.
753 * We mark IPI's with IRQF_DISABLED as they must run with
759 #endif /* CONFIG_SMP */
761 static void mpic_set_affinity(unsigned int irq
, cpumask_t cpumask
)
763 struct mpic
*mpic
= mpic_from_irq(irq
);
764 unsigned int src
= mpic_irq_to_hw(irq
);
768 cpus_and(tmp
, cpumask
, cpu_online_map
);
770 mpic_irq_write(src
, MPIC_INFO(IRQ_DESTINATION
),
771 mpic_physmask(cpus_addr(tmp
)[0]));
774 static unsigned int mpic_type_to_vecpri(struct mpic
*mpic
, unsigned int type
)
776 /* Now convert sense value */
777 switch(type
& IRQ_TYPE_SENSE_MASK
) {
778 case IRQ_TYPE_EDGE_RISING
:
779 return MPIC_INFO(VECPRI_SENSE_EDGE
) |
780 MPIC_INFO(VECPRI_POLARITY_POSITIVE
);
781 case IRQ_TYPE_EDGE_FALLING
:
782 case IRQ_TYPE_EDGE_BOTH
:
783 return MPIC_INFO(VECPRI_SENSE_EDGE
) |
784 MPIC_INFO(VECPRI_POLARITY_NEGATIVE
);
785 case IRQ_TYPE_LEVEL_HIGH
:
786 return MPIC_INFO(VECPRI_SENSE_LEVEL
) |
787 MPIC_INFO(VECPRI_POLARITY_POSITIVE
);
788 case IRQ_TYPE_LEVEL_LOW
:
790 return MPIC_INFO(VECPRI_SENSE_LEVEL
) |
791 MPIC_INFO(VECPRI_POLARITY_NEGATIVE
);
795 int mpic_set_irq_type(unsigned int virq
, unsigned int flow_type
)
797 struct mpic
*mpic
= mpic_from_irq(virq
);
798 unsigned int src
= mpic_irq_to_hw(virq
);
799 struct irq_desc
*desc
= get_irq_desc(virq
);
800 unsigned int vecpri
, vold
, vnew
;
802 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
803 mpic
, virq
, src
, flow_type
);
805 if (src
>= mpic
->irq_count
)
808 if (flow_type
== IRQ_TYPE_NONE
)
809 if (mpic
->senses
&& src
< mpic
->senses_count
)
810 flow_type
= mpic
->senses
[src
];
811 if (flow_type
== IRQ_TYPE_NONE
)
812 flow_type
= IRQ_TYPE_LEVEL_LOW
;
814 desc
->status
&= ~(IRQ_TYPE_SENSE_MASK
| IRQ_LEVEL
);
815 desc
->status
|= flow_type
& IRQ_TYPE_SENSE_MASK
;
816 if (flow_type
& (IRQ_TYPE_LEVEL_HIGH
| IRQ_TYPE_LEVEL_LOW
))
817 desc
->status
|= IRQ_LEVEL
;
819 if (mpic_is_ht_interrupt(mpic
, src
))
820 vecpri
= MPIC_VECPRI_POLARITY_POSITIVE
|
821 MPIC_VECPRI_SENSE_EDGE
;
823 vecpri
= mpic_type_to_vecpri(mpic
, flow_type
);
825 vold
= mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
));
826 vnew
= vold
& ~(MPIC_INFO(VECPRI_POLARITY_MASK
) |
827 MPIC_INFO(VECPRI_SENSE_MASK
));
830 mpic_irq_write(src
, MPIC_INFO(IRQ_VECTOR_PRI
), vnew
);
835 static struct irq_chip mpic_irq_chip
= {
836 .mask
= mpic_mask_irq
,
837 .unmask
= mpic_unmask_irq
,
839 .set_type
= mpic_set_irq_type
,
843 static struct irq_chip mpic_ipi_chip
= {
844 .mask
= mpic_mask_ipi
,
845 .unmask
= mpic_unmask_ipi
,
848 #endif /* CONFIG_SMP */
850 #ifdef CONFIG_MPIC_U3_HT_IRQS
851 static struct irq_chip mpic_irq_ht_chip
= {
852 .startup
= mpic_startup_ht_irq
,
853 .shutdown
= mpic_shutdown_ht_irq
,
854 .mask
= mpic_mask_irq
,
855 .unmask
= mpic_unmask_ht_irq
,
856 .eoi
= mpic_end_ht_irq
,
857 .set_type
= mpic_set_irq_type
,
859 #endif /* CONFIG_MPIC_U3_HT_IRQS */
862 static int mpic_host_match(struct irq_host
*h
, struct device_node
*node
)
864 struct mpic
*mpic
= h
->host_data
;
866 /* Exact match, unless mpic node is NULL */
867 return mpic
->of_node
== NULL
|| mpic
->of_node
== node
;
870 static int mpic_host_map(struct irq_host
*h
, unsigned int virq
,
873 struct mpic
*mpic
= h
->host_data
;
874 struct irq_chip
*chip
;
876 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq
, hw
);
878 if (hw
== mpic
->spurious_vec
)
880 if (mpic
->protected && test_bit(hw
, mpic
->protected))
884 else if (hw
>= mpic
->ipi_vecs
[0]) {
885 WARN_ON(!(mpic
->flags
& MPIC_PRIMARY
));
887 DBG("mpic: mapping as IPI\n");
888 set_irq_chip_data(virq
, mpic
);
889 set_irq_chip_and_handler(virq
, &mpic
->hc_ipi
,
893 #endif /* CONFIG_SMP */
895 if (hw
>= mpic
->irq_count
)
898 mpic_msi_reserve_hwirq(mpic
, hw
);
901 chip
= &mpic
->hc_irq
;
903 #ifdef CONFIG_MPIC_U3_HT_IRQS
904 /* Check for HT interrupts, override vecpri */
905 if (mpic_is_ht_interrupt(mpic
, hw
))
906 chip
= &mpic
->hc_ht_irq
;
907 #endif /* CONFIG_MPIC_U3_HT_IRQS */
909 DBG("mpic: mapping to irq chip @%p\n", chip
);
911 set_irq_chip_data(virq
, mpic
);
912 set_irq_chip_and_handler(virq
, chip
, handle_fasteoi_irq
);
914 /* Set default irq type */
915 set_irq_type(virq
, IRQ_TYPE_NONE
);
920 static int mpic_host_xlate(struct irq_host
*h
, struct device_node
*ct
,
921 u32
*intspec
, unsigned int intsize
,
922 irq_hw_number_t
*out_hwirq
, unsigned int *out_flags
)
925 static unsigned char map_mpic_senses
[4] = {
926 IRQ_TYPE_EDGE_RISING
,
929 IRQ_TYPE_EDGE_FALLING
,
932 *out_hwirq
= intspec
[0];
936 /* Apple invented a new race of encoding on machines with
937 * an HT APIC. They encode, among others, the index within
938 * the HT APIC. We don't care about it here since thankfully,
939 * it appears that they have the APIC already properly
940 * configured, and thus our current fixup code that reads the
941 * APIC config works fine. However, we still need to mask out
942 * bits in the specifier to make sure we only get bit 0 which
943 * is the level/edge bit (the only sense bit exposed by Apple),
944 * as their bit 1 means something else.
946 if (machine_is(powermac
))
948 *out_flags
= map_mpic_senses
[intspec
[1] & mask
];
950 *out_flags
= IRQ_TYPE_NONE
;
952 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
953 intsize
, intspec
[0], intspec
[1], *out_hwirq
, *out_flags
);
958 static struct irq_host_ops mpic_host_ops
= {
959 .match
= mpic_host_match
,
960 .map
= mpic_host_map
,
961 .xlate
= mpic_host_xlate
,
968 struct mpic
* __init
mpic_alloc(struct device_node
*node
,
969 phys_addr_t phys_addr
,
971 unsigned int isu_size
,
972 unsigned int irq_count
,
980 u64 paddr
= phys_addr
;
982 mpic
= alloc_bootmem(sizeof(struct mpic
));
986 memset(mpic
, 0, sizeof(struct mpic
));
988 mpic
->of_node
= of_node_get(node
);
990 mpic
->irqhost
= irq_alloc_host(IRQ_HOST_MAP_LINEAR
, isu_size
,
992 flags
& MPIC_LARGE_VECTORS
? 2048 : 256);
993 if (mpic
->irqhost
== NULL
) {
998 mpic
->irqhost
->host_data
= mpic
;
999 mpic
->hc_irq
= mpic_irq_chip
;
1000 mpic
->hc_irq
.typename
= name
;
1001 if (flags
& MPIC_PRIMARY
)
1002 mpic
->hc_irq
.set_affinity
= mpic_set_affinity
;
1003 #ifdef CONFIG_MPIC_U3_HT_IRQS
1004 mpic
->hc_ht_irq
= mpic_irq_ht_chip
;
1005 mpic
->hc_ht_irq
.typename
= name
;
1006 if (flags
& MPIC_PRIMARY
)
1007 mpic
->hc_ht_irq
.set_affinity
= mpic_set_affinity
;
1008 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1011 mpic
->hc_ipi
= mpic_ipi_chip
;
1012 mpic
->hc_ipi
.typename
= name
;
1013 #endif /* CONFIG_SMP */
1015 mpic
->flags
= flags
;
1016 mpic
->isu_size
= isu_size
;
1017 mpic
->irq_count
= irq_count
;
1018 mpic
->num_sources
= 0; /* so far */
1020 if (flags
& MPIC_LARGE_VECTORS
)
1025 mpic
->timer_vecs
[0] = intvec_top
- 8;
1026 mpic
->timer_vecs
[1] = intvec_top
- 7;
1027 mpic
->timer_vecs
[2] = intvec_top
- 6;
1028 mpic
->timer_vecs
[3] = intvec_top
- 5;
1029 mpic
->ipi_vecs
[0] = intvec_top
- 4;
1030 mpic
->ipi_vecs
[1] = intvec_top
- 3;
1031 mpic
->ipi_vecs
[2] = intvec_top
- 2;
1032 mpic
->ipi_vecs
[3] = intvec_top
- 1;
1033 mpic
->spurious_vec
= intvec_top
;
1035 /* Check for "big-endian" in device-tree */
1036 if (node
&& of_get_property(node
, "big-endian", NULL
) != NULL
)
1037 mpic
->flags
|= MPIC_BIG_ENDIAN
;
1039 /* Look for protected sources */
1041 unsigned int psize
, bits
, mapsize
;
1043 of_get_property(node
, "protected-sources", &psize
);
1046 bits
= intvec_top
+ 1;
1047 mapsize
= BITS_TO_LONGS(bits
) * sizeof(unsigned long);
1048 mpic
->protected = alloc_bootmem(mapsize
);
1049 BUG_ON(mpic
->protected == NULL
);
1050 memset(mpic
->protected, 0, mapsize
);
1051 for (i
= 0; i
< psize
; i
++) {
1052 if (psrc
[i
] > intvec_top
)
1054 __set_bit(psrc
[i
], mpic
->protected);
1059 #ifdef CONFIG_MPIC_WEIRD
1060 mpic
->hw_set
= mpic_infos
[MPIC_GET_REGSET(flags
)];
1063 /* default register type */
1064 mpic
->reg_type
= (flags
& MPIC_BIG_ENDIAN
) ?
1065 mpic_access_mmio_be
: mpic_access_mmio_le
;
1067 /* If no physical address is passed in, a device-node is mandatory */
1068 BUG_ON(paddr
== 0 && node
== NULL
);
1070 /* If no physical address passed in, check if it's dcr based */
1071 if (paddr
== 0 && of_get_property(node
, "dcr-reg", NULL
) != NULL
)
1072 mpic
->flags
|= MPIC_USES_DCR
;
1074 #ifdef CONFIG_PPC_DCR
1075 if (mpic
->flags
& MPIC_USES_DCR
) {
1077 dbasep
= of_get_property(node
, "dcr-reg", NULL
);
1078 BUG_ON(dbasep
== NULL
);
1079 mpic
->dcr_base
= *dbasep
;
1080 mpic
->reg_type
= mpic_access_dcr
;
1083 BUG_ON (mpic
->flags
& MPIC_USES_DCR
);
1084 #endif /* CONFIG_PPC_DCR */
1086 /* If the MPIC is not DCR based, and no physical address was passed
1087 * in, try to obtain one
1089 if (paddr
== 0 && !(mpic
->flags
& MPIC_USES_DCR
)) {
1091 reg
= of_get_property(node
, "reg", NULL
);
1092 BUG_ON(reg
== NULL
);
1093 paddr
= of_translate_address(node
, reg
);
1094 BUG_ON(paddr
== OF_BAD_ADDR
);
1097 /* Map the global registers */
1098 mpic_map(mpic
, paddr
, &mpic
->gregs
, MPIC_INFO(GREG_BASE
), 0x1000);
1099 mpic_map(mpic
, paddr
, &mpic
->tmregs
, MPIC_INFO(TIMER_BASE
), 0x1000);
1102 if (flags
& MPIC_WANTS_RESET
) {
1103 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
),
1104 mpic_read(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
))
1105 | MPIC_GREG_GCONF_RESET
);
1106 while( mpic_read(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
))
1107 & MPIC_GREG_GCONF_RESET
)
1111 /* Read feature register, calculate num CPUs and, for non-ISU
1112 * MPICs, num sources as well. On ISU MPICs, sources are counted
1115 reg
= mpic_read(mpic
->gregs
, MPIC_INFO(GREG_FEATURE_0
));
1116 mpic
->num_cpus
= ((reg
& MPIC_GREG_FEATURE_LAST_CPU_MASK
)
1117 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT
) + 1;
1119 mpic
->num_sources
= ((reg
& MPIC_GREG_FEATURE_LAST_SRC_MASK
)
1120 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT
) + 1;
1122 /* Map the per-CPU registers */
1123 for (i
= 0; i
< mpic
->num_cpus
; i
++) {
1124 mpic_map(mpic
, paddr
, &mpic
->cpuregs
[i
],
1125 MPIC_INFO(CPU_BASE
) + i
* MPIC_INFO(CPU_STRIDE
),
1129 /* Initialize main ISU if none provided */
1130 if (mpic
->isu_size
== 0) {
1131 mpic
->isu_size
= mpic
->num_sources
;
1132 mpic_map(mpic
, paddr
, &mpic
->isus
[0],
1133 MPIC_INFO(IRQ_BASE
), MPIC_INFO(IRQ_STRIDE
) * mpic
->isu_size
);
1135 mpic
->isu_shift
= 1 + __ilog2(mpic
->isu_size
- 1);
1136 mpic
->isu_mask
= (1 << mpic
->isu_shift
) - 1;
1138 /* Display version */
1139 switch (reg
& MPIC_GREG_FEATURE_VERSION_MASK
) {
1153 printk(KERN_INFO
"mpic: Setting up MPIC \"%s\" version %s at %llx,"
1155 name
, vers
, (unsigned long long)paddr
, mpic
->num_cpus
);
1156 printk(KERN_INFO
"mpic: ISU size: %d, shift: %d, mask: %x\n",
1157 mpic
->isu_size
, mpic
->isu_shift
, mpic
->isu_mask
);
1162 if (flags
& MPIC_PRIMARY
) {
1163 mpic_primary
= mpic
;
1164 irq_set_default_host(mpic
->irqhost
);
1170 void __init
mpic_assign_isu(struct mpic
*mpic
, unsigned int isu_num
,
1173 unsigned int isu_first
= isu_num
* mpic
->isu_size
;
1175 BUG_ON(isu_num
>= MPIC_MAX_ISU
);
1177 mpic_map(mpic
, paddr
, &mpic
->isus
[isu_num
], 0,
1178 MPIC_INFO(IRQ_STRIDE
) * mpic
->isu_size
);
1179 if ((isu_first
+ mpic
->isu_size
) > mpic
->num_sources
)
1180 mpic
->num_sources
= isu_first
+ mpic
->isu_size
;
1183 void __init
mpic_set_default_senses(struct mpic
*mpic
, u8
*senses
, int count
)
1185 mpic
->senses
= senses
;
1186 mpic
->senses_count
= count
;
1189 void __init
mpic_init(struct mpic
*mpic
)
1193 BUG_ON(mpic
->num_sources
== 0);
1195 printk(KERN_INFO
"mpic: Initializing for %d sources\n", mpic
->num_sources
);
1197 /* Set current processor priority to max */
1198 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI
), 0xf);
1200 /* Initialize timers: just disable them all */
1201 for (i
= 0; i
< 4; i
++) {
1202 mpic_write(mpic
->tmregs
,
1203 i
* MPIC_INFO(TIMER_STRIDE
) +
1204 MPIC_INFO(TIMER_DESTINATION
), 0);
1205 mpic_write(mpic
->tmregs
,
1206 i
* MPIC_INFO(TIMER_STRIDE
) +
1207 MPIC_INFO(TIMER_VECTOR_PRI
),
1209 (mpic
->timer_vecs
[0] + i
));
1212 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1213 mpic_test_broken_ipi(mpic
);
1214 for (i
= 0; i
< 4; i
++) {
1217 (10 << MPIC_VECPRI_PRIORITY_SHIFT
) |
1218 (mpic
->ipi_vecs
[0] + i
));
1221 /* Initialize interrupt sources */
1222 if (mpic
->irq_count
== 0)
1223 mpic
->irq_count
= mpic
->num_sources
;
1225 /* Do the HT PIC fixups on U3 broken mpic */
1226 DBG("MPIC flags: %x\n", mpic
->flags
);
1227 if ((mpic
->flags
& MPIC_U3_HT_IRQS
) && (mpic
->flags
& MPIC_PRIMARY
)) {
1228 mpic_scan_ht_pics(mpic
);
1229 mpic_u3msi_init(mpic
);
1232 for (i
= 0; i
< mpic
->num_sources
; i
++) {
1233 /* start with vector = source number, and masked */
1234 u32 vecpri
= MPIC_VECPRI_MASK
| i
|
1235 (8 << MPIC_VECPRI_PRIORITY_SHIFT
);
1237 /* check if protected */
1238 if (mpic
->protected && test_bit(i
, mpic
->protected))
1241 mpic_irq_write(i
, MPIC_INFO(IRQ_VECTOR_PRI
), vecpri
);
1242 mpic_irq_write(i
, MPIC_INFO(IRQ_DESTINATION
),
1243 1 << hard_smp_processor_id());
1246 /* Init spurious vector */
1247 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_SPURIOUS
), mpic
->spurious_vec
);
1249 /* Disable 8259 passthrough, if supported */
1250 if (!(mpic
->flags
& MPIC_NO_PTHROU_DIS
))
1251 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
),
1252 mpic_read(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
))
1253 | MPIC_GREG_GCONF_8259_PTHROU_DIS
);
1255 /* Set current processor priority to 0 */
1256 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI
), 0);
1259 /* allocate memory to save mpic state */
1260 mpic
->save_data
= alloc_bootmem(mpic
->num_sources
* sizeof(struct mpic_irq_save
));
1261 BUG_ON(mpic
->save_data
== NULL
);
1265 void __init
mpic_set_clk_ratio(struct mpic
*mpic
, u32 clock_ratio
)
1269 v
= mpic_read(mpic
->gregs
, MPIC_GREG_GLOBAL_CONF_1
);
1270 v
&= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK
;
1271 v
|= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio
);
1272 mpic_write(mpic
->gregs
, MPIC_GREG_GLOBAL_CONF_1
, v
);
1275 void __init
mpic_set_serial_int(struct mpic
*mpic
, int enable
)
1277 unsigned long flags
;
1280 spin_lock_irqsave(&mpic_lock
, flags
);
1281 v
= mpic_read(mpic
->gregs
, MPIC_GREG_GLOBAL_CONF_1
);
1283 v
|= MPIC_GREG_GLOBAL_CONF_1_SIE
;
1285 v
&= ~MPIC_GREG_GLOBAL_CONF_1_SIE
;
1286 mpic_write(mpic
->gregs
, MPIC_GREG_GLOBAL_CONF_1
, v
);
1287 spin_unlock_irqrestore(&mpic_lock
, flags
);
1290 void mpic_irq_set_priority(unsigned int irq
, unsigned int pri
)
1293 struct mpic
*mpic
= mpic_find(irq
, &is_ipi
);
1294 unsigned int src
= mpic_irq_to_hw(irq
);
1295 unsigned long flags
;
1298 spin_lock_irqsave(&mpic_lock
, flags
);
1300 reg
= mpic_ipi_read(src
- mpic
->ipi_vecs
[0]) &
1301 ~MPIC_VECPRI_PRIORITY_MASK
;
1302 mpic_ipi_write(src
- mpic
->ipi_vecs
[0],
1303 reg
| (pri
<< MPIC_VECPRI_PRIORITY_SHIFT
));
1305 reg
= mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
))
1306 & ~MPIC_VECPRI_PRIORITY_MASK
;
1307 mpic_irq_write(src
, MPIC_INFO(IRQ_VECTOR_PRI
),
1308 reg
| (pri
<< MPIC_VECPRI_PRIORITY_SHIFT
));
1310 spin_unlock_irqrestore(&mpic_lock
, flags
);
1313 unsigned int mpic_irq_get_priority(unsigned int irq
)
1316 struct mpic
*mpic
= mpic_find(irq
, &is_ipi
);
1317 unsigned int src
= mpic_irq_to_hw(irq
);
1318 unsigned long flags
;
1321 spin_lock_irqsave(&mpic_lock
, flags
);
1323 reg
= mpic_ipi_read(src
= mpic
->ipi_vecs
[0]);
1325 reg
= mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
));
1326 spin_unlock_irqrestore(&mpic_lock
, flags
);
1327 return (reg
& MPIC_VECPRI_PRIORITY_MASK
) >> MPIC_VECPRI_PRIORITY_SHIFT
;
1330 void mpic_setup_this_cpu(void)
1333 struct mpic
*mpic
= mpic_primary
;
1334 unsigned long flags
;
1335 u32 msk
= 1 << hard_smp_processor_id();
1338 BUG_ON(mpic
== NULL
);
1340 DBG("%s: setup_this_cpu(%d)\n", mpic
->name
, hard_smp_processor_id());
1342 spin_lock_irqsave(&mpic_lock
, flags
);
1344 /* let the mpic know we want intrs. default affinity is 0xffffffff
1345 * until changed via /proc. That's how it's done on x86. If we want
1346 * it differently, then we should make sure we also change the default
1347 * values of irq_desc[].affinity in irq.c.
1349 if (distribute_irqs
) {
1350 for (i
= 0; i
< mpic
->num_sources
; i
++)
1351 mpic_irq_write(i
, MPIC_INFO(IRQ_DESTINATION
),
1352 mpic_irq_read(i
, MPIC_INFO(IRQ_DESTINATION
)) | msk
);
1355 /* Set current processor priority to 0 */
1356 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI
), 0);
1358 spin_unlock_irqrestore(&mpic_lock
, flags
);
1359 #endif /* CONFIG_SMP */
1362 int mpic_cpu_get_priority(void)
1364 struct mpic
*mpic
= mpic_primary
;
1366 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI
));
1369 void mpic_cpu_set_priority(int prio
)
1371 struct mpic
*mpic
= mpic_primary
;
1373 prio
&= MPIC_CPU_TASKPRI_MASK
;
1374 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI
), prio
);
1378 * XXX: someone who knows mpic should check this.
1379 * do we need to eoi the ipi including for kexec cpu here (see xics comments)?
1380 * or can we reset the mpic in the new kernel?
1382 void mpic_teardown_this_cpu(int secondary
)
1384 struct mpic
*mpic
= mpic_primary
;
1385 unsigned long flags
;
1386 u32 msk
= 1 << hard_smp_processor_id();
1389 BUG_ON(mpic
== NULL
);
1391 DBG("%s: teardown_this_cpu(%d)\n", mpic
->name
, hard_smp_processor_id());
1392 spin_lock_irqsave(&mpic_lock
, flags
);
1394 /* let the mpic know we don't want intrs. */
1395 for (i
= 0; i
< mpic
->num_sources
; i
++)
1396 mpic_irq_write(i
, MPIC_INFO(IRQ_DESTINATION
),
1397 mpic_irq_read(i
, MPIC_INFO(IRQ_DESTINATION
)) & ~msk
);
1399 /* Set current processor priority to max */
1400 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI
), 0xf);
1402 spin_unlock_irqrestore(&mpic_lock
, flags
);
1406 void mpic_send_ipi(unsigned int ipi_no
, unsigned int cpu_mask
)
1408 struct mpic
*mpic
= mpic_primary
;
1410 BUG_ON(mpic
== NULL
);
1413 DBG("%s: send_ipi(ipi_no: %d)\n", mpic
->name
, ipi_no
);
1416 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0
) +
1417 ipi_no
* MPIC_INFO(CPU_IPI_DISPATCH_STRIDE
),
1418 mpic_physmask(cpu_mask
& cpus_addr(cpu_online_map
)[0]));
1421 unsigned int mpic_get_one_irq(struct mpic
*mpic
)
1425 src
= mpic_cpu_read(MPIC_INFO(CPU_INTACK
)) & MPIC_INFO(VECPRI_VECTOR_MASK
);
1427 DBG("%s: get_one_irq(): %d\n", mpic
->name
, src
);
1429 if (unlikely(src
== mpic
->spurious_vec
)) {
1430 if (mpic
->flags
& MPIC_SPV_EOI
)
1434 if (unlikely(mpic
->protected && test_bit(src
, mpic
->protected))) {
1435 if (printk_ratelimit())
1436 printk(KERN_WARNING
"%s: Got protected source %d !\n",
1437 mpic
->name
, (int)src
);
1442 return irq_linear_revmap(mpic
->irqhost
, src
);
1445 unsigned int mpic_get_irq(void)
1447 struct mpic
*mpic
= mpic_primary
;
1449 BUG_ON(mpic
== NULL
);
1451 return mpic_get_one_irq(mpic
);
1456 void mpic_request_ipis(void)
1458 struct mpic
*mpic
= mpic_primary
;
1460 static char *ipi_names
[] = {
1461 "IPI0 (call function)",
1462 "IPI1 (reschedule)",
1464 "IPI3 (debugger break)",
1466 BUG_ON(mpic
== NULL
);
1468 printk(KERN_INFO
"mpic: requesting IPIs ... \n");
1470 for (i
= 0; i
< 4; i
++) {
1471 unsigned int vipi
= irq_create_mapping(mpic
->irqhost
,
1472 mpic
->ipi_vecs
[0] + i
);
1473 if (vipi
== NO_IRQ
) {
1474 printk(KERN_ERR
"Failed to map IPI %d\n", i
);
1477 err
= request_irq(vipi
, mpic_ipi_action
,
1478 IRQF_DISABLED
|IRQF_PERCPU
,
1479 ipi_names
[i
], mpic
);
1481 printk(KERN_ERR
"Request of irq %d for IPI %d failed\n",
1488 void smp_mpic_message_pass(int target
, int msg
)
1490 /* make sure we're sending something that translates to an IPI */
1491 if ((unsigned int)msg
> 3) {
1492 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1493 smp_processor_id(), msg
);
1498 mpic_send_ipi(msg
, 0xffffffff);
1500 case MSG_ALL_BUT_SELF
:
1501 mpic_send_ipi(msg
, 0xffffffff & ~(1 << smp_processor_id()));
1504 mpic_send_ipi(msg
, 1 << target
);
1509 int __init
smp_mpic_probe(void)
1513 DBG("smp_mpic_probe()...\n");
1515 nr_cpus
= cpus_weight(cpu_possible_map
);
1517 DBG("nr_cpus: %d\n", nr_cpus
);
1520 mpic_request_ipis();
1525 void __devinit
smp_mpic_setup_cpu(int cpu
)
1527 mpic_setup_this_cpu();
1529 #endif /* CONFIG_SMP */
1532 static int mpic_suspend(struct sys_device
*dev
, pm_message_t state
)
1534 struct mpic
*mpic
= container_of(dev
, struct mpic
, sysdev
);
1537 for (i
= 0; i
< mpic
->num_sources
; i
++) {
1538 mpic
->save_data
[i
].vecprio
=
1539 mpic_irq_read(i
, MPIC_INFO(IRQ_VECTOR_PRI
));
1540 mpic
->save_data
[i
].dest
=
1541 mpic_irq_read(i
, MPIC_INFO(IRQ_DESTINATION
));
1547 static int mpic_resume(struct sys_device
*dev
)
1549 struct mpic
*mpic
= container_of(dev
, struct mpic
, sysdev
);
1552 for (i
= 0; i
< mpic
->num_sources
; i
++) {
1553 mpic_irq_write(i
, MPIC_INFO(IRQ_VECTOR_PRI
),
1554 mpic
->save_data
[i
].vecprio
);
1555 mpic_irq_write(i
, MPIC_INFO(IRQ_DESTINATION
),
1556 mpic
->save_data
[i
].dest
);
1558 #ifdef CONFIG_MPIC_U3_HT_IRQS
1560 struct mpic_irq_fixup
*fixup
= &mpic
->fixups
[i
];
1563 /* we use the lowest bit in an inverted meaning */
1564 if ((mpic
->save_data
[i
].fixup_data
& 1) == 0)
1567 /* Enable and configure */
1568 writeb(0x10 + 2 * fixup
->index
, fixup
->base
+ 2);
1570 writel(mpic
->save_data
[i
].fixup_data
& ~1,
1575 } /* end for loop */
1581 static struct sysdev_class mpic_sysclass
= {
1583 .resume
= mpic_resume
,
1584 .suspend
= mpic_suspend
,
1586 set_kset_name("mpic"),
1589 static int mpic_init_sys(void)
1591 struct mpic
*mpic
= mpics
;
1594 error
= sysdev_class_register(&mpic_sysclass
);
1596 while (mpic
&& !error
) {
1597 mpic
->sysdev
.cls
= &mpic_sysclass
;
1598 mpic
->sysdev
.id
= id
++;
1599 error
= sysdev_register(&mpic
->sysdev
);
1605 device_initcall(mpic_init_sys
);