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generic: redefine resource_size_t as phys_addr_t
[deliverable/linux.git] / arch / powerpc / sysdev / ppc4xx_pci.c
1 /*
2 * PCI / PCI-X / PCI-Express support for 4xx parts
3 *
4 * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
5 *
6 * Most PCI Express code is coming from Stefan Roese implementation for
7 * arch/ppc in the Denx tree, slightly reworked by me.
8 *
9 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
10 *
11 * Some of that comes itself from a previous implementation for 440SPE only
12 * by Roland Dreier:
13 *
14 * Copyright (c) 2005 Cisco Systems. All rights reserved.
15 * Roland Dreier <rolandd@cisco.com>
16 *
17 */
18
19 #undef DEBUG
20
21 #include <linux/kernel.h>
22 #include <linux/pci.h>
23 #include <linux/init.h>
24 #include <linux/of.h>
25 #include <linux/bootmem.h>
26 #include <linux/delay.h>
27
28 #include <asm/io.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/machdep.h>
31 #include <asm/dcr.h>
32 #include <asm/dcr-regs.h>
33
34 #include "ppc4xx_pci.h"
35
36 static int dma_offset_set;
37
38 /* Move that to a useable header */
39 extern unsigned long total_memory;
40
41 #define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
42 #define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
43
44 #define RES_TO_U32_LOW(val) \
45 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val))
46 #define RES_TO_U32_HIGH(val) \
47 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0))
48
49 static inline int ppc440spe_revA(void)
50 {
51 /* Catch both 440SPe variants, with and without RAID6 support */
52 if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890)
53 return 1;
54 else
55 return 0;
56 }
57
58 static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev)
59 {
60 struct pci_controller *hose;
61 int i;
62
63 if (dev->devfn != 0 || dev->bus->self != NULL)
64 return;
65
66 hose = pci_bus_to_host(dev->bus);
67 if (hose == NULL)
68 return;
69
70 if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") &&
71 !of_device_is_compatible(hose->dn, "ibm,plb-pcix") &&
72 !of_device_is_compatible(hose->dn, "ibm,plb-pci"))
73 return;
74
75 if (of_device_is_compatible(hose->dn, "ibm,plb440epx-pci") ||
76 of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) {
77 hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM;
78 }
79
80 /* Hide the PCI host BARs from the kernel as their content doesn't
81 * fit well in the resource management
82 */
83 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
84 dev->resource[i].start = dev->resource[i].end = 0;
85 dev->resource[i].flags = 0;
86 }
87
88 printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n",
89 pci_name(dev));
90 }
91 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge);
92
93 static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
94 void __iomem *reg,
95 struct resource *res)
96 {
97 u64 size;
98 const u32 *ranges;
99 int rlen;
100 int pna = of_n_addr_cells(hose->dn);
101 int np = pna + 5;
102
103 /* Default */
104 res->start = 0;
105 res->end = size = 0x80000000;
106 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
107
108 /* Get dma-ranges property */
109 ranges = of_get_property(hose->dn, "dma-ranges", &rlen);
110 if (ranges == NULL)
111 goto out;
112
113 /* Walk it */
114 while ((rlen -= np * 4) >= 0) {
115 u32 pci_space = ranges[0];
116 u64 pci_addr = of_read_number(ranges + 1, 2);
117 u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3);
118 size = of_read_number(ranges + pna + 3, 2);
119 ranges += np;
120 if (cpu_addr == OF_BAD_ADDR || size == 0)
121 continue;
122
123 /* We only care about memory */
124 if ((pci_space & 0x03000000) != 0x02000000)
125 continue;
126
127 /* We currently only support memory at 0, and pci_addr
128 * within 32 bits space
129 */
130 if (cpu_addr != 0 || pci_addr > 0xffffffff) {
131 printk(KERN_WARNING "%s: Ignored unsupported dma range"
132 " 0x%016llx...0x%016llx -> 0x%016llx\n",
133 hose->dn->full_name,
134 pci_addr, pci_addr + size - 1, cpu_addr);
135 continue;
136 }
137
138 /* Check if not prefetchable */
139 if (!(pci_space & 0x40000000))
140 res->flags &= ~IORESOURCE_PREFETCH;
141
142
143 /* Use that */
144 res->start = pci_addr;
145 /* Beware of 32 bits resources */
146 if (sizeof(resource_size_t) == sizeof(u32) &&
147 (pci_addr + size) > 0x100000000ull)
148 res->end = 0xffffffff;
149 else
150 res->end = res->start + size - 1;
151 break;
152 }
153
154 /* We only support one global DMA offset */
155 if (dma_offset_set && pci_dram_offset != res->start) {
156 printk(KERN_ERR "%s: dma-ranges(s) mismatch\n",
157 hose->dn->full_name);
158 return -ENXIO;
159 }
160
161 /* Check that we can fit all of memory as we don't support
162 * DMA bounce buffers
163 */
164 if (size < total_memory) {
165 printk(KERN_ERR "%s: dma-ranges too small "
166 "(size=%llx total_memory=%lx)\n",
167 hose->dn->full_name, size, total_memory);
168 return -ENXIO;
169 }
170
171 /* Check we are a power of 2 size and that base is a multiple of size*/
172 if (!is_power_of_2(size) ||
173 (res->start & (size - 1)) != 0) {
174 printk(KERN_ERR "%s: dma-ranges unaligned\n",
175 hose->dn->full_name);
176 return -ENXIO;
177 }
178
179 /* Check that we are fully contained within 32 bits space */
180 if (res->end > 0xffffffff) {
181 printk(KERN_ERR "%s: dma-ranges outside of 32 bits space\n",
182 hose->dn->full_name);
183 return -ENXIO;
184 }
185 out:
186 dma_offset_set = 1;
187 pci_dram_offset = res->start;
188
189 printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n",
190 pci_dram_offset);
191 return 0;
192 }
193
194 /*
195 * 4xx PCI 2.x part
196 */
197
198 static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose,
199 void __iomem *reg)
200 {
201 u32 la, ma, pcila, pciha;
202 int i, j;
203
204 /* Setup outbound memory windows */
205 for (i = j = 0; i < 3; i++) {
206 struct resource *res = &hose->mem_resources[i];
207
208 /* we only care about memory windows */
209 if (!(res->flags & IORESOURCE_MEM))
210 continue;
211 if (j > 2) {
212 printk(KERN_WARNING "%s: Too many ranges\n",
213 hose->dn->full_name);
214 break;
215 }
216
217 /* Calculate register values */
218 la = res->start;
219 pciha = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
220 pcila = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
221
222 ma = res->end + 1 - res->start;
223 if (!is_power_of_2(ma) || ma < 0x1000 || ma > 0xffffffffu) {
224 printk(KERN_WARNING "%s: Resource out of range\n",
225 hose->dn->full_name);
226 continue;
227 }
228 ma = (0xffffffffu << ilog2(ma)) | 0x1;
229 if (res->flags & IORESOURCE_PREFETCH)
230 ma |= 0x2;
231
232 /* Program register values */
233 writel(la, reg + PCIL0_PMM0LA + (0x10 * j));
234 writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * j));
235 writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * j));
236 writel(ma, reg + PCIL0_PMM0MA + (0x10 * j));
237 j++;
238 }
239 }
240
241 static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose,
242 void __iomem *reg,
243 const struct resource *res)
244 {
245 resource_size_t size = res->end - res->start + 1;
246 u32 sa;
247
248 /* Calculate window size */
249 sa = (0xffffffffu << ilog2(size)) | 1;
250 sa |= 0x1;
251
252 /* RAM is always at 0 local for now */
253 writel(0, reg + PCIL0_PTM1LA);
254 writel(sa, reg + PCIL0_PTM1MS);
255
256 /* Map on PCI side */
257 early_write_config_dword(hose, hose->first_busno, 0,
258 PCI_BASE_ADDRESS_1, res->start);
259 early_write_config_dword(hose, hose->first_busno, 0,
260 PCI_BASE_ADDRESS_2, 0x00000000);
261 early_write_config_word(hose, hose->first_busno, 0,
262 PCI_COMMAND, 0x0006);
263 }
264
265 static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
266 {
267 /* NYI */
268 struct resource rsrc_cfg;
269 struct resource rsrc_reg;
270 struct resource dma_window;
271 struct pci_controller *hose = NULL;
272 void __iomem *reg = NULL;
273 const int *bus_range;
274 int primary = 0;
275
276 /* Fetch config space registers address */
277 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
278 printk(KERN_ERR "%s:Can't get PCI config register base !",
279 np->full_name);
280 return;
281 }
282 /* Fetch host bridge internal registers address */
283 if (of_address_to_resource(np, 3, &rsrc_reg)) {
284 printk(KERN_ERR "%s: Can't get PCI internal register base !",
285 np->full_name);
286 return;
287 }
288
289 /* Check if primary bridge */
290 if (of_get_property(np, "primary", NULL))
291 primary = 1;
292
293 /* Get bus range if any */
294 bus_range = of_get_property(np, "bus-range", NULL);
295
296 /* Map registers */
297 reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
298 if (reg == NULL) {
299 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
300 goto fail;
301 }
302
303 /* Allocate the host controller data structure */
304 hose = pcibios_alloc_controller(np);
305 if (!hose)
306 goto fail;
307
308 hose->first_busno = bus_range ? bus_range[0] : 0x0;
309 hose->last_busno = bus_range ? bus_range[1] : 0xff;
310
311 /* Setup config space */
312 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
313
314 /* Disable all windows */
315 writel(0, reg + PCIL0_PMM0MA);
316 writel(0, reg + PCIL0_PMM1MA);
317 writel(0, reg + PCIL0_PMM2MA);
318 writel(0, reg + PCIL0_PTM1MS);
319 writel(0, reg + PCIL0_PTM2MS);
320
321 /* Parse outbound mapping resources */
322 pci_process_bridge_OF_ranges(hose, np, primary);
323
324 /* Parse inbound mapping resources */
325 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
326 goto fail;
327
328 /* Configure outbound ranges POMs */
329 ppc4xx_configure_pci_PMMs(hose, reg);
330
331 /* Configure inbound ranges PIMs */
332 ppc4xx_configure_pci_PTMs(hose, reg, &dma_window);
333
334 /* We don't need the registers anymore */
335 iounmap(reg);
336 return;
337
338 fail:
339 if (hose)
340 pcibios_free_controller(hose);
341 if (reg)
342 iounmap(reg);
343 }
344
345 /*
346 * 4xx PCI-X part
347 */
348
349 static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
350 void __iomem *reg)
351 {
352 u32 lah, lal, pciah, pcial, sa;
353 int i, j;
354
355 /* Setup outbound memory windows */
356 for (i = j = 0; i < 3; i++) {
357 struct resource *res = &hose->mem_resources[i];
358
359 /* we only care about memory windows */
360 if (!(res->flags & IORESOURCE_MEM))
361 continue;
362 if (j > 1) {
363 printk(KERN_WARNING "%s: Too many ranges\n",
364 hose->dn->full_name);
365 break;
366 }
367
368 /* Calculate register values */
369 lah = RES_TO_U32_HIGH(res->start);
370 lal = RES_TO_U32_LOW(res->start);
371 pciah = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
372 pcial = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
373 sa = res->end + 1 - res->start;
374 if (!is_power_of_2(sa) || sa < 0x100000 ||
375 sa > 0xffffffffu) {
376 printk(KERN_WARNING "%s: Resource out of range\n",
377 hose->dn->full_name);
378 continue;
379 }
380 sa = (0xffffffffu << ilog2(sa)) | 0x1;
381
382 /* Program register values */
383 if (j == 0) {
384 writel(lah, reg + PCIX0_POM0LAH);
385 writel(lal, reg + PCIX0_POM0LAL);
386 writel(pciah, reg + PCIX0_POM0PCIAH);
387 writel(pcial, reg + PCIX0_POM0PCIAL);
388 writel(sa, reg + PCIX0_POM0SA);
389 } else {
390 writel(lah, reg + PCIX0_POM1LAH);
391 writel(lal, reg + PCIX0_POM1LAL);
392 writel(pciah, reg + PCIX0_POM1PCIAH);
393 writel(pcial, reg + PCIX0_POM1PCIAL);
394 writel(sa, reg + PCIX0_POM1SA);
395 }
396 j++;
397 }
398 }
399
400 static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose,
401 void __iomem *reg,
402 const struct resource *res,
403 int big_pim,
404 int enable_msi_hole)
405 {
406 resource_size_t size = res->end - res->start + 1;
407 u32 sa;
408
409 /* RAM is always at 0 */
410 writel(0x00000000, reg + PCIX0_PIM0LAH);
411 writel(0x00000000, reg + PCIX0_PIM0LAL);
412
413 /* Calculate window size */
414 sa = (0xffffffffu << ilog2(size)) | 1;
415 sa |= 0x1;
416 if (res->flags & IORESOURCE_PREFETCH)
417 sa |= 0x2;
418 if (enable_msi_hole)
419 sa |= 0x4;
420 writel(sa, reg + PCIX0_PIM0SA);
421 if (big_pim)
422 writel(0xffffffff, reg + PCIX0_PIM0SAH);
423
424 /* Map on PCI side */
425 writel(0x00000000, reg + PCIX0_BAR0H);
426 writel(res->start, reg + PCIX0_BAR0L);
427 writew(0x0006, reg + PCIX0_COMMAND);
428 }
429
430 static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
431 {
432 struct resource rsrc_cfg;
433 struct resource rsrc_reg;
434 struct resource dma_window;
435 struct pci_controller *hose = NULL;
436 void __iomem *reg = NULL;
437 const int *bus_range;
438 int big_pim = 0, msi = 0, primary = 0;
439
440 /* Fetch config space registers address */
441 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
442 printk(KERN_ERR "%s:Can't get PCI-X config register base !",
443 np->full_name);
444 return;
445 }
446 /* Fetch host bridge internal registers address */
447 if (of_address_to_resource(np, 3, &rsrc_reg)) {
448 printk(KERN_ERR "%s: Can't get PCI-X internal register base !",
449 np->full_name);
450 return;
451 }
452
453 /* Check if it supports large PIMs (440GX) */
454 if (of_get_property(np, "large-inbound-windows", NULL))
455 big_pim = 1;
456
457 /* Check if we should enable MSIs inbound hole */
458 if (of_get_property(np, "enable-msi-hole", NULL))
459 msi = 1;
460
461 /* Check if primary bridge */
462 if (of_get_property(np, "primary", NULL))
463 primary = 1;
464
465 /* Get bus range if any */
466 bus_range = of_get_property(np, "bus-range", NULL);
467
468 /* Map registers */
469 reg = ioremap(rsrc_reg.start, rsrc_reg.end + 1 - rsrc_reg.start);
470 if (reg == NULL) {
471 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
472 goto fail;
473 }
474
475 /* Allocate the host controller data structure */
476 hose = pcibios_alloc_controller(np);
477 if (!hose)
478 goto fail;
479
480 hose->first_busno = bus_range ? bus_range[0] : 0x0;
481 hose->last_busno = bus_range ? bus_range[1] : 0xff;
482
483 /* Setup config space */
484 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
485
486 /* Disable all windows */
487 writel(0, reg + PCIX0_POM0SA);
488 writel(0, reg + PCIX0_POM1SA);
489 writel(0, reg + PCIX0_POM2SA);
490 writel(0, reg + PCIX0_PIM0SA);
491 writel(0, reg + PCIX0_PIM1SA);
492 writel(0, reg + PCIX0_PIM2SA);
493 if (big_pim) {
494 writel(0, reg + PCIX0_PIM0SAH);
495 writel(0, reg + PCIX0_PIM2SAH);
496 }
497
498 /* Parse outbound mapping resources */
499 pci_process_bridge_OF_ranges(hose, np, primary);
500
501 /* Parse inbound mapping resources */
502 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
503 goto fail;
504
505 /* Configure outbound ranges POMs */
506 ppc4xx_configure_pcix_POMs(hose, reg);
507
508 /* Configure inbound ranges PIMs */
509 ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi);
510
511 /* We don't need the registers anymore */
512 iounmap(reg);
513 return;
514
515 fail:
516 if (hose)
517 pcibios_free_controller(hose);
518 if (reg)
519 iounmap(reg);
520 }
521
522 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
523
524 /*
525 * 4xx PCI-Express part
526 *
527 * We support 3 parts currently based on the compatible property:
528 *
529 * ibm,plb-pciex-440spe
530 * ibm,plb-pciex-405ex
531 * ibm,plb-pciex-460ex
532 *
533 * Anything else will be rejected for now as they are all subtly
534 * different unfortunately.
535 *
536 */
537
538 #define MAX_PCIE_BUS_MAPPED 0x40
539
540 struct ppc4xx_pciex_port
541 {
542 struct pci_controller *hose;
543 struct device_node *node;
544 unsigned int index;
545 int endpoint;
546 int link;
547 int has_ibpre;
548 unsigned int sdr_base;
549 dcr_host_t dcrs;
550 struct resource cfg_space;
551 struct resource utl_regs;
552 void __iomem *utl_base;
553 };
554
555 static struct ppc4xx_pciex_port *ppc4xx_pciex_ports;
556 static unsigned int ppc4xx_pciex_port_count;
557
558 struct ppc4xx_pciex_hwops
559 {
560 int (*core_init)(struct device_node *np);
561 int (*port_init_hw)(struct ppc4xx_pciex_port *port);
562 int (*setup_utl)(struct ppc4xx_pciex_port *port);
563 };
564
565 static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops;
566
567 #ifdef CONFIG_44x
568
569 /* Check various reset bits of the 440SPe PCIe core */
570 static int __init ppc440spe_pciex_check_reset(struct device_node *np)
571 {
572 u32 valPE0, valPE1, valPE2;
573 int err = 0;
574
575 /* SDR0_PEGPLLLCT1 reset */
576 if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) {
577 /*
578 * the PCIe core was probably already initialised
579 * by firmware - let's re-reset RCSSET regs
580 *
581 * -- Shouldn't we also re-reset the whole thing ? -- BenH
582 */
583 pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n");
584 mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000);
585 mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000);
586 mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000);
587 }
588
589 valPE0 = mfdcri(SDR0, PESDR0_440SPE_RCSSET);
590 valPE1 = mfdcri(SDR0, PESDR1_440SPE_RCSSET);
591 valPE2 = mfdcri(SDR0, PESDR2_440SPE_RCSSET);
592
593 /* SDR0_PExRCSSET rstgu */
594 if (!(valPE0 & 0x01000000) ||
595 !(valPE1 & 0x01000000) ||
596 !(valPE2 & 0x01000000)) {
597 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n");
598 err = -1;
599 }
600
601 /* SDR0_PExRCSSET rstdl */
602 if (!(valPE0 & 0x00010000) ||
603 !(valPE1 & 0x00010000) ||
604 !(valPE2 & 0x00010000)) {
605 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n");
606 err = -1;
607 }
608
609 /* SDR0_PExRCSSET rstpyn */
610 if ((valPE0 & 0x00001000) ||
611 (valPE1 & 0x00001000) ||
612 (valPE2 & 0x00001000)) {
613 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n");
614 err = -1;
615 }
616
617 /* SDR0_PExRCSSET hldplb */
618 if ((valPE0 & 0x10000000) ||
619 (valPE1 & 0x10000000) ||
620 (valPE2 & 0x10000000)) {
621 printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n");
622 err = -1;
623 }
624
625 /* SDR0_PExRCSSET rdy */
626 if ((valPE0 & 0x00100000) ||
627 (valPE1 & 0x00100000) ||
628 (valPE2 & 0x00100000)) {
629 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n");
630 err = -1;
631 }
632
633 /* SDR0_PExRCSSET shutdown */
634 if ((valPE0 & 0x00000100) ||
635 (valPE1 & 0x00000100) ||
636 (valPE2 & 0x00000100)) {
637 printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n");
638 err = -1;
639 }
640
641 return err;
642 }
643
644 /* Global PCIe core initializations for 440SPe core */
645 static int __init ppc440spe_pciex_core_init(struct device_node *np)
646 {
647 int time_out = 20;
648
649 /* Set PLL clock receiver to LVPECL */
650 dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28);
651
652 /* Shouldn't we do all the calibration stuff etc... here ? */
653 if (ppc440spe_pciex_check_reset(np))
654 return -ENXIO;
655
656 if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) {
657 printk(KERN_INFO "PCIE: PESDR_PLLCT2 resistance calibration "
658 "failed (0x%08x)\n",
659 mfdcri(SDR0, PESDR0_PLLLCT2));
660 return -1;
661 }
662
663 /* De-assert reset of PCIe PLL, wait for lock */
664 dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0);
665 udelay(3);
666
667 while (time_out) {
668 if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) {
669 time_out--;
670 udelay(1);
671 } else
672 break;
673 }
674 if (!time_out) {
675 printk(KERN_INFO "PCIE: VCO output not locked\n");
676 return -1;
677 }
678
679 pr_debug("PCIE initialization OK\n");
680
681 return 3;
682 }
683
684 static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
685 {
686 u32 val = 1 << 24;
687
688 if (port->endpoint)
689 val = PTYPE_LEGACY_ENDPOINT << 20;
690 else
691 val = PTYPE_ROOT_PORT << 20;
692
693 if (port->index == 0)
694 val |= LNKW_X8 << 12;
695 else
696 val |= LNKW_X4 << 12;
697
698 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
699 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);
700 if (ppc440spe_revA())
701 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);
702 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);
703 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);
704 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000);
705 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000);
706 if (port->index == 0) {
707 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1,
708 0x35000000);
709 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1,
710 0x35000000);
711 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1,
712 0x35000000);
713 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
714 0x35000000);
715 }
716 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
717 (1 << 24) | (1 << 16), 1 << 12);
718
719 return 0;
720 }
721
722 static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
723 {
724 return ppc440spe_pciex_init_port_hw(port);
725 }
726
727 static int ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
728 {
729 int rc = ppc440spe_pciex_init_port_hw(port);
730
731 port->has_ibpre = 1;
732
733 return rc;
734 }
735
736 static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port)
737 {
738 /* XXX Check what that value means... I hate magic */
739 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800);
740
741 /*
742 * Set buffer allocations and then assert VRB and TXE.
743 */
744 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
745 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
746 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000);
747 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000);
748 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000);
749 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000);
750 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
751 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
752
753 return 0;
754 }
755
756 static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port)
757 {
758 /* Report CRS to the operating system */
759 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
760
761 return 0;
762 }
763
764 static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
765 {
766 .core_init = ppc440spe_pciex_core_init,
767 .port_init_hw = ppc440speA_pciex_init_port_hw,
768 .setup_utl = ppc440speA_pciex_init_utl,
769 };
770
771 static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
772 {
773 .core_init = ppc440spe_pciex_core_init,
774 .port_init_hw = ppc440speB_pciex_init_port_hw,
775 .setup_utl = ppc440speB_pciex_init_utl,
776 };
777
778 static int __init ppc460ex_pciex_core_init(struct device_node *np)
779 {
780 /* Nothing to do, return 2 ports */
781 return 2;
782 }
783
784 static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
785 {
786 u32 val;
787 u32 utlset1;
788
789 if (port->endpoint)
790 val = PTYPE_LEGACY_ENDPOINT << 20;
791 else
792 val = PTYPE_ROOT_PORT << 20;
793
794 if (port->index == 0) {
795 val |= LNKW_X1 << 12;
796 utlset1 = 0x20000000;
797 } else {
798 val |= LNKW_X4 << 12;
799 utlset1 = 0x20101101;
800 }
801
802 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
803 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
804 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);
805
806 switch (port->index) {
807 case 0:
808 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
809 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000136);
810 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
811
812 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000);
813 break;
814
815 case 1:
816 mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230);
817 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);
818 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);
819 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);
820 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000136);
821 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000136);
822 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000136);
823 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000136);
824 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);
825 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);
826 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);
827 mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006);
828
829 mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000);
830 break;
831 }
832
833 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
834 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
835 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
836
837 /* Poll for PHY reset */
838 /* XXX FIXME add timeout */
839 switch (port->index) {
840 case 0:
841 while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1))
842 udelay(10);
843 break;
844 case 1:
845 while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1))
846 udelay(10);
847 break;
848 }
849
850 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
851 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
852 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
853 PESDRx_RCSSET_RSTPYN);
854
855 port->has_ibpre = 1;
856
857 return 0;
858 }
859
860 static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
861 {
862 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
863
864 /*
865 * Set buffer allocations and then assert VRB and TXE.
866 */
867 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c);
868 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
869 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
870 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
871 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000);
872 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
873 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
874 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000);
875 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
876
877 return 0;
878 }
879
880 static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
881 {
882 .core_init = ppc460ex_pciex_core_init,
883 .port_init_hw = ppc460ex_pciex_init_port_hw,
884 .setup_utl = ppc460ex_pciex_init_utl,
885 };
886
887 #endif /* CONFIG_44x */
888
889 #ifdef CONFIG_40x
890
891 static int __init ppc405ex_pciex_core_init(struct device_node *np)
892 {
893 /* Nothing to do, return 2 ports */
894 return 2;
895 }
896
897 static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port)
898 {
899 /* Assert the PE0_PHY reset */
900 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000);
901 msleep(1);
902
903 /* deassert the PE0_hotreset */
904 if (port->endpoint)
905 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000);
906 else
907 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000);
908
909 /* poll for phy !reset */
910 /* XXX FIXME add timeout */
911 while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000))
912 ;
913
914 /* deassert the PE0_gpl_utl_reset */
915 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000);
916 }
917
918 static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
919 {
920 u32 val;
921
922 if (port->endpoint)
923 val = PTYPE_LEGACY_ENDPOINT;
924 else
925 val = PTYPE_ROOT_PORT;
926
927 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET,
928 1 << 24 | val << 20 | LNKW_X1 << 12);
929
930 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
931 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
932 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000);
933 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003);
934
935 /*
936 * Only reset the PHY when no link is currently established.
937 * This is for the Atheros PCIe board which has problems to establish
938 * the link (again) after this PHY reset. All other currently tested
939 * PCIe boards don't show this problem.
940 * This has to be re-tested and fixed in a later release!
941 */
942 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
943 if (!(val & 0x00001000))
944 ppc405ex_pcie_phy_reset(port);
945
946 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */
947
948 port->has_ibpre = 1;
949
950 return 0;
951 }
952
953 static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
954 {
955 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
956
957 /*
958 * Set buffer allocations and then assert VRB and TXE.
959 */
960 out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000);
961 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
962 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
963 out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000);
964 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
965 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
966 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
967 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
968
969 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
970
971 return 0;
972 }
973
974 static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
975 {
976 .core_init = ppc405ex_pciex_core_init,
977 .port_init_hw = ppc405ex_pciex_init_port_hw,
978 .setup_utl = ppc405ex_pciex_init_utl,
979 };
980
981 #endif /* CONFIG_40x */
982
983
984 /* Check that the core has been initied and if not, do it */
985 static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
986 {
987 static int core_init;
988 int count = -ENODEV;
989
990 if (core_init++)
991 return 0;
992
993 #ifdef CONFIG_44x
994 if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) {
995 if (ppc440spe_revA())
996 ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops;
997 else
998 ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
999 }
1000 if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
1001 ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
1002 #endif /* CONFIG_44x */
1003 #ifdef CONFIG_40x
1004 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
1005 ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops;
1006 #endif
1007 if (ppc4xx_pciex_hwops == NULL) {
1008 printk(KERN_WARNING "PCIE: unknown host type %s\n",
1009 np->full_name);
1010 return -ENODEV;
1011 }
1012
1013 count = ppc4xx_pciex_hwops->core_init(np);
1014 if (count > 0) {
1015 ppc4xx_pciex_ports =
1016 kzalloc(count * sizeof(struct ppc4xx_pciex_port),
1017 GFP_KERNEL);
1018 if (ppc4xx_pciex_ports) {
1019 ppc4xx_pciex_port_count = count;
1020 return 0;
1021 }
1022 printk(KERN_WARNING "PCIE: failed to allocate ports array\n");
1023 return -ENOMEM;
1024 }
1025 return -ENODEV;
1026 }
1027
1028 static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port)
1029 {
1030 /* We map PCI Express configuration based on the reg property */
1031 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH,
1032 RES_TO_U32_HIGH(port->cfg_space.start));
1033 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL,
1034 RES_TO_U32_LOW(port->cfg_space.start));
1035
1036 /* XXX FIXME: Use size from reg property. For now, map 512M */
1037 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001);
1038
1039 /* We map UTL registers based on the reg property */
1040 dcr_write(port->dcrs, DCRO_PEGPL_REGBAH,
1041 RES_TO_U32_HIGH(port->utl_regs.start));
1042 dcr_write(port->dcrs, DCRO_PEGPL_REGBAL,
1043 RES_TO_U32_LOW(port->utl_regs.start));
1044
1045 /* XXX FIXME: Use size from reg property */
1046 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001);
1047
1048 /* Disable all other outbound windows */
1049 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0);
1050 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0);
1051 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0);
1052 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
1053 }
1054
1055 static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
1056 unsigned int sdr_offset,
1057 unsigned int mask,
1058 unsigned int value,
1059 int timeout_ms)
1060 {
1061 u32 val;
1062
1063 while(timeout_ms--) {
1064 val = mfdcri(SDR0, port->sdr_base + sdr_offset);
1065 if ((val & mask) == value) {
1066 pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
1067 port->index, sdr_offset, timeout_ms, val);
1068 return 0;
1069 }
1070 msleep(1);
1071 }
1072 return -1;
1073 }
1074
1075 static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1076 {
1077 int rc = 0;
1078
1079 /* Init HW */
1080 if (ppc4xx_pciex_hwops->port_init_hw)
1081 rc = ppc4xx_pciex_hwops->port_init_hw(port);
1082 if (rc != 0)
1083 return rc;
1084
1085 printk(KERN_INFO "PCIE%d: Checking link...\n",
1086 port->index);
1087
1088 /* Wait for reset to complete */
1089 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
1090 printk(KERN_WARNING "PCIE%d: PGRST failed\n",
1091 port->index);
1092 return -1;
1093 }
1094
1095 /* Check for card presence detect if supported, if not, just wait for
1096 * link unconditionally.
1097 *
1098 * note that we don't fail if there is no link, we just filter out
1099 * config space accesses. That way, it will be easier to implement
1100 * hotplug later on.
1101 */
1102 if (!port->has_ibpre ||
1103 !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
1104 1 << 28, 1 << 28, 100)) {
1105 printk(KERN_INFO
1106 "PCIE%d: Device detected, waiting for link...\n",
1107 port->index);
1108 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
1109 0x1000, 0x1000, 2000))
1110 printk(KERN_WARNING
1111 "PCIE%d: Link up failed\n", port->index);
1112 else {
1113 printk(KERN_INFO
1114 "PCIE%d: link is up !\n", port->index);
1115 port->link = 1;
1116 }
1117 } else
1118 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
1119
1120 /*
1121 * Initialize mapping: disable all regions and configure
1122 * CFG and REG regions based on resources in the device tree
1123 */
1124 ppc4xx_pciex_port_init_mapping(port);
1125
1126 /*
1127 * Map UTL
1128 */
1129 port->utl_base = ioremap(port->utl_regs.start, 0x100);
1130 BUG_ON(port->utl_base == NULL);
1131
1132 /*
1133 * Setup UTL registers --BenH.
1134 */
1135 if (ppc4xx_pciex_hwops->setup_utl)
1136 ppc4xx_pciex_hwops->setup_utl(port);
1137
1138 /*
1139 * Check for VC0 active and assert RDY.
1140 */
1141 if (port->link &&
1142 ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
1143 1 << 16, 1 << 16, 5000)) {
1144 printk(KERN_INFO "PCIE%d: VC0 not active\n", port->index);
1145 port->link = 0;
1146 }
1147
1148 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
1149 msleep(100);
1150
1151 return 0;
1152 }
1153
1154 static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port,
1155 struct pci_bus *bus,
1156 unsigned int devfn)
1157 {
1158 static int message;
1159
1160 /* Endpoint can not generate upstream(remote) config cycles */
1161 if (port->endpoint && bus->number != port->hose->first_busno)
1162 return PCIBIOS_DEVICE_NOT_FOUND;
1163
1164 /* Check we are within the mapped range */
1165 if (bus->number > port->hose->last_busno) {
1166 if (!message) {
1167 printk(KERN_WARNING "Warning! Probing bus %u"
1168 " out of range !\n", bus->number);
1169 message++;
1170 }
1171 return PCIBIOS_DEVICE_NOT_FOUND;
1172 }
1173
1174 /* The root complex has only one device / function */
1175 if (bus->number == port->hose->first_busno && devfn != 0)
1176 return PCIBIOS_DEVICE_NOT_FOUND;
1177
1178 /* The other side of the RC has only one device as well */
1179 if (bus->number == (port->hose->first_busno + 1) &&
1180 PCI_SLOT(devfn) != 0)
1181 return PCIBIOS_DEVICE_NOT_FOUND;
1182
1183 /* Check if we have a link */
1184 if ((bus->number != port->hose->first_busno) && !port->link)
1185 return PCIBIOS_DEVICE_NOT_FOUND;
1186
1187 return 0;
1188 }
1189
1190 static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port,
1191 struct pci_bus *bus,
1192 unsigned int devfn)
1193 {
1194 int relbus;
1195
1196 /* Remove the casts when we finally remove the stupid volatile
1197 * in struct pci_controller
1198 */
1199 if (bus->number == port->hose->first_busno)
1200 return (void __iomem *)port->hose->cfg_addr;
1201
1202 relbus = bus->number - (port->hose->first_busno + 1);
1203 return (void __iomem *)port->hose->cfg_data +
1204 ((relbus << 20) | (devfn << 12));
1205 }
1206
1207 static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
1208 int offset, int len, u32 *val)
1209 {
1210 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1211 struct ppc4xx_pciex_port *port =
1212 &ppc4xx_pciex_ports[hose->indirect_type];
1213 void __iomem *addr;
1214 u32 gpl_cfg;
1215
1216 BUG_ON(hose != port->hose);
1217
1218 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1219 return PCIBIOS_DEVICE_NOT_FOUND;
1220
1221 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1222
1223 /*
1224 * Reading from configuration space of non-existing device can
1225 * generate transaction errors. For the read duration we suppress
1226 * assertion of machine check exceptions to avoid those.
1227 */
1228 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1229 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1230
1231 /* Make sure no CRS is recorded */
1232 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000);
1233
1234 switch (len) {
1235 case 1:
1236 *val = in_8((u8 *)(addr + offset));
1237 break;
1238 case 2:
1239 *val = in_le16((u16 *)(addr + offset));
1240 break;
1241 default:
1242 *val = in_le32((u32 *)(addr + offset));
1243 break;
1244 }
1245
1246 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x"
1247 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1248 bus->number, hose->first_busno, hose->last_busno,
1249 devfn, offset, len, addr + offset, *val);
1250
1251 /* Check for CRS (440SPe rev B does that for us but heh ..) */
1252 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) {
1253 pr_debug("Got CRS !\n");
1254 if (len != 4 || offset != 0)
1255 return PCIBIOS_DEVICE_NOT_FOUND;
1256 *val = 0xffff0001;
1257 }
1258
1259 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1260
1261 return PCIBIOS_SUCCESSFUL;
1262 }
1263
1264 static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
1265 int offset, int len, u32 val)
1266 {
1267 struct pci_controller *hose = (struct pci_controller *) bus->sysdata;
1268 struct ppc4xx_pciex_port *port =
1269 &ppc4xx_pciex_ports[hose->indirect_type];
1270 void __iomem *addr;
1271 u32 gpl_cfg;
1272
1273 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1274 return PCIBIOS_DEVICE_NOT_FOUND;
1275
1276 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1277
1278 /*
1279 * Reading from configuration space of non-existing device can
1280 * generate transaction errors. For the read duration we suppress
1281 * assertion of machine check exceptions to avoid those.
1282 */
1283 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1284 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1285
1286 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x"
1287 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1288 bus->number, hose->first_busno, hose->last_busno,
1289 devfn, offset, len, addr + offset, val);
1290
1291 switch (len) {
1292 case 1:
1293 out_8((u8 *)(addr + offset), val);
1294 break;
1295 case 2:
1296 out_le16((u16 *)(addr + offset), val);
1297 break;
1298 default:
1299 out_le32((u32 *)(addr + offset), val);
1300 break;
1301 }
1302
1303 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1304
1305 return PCIBIOS_SUCCESSFUL;
1306 }
1307
1308 static struct pci_ops ppc4xx_pciex_pci_ops =
1309 {
1310 .read = ppc4xx_pciex_read_config,
1311 .write = ppc4xx_pciex_write_config,
1312 };
1313
1314 static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
1315 struct pci_controller *hose,
1316 void __iomem *mbase)
1317 {
1318 u32 lah, lal, pciah, pcial, sa;
1319 int i, j;
1320
1321 /* Setup outbound memory windows */
1322 for (i = j = 0; i < 3; i++) {
1323 struct resource *res = &hose->mem_resources[i];
1324
1325 /* we only care about memory windows */
1326 if (!(res->flags & IORESOURCE_MEM))
1327 continue;
1328 if (j > 1) {
1329 printk(KERN_WARNING "%s: Too many ranges\n",
1330 port->node->full_name);
1331 break;
1332 }
1333
1334 /* Calculate register values */
1335 lah = RES_TO_U32_HIGH(res->start);
1336 lal = RES_TO_U32_LOW(res->start);
1337 pciah = RES_TO_U32_HIGH(res->start - hose->pci_mem_offset);
1338 pcial = RES_TO_U32_LOW(res->start - hose->pci_mem_offset);
1339 sa = res->end + 1 - res->start;
1340 if (!is_power_of_2(sa) || sa < 0x100000 ||
1341 sa > 0xffffffffu) {
1342 printk(KERN_WARNING "%s: Resource out of range\n",
1343 port->node->full_name);
1344 continue;
1345 }
1346 sa = (0xffffffffu << ilog2(sa)) | 0x1;
1347
1348 /* Program register values */
1349 switch (j) {
1350 case 0:
1351 out_le32(mbase + PECFG_POM0LAH, pciah);
1352 out_le32(mbase + PECFG_POM0LAL, pcial);
1353 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah);
1354 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal);
1355 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff);
1356 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, sa | 3);
1357 break;
1358 case 1:
1359 out_le32(mbase + PECFG_POM1LAH, pciah);
1360 out_le32(mbase + PECFG_POM1LAL, pcial);
1361 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah);
1362 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);
1363 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff);
1364 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, sa | 3);
1365 break;
1366 }
1367 j++;
1368 }
1369
1370 /* Configure IO, always 64K starting at 0 */
1371 if (hose->io_resource.flags & IORESOURCE_IO) {
1372 lah = RES_TO_U32_HIGH(hose->io_base_phys);
1373 lal = RES_TO_U32_LOW(hose->io_base_phys);
1374 out_le32(mbase + PECFG_POM2LAH, 0);
1375 out_le32(mbase + PECFG_POM2LAL, 0);
1376 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah);
1377 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal);
1378 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff);
1379 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0xffff0000 | 3);
1380 }
1381 }
1382
1383 static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
1384 struct pci_controller *hose,
1385 void __iomem *mbase,
1386 struct resource *res)
1387 {
1388 resource_size_t size = res->end - res->start + 1;
1389 u64 sa;
1390
1391 if (port->endpoint) {
1392 resource_size_t ep_addr = 0;
1393 resource_size_t ep_size = 32 << 20;
1394
1395 /* Currently we map a fixed 64MByte window to PLB address
1396 * 0 (SDRAM). This should probably be configurable via a dts
1397 * property.
1398 */
1399
1400 /* Calculate window size */
1401 sa = (0xffffffffffffffffull << ilog2(ep_size));;
1402
1403 /* Setup BAR0 */
1404 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1405 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa) |
1406 PCI_BASE_ADDRESS_MEM_TYPE_64);
1407
1408 /* Disable BAR1 & BAR2 */
1409 out_le32(mbase + PECFG_BAR1MPA, 0);
1410 out_le32(mbase + PECFG_BAR2HMPA, 0);
1411 out_le32(mbase + PECFG_BAR2LMPA, 0);
1412
1413 out_le32(mbase + PECFG_PIM01SAH, RES_TO_U32_HIGH(sa));
1414 out_le32(mbase + PECFG_PIM01SAL, RES_TO_U32_LOW(sa));
1415
1416 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr));
1417 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(ep_addr));
1418 } else {
1419 /* Calculate window size */
1420 sa = (0xffffffffffffffffull << ilog2(size));;
1421 if (res->flags & IORESOURCE_PREFETCH)
1422 sa |= 0x8;
1423
1424 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1425 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa));
1426
1427 /* The setup of the split looks weird to me ... let's see
1428 * if it works
1429 */
1430 out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
1431 out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
1432 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
1433 out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
1434 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
1435 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
1436
1437 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start));
1438 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start));
1439 }
1440
1441 /* Enable inbound mapping */
1442 out_le32(mbase + PECFG_PIMEN, 0x1);
1443
1444 /* Enable I/O, Mem, and Busmaster cycles */
1445 out_le16(mbase + PCI_COMMAND,
1446 in_le16(mbase + PCI_COMMAND) |
1447 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1448 }
1449
1450 static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port)
1451 {
1452 struct resource dma_window;
1453 struct pci_controller *hose = NULL;
1454 const int *bus_range;
1455 int primary = 0, busses;
1456 void __iomem *mbase = NULL, *cfg_data = NULL;
1457 const u32 *pval;
1458 u32 val;
1459
1460 /* Check if primary bridge */
1461 if (of_get_property(port->node, "primary", NULL))
1462 primary = 1;
1463
1464 /* Get bus range if any */
1465 bus_range = of_get_property(port->node, "bus-range", NULL);
1466
1467 /* Allocate the host controller data structure */
1468 hose = pcibios_alloc_controller(port->node);
1469 if (!hose)
1470 goto fail;
1471
1472 /* We stick the port number in "indirect_type" so the config space
1473 * ops can retrieve the port data structure easily
1474 */
1475 hose->indirect_type = port->index;
1476
1477 /* Get bus range */
1478 hose->first_busno = bus_range ? bus_range[0] : 0x0;
1479 hose->last_busno = bus_range ? bus_range[1] : 0xff;
1480
1481 /* Because of how big mapping the config space is (1M per bus), we
1482 * limit how many busses we support. In the long run, we could replace
1483 * that with something akin to kmap_atomic instead. We set aside 1 bus
1484 * for the host itself too.
1485 */
1486 busses = hose->last_busno - hose->first_busno; /* This is off by 1 */
1487 if (busses > MAX_PCIE_BUS_MAPPED) {
1488 busses = MAX_PCIE_BUS_MAPPED;
1489 hose->last_busno = hose->first_busno + busses;
1490 }
1491
1492 if (!port->endpoint) {
1493 /* Only map the external config space in cfg_data for
1494 * PCIe root-complexes. External space is 1M per bus
1495 */
1496 cfg_data = ioremap(port->cfg_space.start +
1497 (hose->first_busno + 1) * 0x100000,
1498 busses * 0x100000);
1499 if (cfg_data == NULL) {
1500 printk(KERN_ERR "%s: Can't map external config space !",
1501 port->node->full_name);
1502 goto fail;
1503 }
1504 hose->cfg_data = cfg_data;
1505 }
1506
1507 /* Always map the host config space in cfg_addr.
1508 * Internal space is 4K
1509 */
1510 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
1511 if (mbase == NULL) {
1512 printk(KERN_ERR "%s: Can't map internal config space !",
1513 port->node->full_name);
1514 goto fail;
1515 }
1516 hose->cfg_addr = mbase;
1517
1518 pr_debug("PCIE %s, bus %d..%d\n", port->node->full_name,
1519 hose->first_busno, hose->last_busno);
1520 pr_debug(" config space mapped at: root @0x%p, other @0x%p\n",
1521 hose->cfg_addr, hose->cfg_data);
1522
1523 /* Setup config space */
1524 hose->ops = &ppc4xx_pciex_pci_ops;
1525 port->hose = hose;
1526 mbase = (void __iomem *)hose->cfg_addr;
1527
1528 if (!port->endpoint) {
1529 /*
1530 * Set bus numbers on our root port
1531 */
1532 out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno);
1533 out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1);
1534 out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno);
1535 }
1536
1537 /*
1538 * OMRs are already reset, also disable PIMs
1539 */
1540 out_le32(mbase + PECFG_PIMEN, 0);
1541
1542 /* Parse outbound mapping resources */
1543 pci_process_bridge_OF_ranges(hose, port->node, primary);
1544
1545 /* Parse inbound mapping resources */
1546 if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0)
1547 goto fail;
1548
1549 /* Configure outbound ranges POMs */
1550 ppc4xx_configure_pciex_POMs(port, hose, mbase);
1551
1552 /* Configure inbound ranges PIMs */
1553 ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window);
1554
1555 /* The root complex doesn't show up if we don't set some vendor
1556 * and device IDs into it. The defaults below are the same bogus
1557 * one that the initial code in arch/ppc had. This can be
1558 * overwritten by setting the "vendor-id/device-id" properties
1559 * in the pciex node.
1560 */
1561
1562 /* Get the (optional) vendor-/device-id from the device-tree */
1563 pval = of_get_property(port->node, "vendor-id", NULL);
1564 if (pval) {
1565 val = *pval;
1566 } else {
1567 if (!port->endpoint)
1568 val = 0xaaa0 + port->index;
1569 else
1570 val = 0xeee0 + port->index;
1571 }
1572 out_le16(mbase + 0x200, val);
1573
1574 pval = of_get_property(port->node, "device-id", NULL);
1575 if (pval) {
1576 val = *pval;
1577 } else {
1578 if (!port->endpoint)
1579 val = 0xbed0 + port->index;
1580 else
1581 val = 0xfed0 + port->index;
1582 }
1583 out_le16(mbase + 0x202, val);
1584
1585 if (!port->endpoint) {
1586 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
1587 out_le32(mbase + 0x208, 0x06040001);
1588
1589 printk(KERN_INFO "PCIE%d: successfully set as root-complex\n",
1590 port->index);
1591 } else {
1592 /* Set Class Code to Processor/PPC */
1593 out_le32(mbase + 0x208, 0x0b200001);
1594
1595 printk(KERN_INFO "PCIE%d: successfully set as endpoint\n",
1596 port->index);
1597 }
1598
1599 return;
1600 fail:
1601 if (hose)
1602 pcibios_free_controller(hose);
1603 if (cfg_data)
1604 iounmap(cfg_data);
1605 if (mbase)
1606 iounmap(mbase);
1607 }
1608
1609 static void __init ppc4xx_probe_pciex_bridge(struct device_node *np)
1610 {
1611 struct ppc4xx_pciex_port *port;
1612 const u32 *pval;
1613 int portno;
1614 unsigned int dcrs;
1615 const char *val;
1616
1617 /* First, proceed to core initialization as we assume there's
1618 * only one PCIe core in the system
1619 */
1620 if (ppc4xx_pciex_check_core_init(np))
1621 return;
1622
1623 /* Get the port number from the device-tree */
1624 pval = of_get_property(np, "port", NULL);
1625 if (pval == NULL) {
1626 printk(KERN_ERR "PCIE: Can't find port number for %s\n",
1627 np->full_name);
1628 return;
1629 }
1630 portno = *pval;
1631 if (portno >= ppc4xx_pciex_port_count) {
1632 printk(KERN_ERR "PCIE: port number out of range for %s\n",
1633 np->full_name);
1634 return;
1635 }
1636 port = &ppc4xx_pciex_ports[portno];
1637 port->index = portno;
1638
1639 /*
1640 * Check if device is enabled
1641 */
1642 if (!of_device_is_available(np)) {
1643 printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index);
1644 return;
1645 }
1646
1647 port->node = of_node_get(np);
1648 pval = of_get_property(np, "sdr-base", NULL);
1649 if (pval == NULL) {
1650 printk(KERN_ERR "PCIE: missing sdr-base for %s\n",
1651 np->full_name);
1652 return;
1653 }
1654 port->sdr_base = *pval;
1655
1656 /* Check if device_type property is set to "pci" or "pci-endpoint".
1657 * Resulting from this setup this PCIe port will be configured
1658 * as root-complex or as endpoint.
1659 */
1660 val = of_get_property(port->node, "device_type", NULL);
1661 if (!strcmp(val, "pci-endpoint")) {
1662 port->endpoint = 1;
1663 } else if (!strcmp(val, "pci")) {
1664 port->endpoint = 0;
1665 } else {
1666 printk(KERN_ERR "PCIE: missing or incorrect device_type for %s\n",
1667 np->full_name);
1668 return;
1669 }
1670
1671 /* Fetch config space registers address */
1672 if (of_address_to_resource(np, 0, &port->cfg_space)) {
1673 printk(KERN_ERR "%s: Can't get PCI-E config space !",
1674 np->full_name);
1675 return;
1676 }
1677 /* Fetch host bridge internal registers address */
1678 if (of_address_to_resource(np, 1, &port->utl_regs)) {
1679 printk(KERN_ERR "%s: Can't get UTL register base !",
1680 np->full_name);
1681 return;
1682 }
1683
1684 /* Map DCRs */
1685 dcrs = dcr_resource_start(np, 0);
1686 if (dcrs == 0) {
1687 printk(KERN_ERR "%s: Can't get DCR register base !",
1688 np->full_name);
1689 return;
1690 }
1691 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
1692
1693 /* Initialize the port specific registers */
1694 if (ppc4xx_pciex_port_init(port)) {
1695 printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index);
1696 return;
1697 }
1698
1699 /* Setup the linux hose data structure */
1700 ppc4xx_pciex_port_setup_hose(port);
1701 }
1702
1703 #endif /* CONFIG_PPC4xx_PCI_EXPRESS */
1704
1705 static int __init ppc4xx_pci_find_bridges(void)
1706 {
1707 struct device_node *np;
1708
1709 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
1710 for_each_compatible_node(np, NULL, "ibm,plb-pciex")
1711 ppc4xx_probe_pciex_bridge(np);
1712 #endif
1713 for_each_compatible_node(np, NULL, "ibm,plb-pcix")
1714 ppc4xx_probe_pcix_bridge(np);
1715 for_each_compatible_node(np, NULL, "ibm,plb-pci")
1716 ppc4xx_probe_pci_bridge(np);
1717
1718 return 0;
1719 }
1720 arch_initcall(ppc4xx_pci_find_bridges);
1721
Linux kernel - Deliverables
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