arch/ppc/kernel/head_4xx.S

   1 /*
   2  *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
   3  *      Initial PowerPC version.
   4  *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
   5  *      Rewritten for PReP
   6  *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
   7  *      Low-level exception handers, MMU support, and rewrite.
   8  *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
   9  *      PowerPC 8xx modifications.
  10  *    Copyright (c) 1998-1999 TiVo, Inc.
  11  *      PowerPC 403GCX modifications.
  12  *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
  13  *      PowerPC 403GCX/405GP modifications.
  14  *    Copyright 2000 MontaVista Software Inc.
  15  *      PPC405 modifications
  16  *      PowerPC 403GCX/405GP modifications.
  17  *      Author: MontaVista Software, Inc.
  18  *              frank_rowand@mvista.com or source@mvista.com
  19  *              debbie_chu@mvista.com
  20  *
  21  *
  22  *    Module name: head_4xx.S
  23  *
  24  *    Description:
  25  *      Kernel execution entry point code.
  26  *
  27  *    This program is free software; you can redistribute it and/or
  28  *    modify it under the terms of the GNU General Public License
  29  *    as published by the Free Software Foundation; either version
  30  *    2 of the License, or (at your option) any later version.
  31  *
  32  */
  33
  34 #include <linux/config.h>
  35 #include <asm/processor.h>
  36 #include <asm/page.h>
  37 #include <asm/mmu.h>
  38 #include <asm/pgtable.h>
  39 #include <asm/ibm4xx.h>
  40 #include <asm/cputable.h>
  41 #include <asm/thread_info.h>
  42 #include <asm/ppc_asm.h>
  43 #include <asm/offsets.h>
  44
  45 /* As with the other PowerPC ports, it is expected that when code
  46  * execution begins here, the following registers contain valid, yet
  47  * optional, information:
  48  *
  49  *   r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
  50  *   r4 - Starting address of the init RAM disk
  51  *   r5 - Ending address of the init RAM disk
  52  *   r6 - Start of kernel command line string (e.g. "mem=96m")
  53  *   r7 - End of kernel command line string
  54  *
  55  * This is all going to change RSN when we add bi_recs.......  -- Dan
  56  */
  57         .text
  58 _GLOBAL(_stext)
  59 _GLOBAL(_start)
  60
  61         /* Save parameters we are passed.
  62         */
  63         mr      r31,r3
  64         mr      r30,r4
  65         mr      r29,r5
  66         mr      r28,r6
  67         mr      r27,r7
  68
  69         /* We have to turn on the MMU right away so we get cache modes
  70          * set correctly.
  71          */
  72         bl      initial_mmu
  73
  74 /* We now have the lower 16 Meg mapped into TLB entries, and the caches
  75  * ready to work.
  76  */
  77 turn_on_mmu:
  78         lis     r0,MSR_KERNEL@h
  79         ori     r0,r0,MSR_KERNEL@l
  80         mtspr   SPRN_SRR1,r0
  81         lis     r0,start_here@h
  82         ori     r0,r0,start_here@l
  83         mtspr   SPRN_SRR0,r0
  84         SYNC
  85         rfi                             /* enables MMU */
  86         b       .                       /* prevent prefetch past rfi */
  87
  88 /*
  89  * This area is used for temporarily saving registers during the
  90  * critical exception prolog.
  91  */
  92         . = 0xc0
  93 crit_save:
  94 _GLOBAL(crit_r10)
  95         .space  4
  96 _GLOBAL(crit_r11)
  97         .space  4
  98
  99 /*
 100  * Exception vector entry code. This code runs with address translation
 101  * turned off (i.e. using physical addresses). We assume SPRG3 has the
 102  * physical address of the current task thread_struct.
 103  * Note that we have to have decremented r1 before we write to any fields
 104  * of the exception frame, since a critical interrupt could occur at any
 105  * time, and it will write to the area immediately below the current r1.
 106  */
 107 #define NORMAL_EXCEPTION_PROLOG                                              \
 108         mtspr   SPRN_SPRG0,r10;         /* save two registers to work with */\
 109         mtspr   SPRN_SPRG1,r11;                                              \
 110         mtspr   SPRN_SPRG2,r1;                                               \
 111         mfcr    r10;                    /* save CR in r10 for now          */\
 112         mfspr   r11,SPRN_SRR1;          /* check whether user or kernel    */\
 113         andi.   r11,r11,MSR_PR;                                              \
 114         beq     1f;                                                          \
 115         mfspr   r1,SPRN_SPRG3;          /* if from user, start at top of   */\
 116         lwz     r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack   */\
 117         addi    r1,r1,THREAD_SIZE;                                           \
 118 1:      subi    r1,r1,INT_FRAME_SIZE;   /* Allocate an exception frame     */\
 119         tophys(r11,r1);                                                      \
 120         stw     r10,_CCR(r11);          /* save various registers          */\
 121         stw     r12,GPR12(r11);                                              \
 122         stw     r9,GPR9(r11);                                                \
 123         mfspr   r10,SPRN_SPRG0;                                              \
 124         stw     r10,GPR10(r11);                                              \
 125         mfspr   r12,SPRN_SPRG1;                                              \
 126         stw     r12,GPR11(r11);                                              \
 127         mflr    r10;                                                         \
 128         stw     r10,_LINK(r11);                                              \
 129         mfspr   r10,SPRN_SPRG2;                                              \
 130         mfspr   r12,SPRN_SRR0;                                               \
 131         stw     r10,GPR1(r11);                                               \
 132         mfspr   r9,SPRN_SRR1;                                                \
 133         stw     r10,0(r11);                                                  \
 134         rlwinm  r9,r9,0,14,12;          /* clear MSR_WE (necessary?)       */\
 135         stw     r0,GPR0(r11);                                                \
 136         SAVE_4GPRS(3, r11);                                                  \
 137         SAVE_2GPRS(7, r11)
 138
 139 /*
 140  * Exception prolog for critical exceptions.  This is a little different
 141  * from the normal exception prolog above since a critical exception
 142  * can potentially occur at any point during normal exception processing.
 143  * Thus we cannot use the same SPRG registers as the normal prolog above.
 144  * Instead we use a couple of words of memory at low physical addresses.
 145  * This is OK since we don't support SMP on these processors.
 146  */
 147 #define CRITICAL_EXCEPTION_PROLOG                                            \
 148         stw     r10,crit_r10@l(0);      /* save two registers to work with */\
 149         stw     r11,crit_r11@l(0);                                           \
 150         mfcr    r10;                    /* save CR in r10 for now          */\
 151         mfspr   r11,SPRN_SRR3;          /* check whether user or kernel    */\
 152         andi.   r11,r11,MSR_PR;                                              \
 153         lis     r11,critical_stack_top@h;                                    \
 154         ori     r11,r11,critical_stack_top@l;                                \
 155         beq     1f;                                                          \
 156         /* COMING FROM USER MODE */                                          \
 157         mfspr   r11,SPRN_SPRG3;         /* if from user, start at top of   */\
 158         lwz     r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
 159         addi    r11,r11,THREAD_SIZE;                                         \
 160 1:      subi    r11,r11,INT_FRAME_SIZE; /* Allocate an exception frame     */\
 161         tophys(r11,r11);                                                     \
 162         stw     r10,_CCR(r11);          /* save various registers          */\
 163         stw     r12,GPR12(r11);                                              \
 164         stw     r9,GPR9(r11);                                                \
 165         mflr    r10;                                                         \
 166         stw     r10,_LINK(r11);                                              \
 167         mfspr   r12,SPRN_DEAR;          /* save DEAR and ESR in the frame  */\
 168         stw     r12,_DEAR(r11);         /* since they may have had stuff   */\
 169         mfspr   r9,SPRN_ESR;            /* in them at the point where the  */\
 170         stw     r9,_ESR(r11);           /* exception was taken             */\
 171         mfspr   r12,SPRN_SRR2;                                               \
 172         stw     r1,GPR1(r11);                                                \
 173         mfspr   r9,SPRN_SRR3;                                                \
 174         stw     r1,0(r11);                                                   \
 175         tovirt(r1,r11);                                                      \
 176         rlwinm  r9,r9,0,14,12;          /* clear MSR_WE (necessary?)       */\
 177         stw     r0,GPR0(r11);                                                \
 178         SAVE_4GPRS(3, r11);                                                  \
 179         SAVE_2GPRS(7, r11)
 180
 181         /*
 182          * State at this point:
 183          * r9 saved in stack frame, now saved SRR3 & ~MSR_WE
 184          * r10 saved in crit_r10 and in stack frame, trashed
 185          * r11 saved in crit_r11 and in stack frame,
 186          *      now phys stack/exception frame pointer
 187          * r12 saved in stack frame, now saved SRR2
 188          * CR saved in stack frame, CR0.EQ = !SRR3.PR
 189          * LR, DEAR, ESR in stack frame
 190          * r1 saved in stack frame, now virt stack/excframe pointer
 191          * r0, r3-r8 saved in stack frame
 192          */
 193
 194 /*
 195  * Exception vectors.
 196  */
 197 #define START_EXCEPTION(n, label)                                            \
 198         . = n;                                                               \
 199 label:
 200
 201 #define EXCEPTION(n, label, hdlr, xfer)                         \
 202         START_EXCEPTION(n, label);                              \
 203         NORMAL_EXCEPTION_PROLOG;                                \
 204         addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
 205         xfer(n, hdlr)
 206
 207 #define CRITICAL_EXCEPTION(n, label, hdlr)                      \
 208         START_EXCEPTION(n, label);                              \
 209         CRITICAL_EXCEPTION_PROLOG;                              \
 210         addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
 211         EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
 212                           NOCOPY, crit_transfer_to_handler,     \
 213                           ret_from_crit_exc)
 214
 215 #define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret)   \
 216         li      r10,trap;                                       \
 217         stw     r10,TRAP(r11);                                  \
 218         lis     r10,msr@h;                                      \
 219         ori     r10,r10,msr@l;                                  \
 220         copyee(r10, r9);                                        \
 221         bl      tfer;                                           \
 222         .long   hdlr;                                           \
 223         .long   ret
 224
 225 #define COPY_EE(d, s)           rlwimi d,s,0,16,16
 226 #define NOCOPY(d, s)
 227
 228 #define EXC_XFER_STD(n, hdlr)           \
 229         EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
 230                           ret_from_except_full)
 231
 232 #define EXC_XFER_LITE(n, hdlr)          \
 233         EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
 234                           ret_from_except)
 235
 236 #define EXC_XFER_EE(n, hdlr)            \
 237         EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
 238                           ret_from_except_full)
 239
 240 #define EXC_XFER_EE_LITE(n, hdlr)       \
 241         EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
 242                           ret_from_except)
 243
 244
 245 /*
 246  * 0x0100 - Critical Interrupt Exception
 247  */
 248         CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, UnknownException)
 249
 250 /*
 251  * 0x0200 - Machine Check Exception
 252  */
 253         CRITICAL_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
 254
 255 /*
 256  * 0x0300 - Data Storage Exception
 257  * This happens for just a few reasons.  U0 set (but we don't do that),
 258  * or zone protection fault (user violation, write to protected page).
 259  * If this is just an update of modified status, we do that quickly
 260  * and exit.  Otherwise, we call heavywight functions to do the work.
 261  */
 262         START_EXCEPTION(0x0300, DataStorage)
 263         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 264         mtspr   SPRN_SPRG1, r11
 265 #ifdef CONFIG_403GCX
 266         stw     r12, 0(r0)
 267         stw     r9, 4(r0)
 268         mfcr    r11
 269         mfspr   r12, SPRN_PID
 270         stw     r11, 8(r0)
 271         stw     r12, 12(r0)
 272 #else
 273         mtspr   SPRN_SPRG4, r12
 274         mtspr   SPRN_SPRG5, r9
 275         mfcr    r11
 276         mfspr   r12, SPRN_PID
 277         mtspr   SPRN_SPRG7, r11
 278         mtspr   SPRN_SPRG6, r12
 279 #endif
 280
 281         /* First, check if it was a zone fault (which means a user
 282         * tried to access a kernel or read-protected page - always
 283         * a SEGV).  All other faults here must be stores, so no
 284         * need to check ESR_DST as well. */
 285         mfspr   r10, SPRN_ESR
 286         andis.  r10, r10, ESR_DIZ@h
 287         bne     2f
 288
 289         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 290
 291         /* If we are faulting a kernel address, we have to use the
 292          * kernel page tables.
 293          */
 294         lis     r11, TASK_SIZE@h
 295         cmplw   r10, r11
 296         blt+    3f
 297         lis     r11, swapper_pg_dir@h
 298         ori     r11, r11, swapper_pg_dir@l
 299         li      r9, 0
 300         mtspr   SPRN_PID, r9            /* TLB will have 0 TID */
 301         b       4f
 302
 303         /* Get the PGD for the current thread.
 304          */
 305 3:
 306         mfspr   r11,SPRN_SPRG3
 307         lwz     r11,PGDIR(r11)
 308 4:
 309         tophys(r11, r11)
 310         rlwimi  r11, r10, 12, 20, 29    /* Create L1 (pgdir/pmd) address */
 311         lwz     r11, 0(r11)             /* Get L1 entry */
 312         rlwinm. r12, r11, 0, 0, 19      /* Extract L2 (pte) base address */
 313         beq     2f                      /* Bail if no table */
 314
 315         rlwimi  r12, r10, 22, 20, 29    /* Compute PTE address */
 316         lwz     r11, 0(r12)             /* Get Linux PTE */
 317
 318         andi.   r9, r11, _PAGE_RW       /* Is it writeable? */
 319         beq     2f                      /* Bail if not */
 320
 321         /* Update 'changed'.
 322         */
 323         ori     r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
 324         stw     r11, 0(r12)             /* Update Linux page table */
 325
 326         /* Most of the Linux PTE is ready to load into the TLB LO.
 327          * We set ZSEL, where only the LS-bit determines user access.
 328          * We set execute, because we don't have the granularity to
 329          * properly set this at the page level (Linux problem).
 330          * If shared is set, we cause a zero PID->TID load.
 331          * Many of these bits are software only.  Bits we don't set
 332          * here we (properly should) assume have the appropriate value.
 333          */
 334         li      r12, 0x0ce2
 335         andc    r11, r11, r12           /* Make sure 20, 21 are zero */
 336
 337         /* find the TLB index that caused the fault.  It has to be here.
 338         */
 339         tlbsx   r9, 0, r10
 340
 341         tlbwe   r11, r9, TLB_DATA               /* Load TLB LO */
 342
 343         /* Done...restore registers and get out of here.
 344         */
 345 #ifdef CONFIG_403GCX
 346         lwz     r12, 12(r0)
 347         lwz     r11, 8(r0)
 348         mtspr   SPRN_PID, r12
 349         mtcr    r11
 350         lwz     r9, 4(r0)
 351         lwz     r12, 0(r0)
 352 #else
 353         mfspr   r12, SPRN_SPRG6
 354         mfspr   r11, SPRN_SPRG7
 355         mtspr   SPRN_PID, r12
 356         mtcr    r11
 357         mfspr   r9, SPRN_SPRG5
 358         mfspr   r12, SPRN_SPRG4
 359 #endif
 360         mfspr   r11, SPRN_SPRG1
 361         mfspr   r10, SPRN_SPRG0
 362         PPC405_ERR77_SYNC
 363         rfi                     /* Should sync shadow TLBs */
 364         b       .               /* prevent prefetch past rfi */
 365
 366 2:
 367         /* The bailout.  Restore registers to pre-exception conditions
 368          * and call the heavyweights to help us out.
 369          */
 370 #ifdef CONFIG_403GCX
 371         lwz     r12, 12(r0)
 372         lwz     r11, 8(r0)
 373         mtspr   SPRN_PID, r12
 374         mtcr    r11
 375         lwz     r9, 4(r0)
 376         lwz     r12, 0(r0)
 377 #else
 378         mfspr   r12, SPRN_SPRG6
 379         mfspr   r11, SPRN_SPRG7
 380         mtspr   SPRN_PID, r12
 381         mtcr    r11
 382         mfspr   r9, SPRN_SPRG5
 383         mfspr   r12, SPRN_SPRG4
 384 #endif
 385         mfspr   r11, SPRN_SPRG1
 386         mfspr   r10, SPRN_SPRG0
 387         b       DataAccess
 388
 389 /*
 390  * 0x0400 - Instruction Storage Exception
 391  * This is caused by a fetch from non-execute or guarded pages.
 392  */
 393         START_EXCEPTION(0x0400, InstructionAccess)
 394         NORMAL_EXCEPTION_PROLOG
 395         mr      r4,r12                  /* Pass SRR0 as arg2 */
 396         li      r5,0                    /* Pass zero as arg3 */
 397         EXC_XFER_EE_LITE(0x400, handle_page_fault)
 398
 399 /* 0x0500 - External Interrupt Exception */
 400         EXCEPTION(0x0500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
 401
 402 /* 0x0600 - Alignment Exception */
 403         START_EXCEPTION(0x0600, Alignment)
 404         NORMAL_EXCEPTION_PROLOG
 405         mfspr   r4,SPRN_DEAR            /* Grab the DEAR and save it */
 406         stw     r4,_DEAR(r11)
 407         addi    r3,r1,STACK_FRAME_OVERHEAD
 408         EXC_XFER_EE(0x600, AlignmentException)
 409
 410 /* 0x0700 - Program Exception */
 411         START_EXCEPTION(0x0700, ProgramCheck)
 412         NORMAL_EXCEPTION_PROLOG
 413         mfspr   r4,SPRN_ESR             /* Grab the ESR and save it */
 414         stw     r4,_ESR(r11)
 415         addi    r3,r1,STACK_FRAME_OVERHEAD
 416         EXC_XFER_STD(0x700, ProgramCheckException)
 417
 418         EXCEPTION(0x0800, Trap_08, UnknownException, EXC_XFER_EE)
 419         EXCEPTION(0x0900, Trap_09, UnknownException, EXC_XFER_EE)
 420         EXCEPTION(0x0A00, Trap_0A, UnknownException, EXC_XFER_EE)
 421         EXCEPTION(0x0B00, Trap_0B, UnknownException, EXC_XFER_EE)
 422
 423 /* 0x0C00 - System Call Exception */
 424         START_EXCEPTION(0x0C00, SystemCall)
 425         NORMAL_EXCEPTION_PROLOG
 426         EXC_XFER_EE_LITE(0xc00, DoSyscall)
 427
 428         EXCEPTION(0x0D00, Trap_0D, UnknownException, EXC_XFER_EE)
 429         EXCEPTION(0x0E00, Trap_0E, UnknownException, EXC_XFER_EE)
 430         EXCEPTION(0x0F00, Trap_0F, UnknownException, EXC_XFER_EE)
 431
 432 /* 0x1000 - Programmable Interval Timer (PIT) Exception */
 433         START_EXCEPTION(0x1000, Decrementer)
 434         NORMAL_EXCEPTION_PROLOG
 435         lis     r0,TSR_PIS@h
 436         mtspr   SPRN_TSR,r0             /* Clear the PIT exception */
 437         addi    r3,r1,STACK_FRAME_OVERHEAD
 438         EXC_XFER_LITE(0x1000, timer_interrupt)
 439
 440 #if 0
 441 /* NOTE:
 442  * FIT and WDT handlers are not implemented yet.
 443  */
 444
 445 /* 0x1010 - Fixed Interval Timer (FIT) Exception
 446 */
 447         STND_EXCEPTION(0x1010,  FITException,           UnknownException)
 448
 449 /* 0x1020 - Watchdog Timer (WDT) Exception
 450 */
 451
 452         CRITICAL_EXCEPTION(0x1020, WDTException, UnknownException)
 453 #endif
 454
 455 /* 0x1100 - Data TLB Miss Exception
 456  * As the name implies, translation is not in the MMU, so search the
 457  * page tables and fix it.  The only purpose of this function is to
 458  * load TLB entries from the page table if they exist.
 459  */
 460         START_EXCEPTION(0x1100, DTLBMiss)
 461         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 462         mtspr   SPRN_SPRG1, r11
 463 #ifdef CONFIG_403GCX
 464         stw     r12, 0(r0)
 465         stw     r9, 4(r0)
 466         mfcr    r11
 467         mfspr   r12, SPRN_PID
 468         stw     r11, 8(r0)
 469         stw     r12, 12(r0)
 470 #else
 471         mtspr   SPRN_SPRG4, r12
 472         mtspr   SPRN_SPRG5, r9
 473         mfcr    r11
 474         mfspr   r12, SPRN_PID
 475         mtspr   SPRN_SPRG7, r11
 476         mtspr   SPRN_SPRG6, r12
 477 #endif
 478         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 479
 480         /* If we are faulting a kernel address, we have to use the
 481          * kernel page tables.
 482          */
 483         lis     r11, TASK_SIZE@h
 484         cmplw   r10, r11
 485         blt+    3f
 486         lis     r11, swapper_pg_dir@h
 487         ori     r11, r11, swapper_pg_dir@l
 488         li      r9, 0
 489         mtspr   SPRN_PID, r9            /* TLB will have 0 TID */
 490         b       4f
 491
 492         /* Get the PGD for the current thread.
 493          */
 494 3:
 495         mfspr   r11,SPRN_SPRG3
 496         lwz     r11,PGDIR(r11)
 497 4:
 498         tophys(r11, r11)
 499         rlwimi  r11, r10, 12, 20, 29    /* Create L1 (pgdir/pmd) address */
 500         lwz     r12, 0(r11)             /* Get L1 entry */
 501         andi.   r9, r12, _PMD_PRESENT   /* Check if it points to a PTE page */
 502         beq     2f                      /* Bail if no table */
 503
 504         rlwimi  r12, r10, 22, 20, 29    /* Compute PTE address */
 505         lwz     r11, 0(r12)             /* Get Linux PTE */
 506         andi.   r9, r11, _PAGE_PRESENT
 507         beq     5f
 508
 509         ori     r11, r11, _PAGE_ACCESSED
 510         stw     r11, 0(r12)
 511
 512         /* Create TLB tag.  This is the faulting address plus a static
 513          * set of bits.  These are size, valid, E, U0.
 514         */
 515         li      r12, 0x00c0
 516         rlwimi  r10, r12, 0, 20, 31
 517
 518         b       finish_tlb_load
 519
 520 2:      /* Check for possible large-page pmd entry */
 521         rlwinm. r9, r12, 2, 22, 24
 522         beq     5f
 523
 524         /* Create TLB tag.  This is the faulting address, plus a static
 525          * set of bits (valid, E, U0) plus the size from the PMD.
 526          */
 527         ori     r9, r9, 0x40
 528         rlwimi  r10, r9, 0, 20, 31
 529         mr      r11, r12
 530
 531         b       finish_tlb_load
 532
 533 5:
 534         /* The bailout.  Restore registers to pre-exception conditions
 535          * and call the heavyweights to help us out.
 536          */
 537 #ifdef CONFIG_403GCX
 538         lwz     r12, 12(r0)
 539         lwz     r11, 8(r0)
 540         mtspr   SPRN_PID, r12
 541         mtcr    r11
 542         lwz     r9, 4(r0)
 543         lwz     r12, 0(r0)
 544 #else
 545         mfspr   r12, SPRN_SPRG6
 546         mfspr   r11, SPRN_SPRG7
 547         mtspr   SPRN_PID, r12
 548         mtcr    r11
 549         mfspr   r9, SPRN_SPRG5
 550         mfspr   r12, SPRN_SPRG4
 551 #endif
 552         mfspr   r11, SPRN_SPRG1
 553         mfspr   r10, SPRN_SPRG0
 554         b       DataAccess
 555
 556 /* 0x1200 - Instruction TLB Miss Exception
 557  * Nearly the same as above, except we get our information from different
 558  * registers and bailout to a different point.
 559  */
 560         START_EXCEPTION(0x1200, ITLBMiss)
 561         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 562         mtspr   SPRN_SPRG1, r11
 563 #ifdef CONFIG_403GCX
 564         stw     r12, 0(r0)
 565         stw     r9, 4(r0)
 566         mfcr    r11
 567         mfspr   r12, SPRN_PID
 568         stw     r11, 8(r0)
 569         stw     r12, 12(r0)
 570 #else
 571         mtspr   SPRN_SPRG4, r12
 572         mtspr   SPRN_SPRG5, r9
 573         mfcr    r11
 574         mfspr   r12, SPRN_PID
 575         mtspr   SPRN_SPRG7, r11
 576         mtspr   SPRN_SPRG6, r12
 577 #endif
 578         mfspr   r10, SPRN_SRR0          /* Get faulting address */
 579
 580         /* If we are faulting a kernel address, we have to use the
 581          * kernel page tables.
 582          */
 583         lis     r11, TASK_SIZE@h
 584         cmplw   r10, r11
 585         blt+    3f
 586         lis     r11, swapper_pg_dir@h
 587         ori     r11, r11, swapper_pg_dir@l
 588         li      r9, 0
 589         mtspr   SPRN_PID, r9            /* TLB will have 0 TID */
 590         b       4f
 591
 592         /* Get the PGD for the current thread.
 593          */
 594 3:
 595         mfspr   r11,SPRN_SPRG3
 596         lwz     r11,PGDIR(r11)
 597 4:
 598         tophys(r11, r11)
 599         rlwimi  r11, r10, 12, 20, 29    /* Create L1 (pgdir/pmd) address */
 600         lwz     r12, 0(r11)             /* Get L1 entry */
 601         andi.   r9, r12, _PMD_PRESENT   /* Check if it points to a PTE page */
 602         beq     2f                      /* Bail if no table */
 603
 604         rlwimi  r12, r10, 22, 20, 29    /* Compute PTE address */
 605         lwz     r11, 0(r12)             /* Get Linux PTE */
 606         andi.   r9, r11, _PAGE_PRESENT
 607         beq     5f
 608
 609         ori     r11, r11, _PAGE_ACCESSED
 610         stw     r11, 0(r12)
 611
 612         /* Create TLB tag.  This is the faulting address plus a static
 613          * set of bits.  These are size, valid, E, U0.
 614         */
 615         li      r12, 0x00c0
 616         rlwimi  r10, r12, 0, 20, 31
 617
 618         b       finish_tlb_load
 619
 620 2:      /* Check for possible large-page pmd entry */
 621         rlwinm. r9, r12, 2, 22, 24
 622         beq     5f
 623
 624         /* Create TLB tag.  This is the faulting address, plus a static
 625          * set of bits (valid, E, U0) plus the size from the PMD.
 626          */
 627         ori     r9, r9, 0x40
 628         rlwimi  r10, r9, 0, 20, 31
 629         mr      r11, r12
 630
 631         b       finish_tlb_load
 632
 633 5:
 634         /* The bailout.  Restore registers to pre-exception conditions
 635          * and call the heavyweights to help us out.
 636          */
 637 #ifdef CONFIG_403GCX
 638         lwz     r12, 12(r0)
 639         lwz     r11, 8(r0)
 640         mtspr   SPRN_PID, r12
 641         mtcr    r11
 642         lwz     r9, 4(r0)
 643         lwz     r12, 0(r0)
 644 #else
 645         mfspr   r12, SPRN_SPRG6
 646         mfspr   r11, SPRN_SPRG7
 647         mtspr   SPRN_PID, r12
 648         mtcr    r11
 649         mfspr   r9, SPRN_SPRG5
 650         mfspr   r12, SPRN_SPRG4
 651 #endif
 652         mfspr   r11, SPRN_SPRG1
 653         mfspr   r10, SPRN_SPRG0
 654         b       InstructionAccess
 655
 656         EXCEPTION(0x1300, Trap_13, UnknownException, EXC_XFER_EE)
 657         EXCEPTION(0x1400, Trap_14, UnknownException, EXC_XFER_EE)
 658         EXCEPTION(0x1500, Trap_15, UnknownException, EXC_XFER_EE)
 659         EXCEPTION(0x1600, Trap_16, UnknownException, EXC_XFER_EE)
 660 #ifdef CONFIG_IBM405_ERR51
 661         /* 405GP errata 51 */
 662         START_EXCEPTION(0x1700, Trap_17)
 663         b DTLBMiss
 664 #else
 665         EXCEPTION(0x1700, Trap_17, UnknownException, EXC_XFER_EE)
 666 #endif
 667         EXCEPTION(0x1800, Trap_18, UnknownException, EXC_XFER_EE)
 668         EXCEPTION(0x1900, Trap_19, UnknownException, EXC_XFER_EE)
 669         EXCEPTION(0x1A00, Trap_1A, UnknownException, EXC_XFER_EE)
 670         EXCEPTION(0x1B00, Trap_1B, UnknownException, EXC_XFER_EE)
 671         EXCEPTION(0x1C00, Trap_1C, UnknownException, EXC_XFER_EE)
 672         EXCEPTION(0x1D00, Trap_1D, UnknownException, EXC_XFER_EE)
 673         EXCEPTION(0x1E00, Trap_1E, UnknownException, EXC_XFER_EE)
 674         EXCEPTION(0x1F00, Trap_1F, UnknownException, EXC_XFER_EE)
 675
 676 /* Check for a single step debug exception while in an exception
 677  * handler before state has been saved.  This is to catch the case
 678  * where an instruction that we are trying to single step causes
 679  * an exception (eg ITLB/DTLB miss) and thus the first instruction of
 680  * the exception handler generates a single step debug exception.
 681  *
 682  * If we get a debug trap on the first instruction of an exception handler,
 683  * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
 684  * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
 685  * The exception handler was handling a non-critical interrupt, so it will
 686  * save (and later restore) the MSR via SPRN_SRR1, which will still have
 687  * the MSR_DE bit set.
 688  */
 689         /* 0x2000 - Debug Exception */
 690         START_EXCEPTION(0x2000, DebugTrap)
 691         CRITICAL_EXCEPTION_PROLOG
 692
 693         /*
 694          * If this is a single step or branch-taken exception in an
 695          * exception entry sequence, it was probably meant to apply to
 696          * the code where the exception occurred (since exception entry
 697          * doesn't turn off DE automatically).  We simulate the effect
 698          * of turning off DE on entry to an exception handler by turning
 699          * off DE in the SRR3 value and clearing the debug status.
 700          */
 701         mfspr   r10,SPRN_DBSR           /* check single-step/branch taken */
 702         andis.  r10,r10,DBSR_IC@h
 703         beq+    2f
 704
 705         andi.   r10,r9,MSR_IR|MSR_PR    /* check supervisor + MMU off */
 706         beq     1f                      /* branch and fix it up */
 707
 708         mfspr   r10,SPRN_SRR2           /* Faulting instruction address */
 709         cmplwi  r10,0x2100
 710         bgt+    2f                      /* address above exception vectors */
 711
 712         /* here it looks like we got an inappropriate debug exception. */
 713 1:      rlwinm  r9,r9,0,~MSR_DE         /* clear DE in the SRR3 value */
 714         lis     r10,DBSR_IC@h           /* clear the IC event */
 715         mtspr   SPRN_DBSR,r10
 716         /* restore state and get out */
 717         lwz     r10,_CCR(r11)
 718         lwz     r0,GPR0(r11)
 719         lwz     r1,GPR1(r11)
 720         mtcrf   0x80,r10
 721         mtspr   SPRN_SRR2,r12
 722         mtspr   SPRN_SRR3,r9
 723         lwz     r9,GPR9(r11)
 724         lwz     r12,GPR12(r11)
 725         lwz     r10,crit_r10@l(0)
 726         lwz     r11,crit_r11@l(0)
 727         PPC405_ERR77_SYNC
 728         rfci
 729         b       .
 730
 731         /* continue normal handling for a critical exception... */
 732 2:      mfspr   r4,SPRN_DBSR
 733         addi    r3,r1,STACK_FRAME_OVERHEAD
 734         EXC_XFER_TEMPLATE(DebugException, 0x2002, \
 735                 (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
 736                 NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
 737
 738 /*
 739  * The other Data TLB exceptions bail out to this point
 740  * if they can't resolve the lightweight TLB fault.
 741  */
 742 DataAccess:
 743         NORMAL_EXCEPTION_PROLOG
 744         mfspr   r5,SPRN_ESR             /* Grab the ESR, save it, pass arg3 */
 745         stw     r5,_ESR(r11)
 746         mfspr   r4,SPRN_DEAR            /* Grab the DEAR, save it, pass arg2 */
 747         EXC_XFER_EE_LITE(0x300, handle_page_fault)
 748
 749 /* Other PowerPC processors, namely those derived from the 6xx-series
 750  * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved.
 751  * However, for the 4xx-series processors these are neither defined nor
 752  * reserved.
 753  */
 754
 755         /* Damn, I came up one instruction too many to fit into the
 756          * exception space :-).  Both the instruction and data TLB
 757          * miss get to this point to load the TLB.
 758          *      r10 - TLB_TAG value
 759          *      r11 - Linux PTE
 760          *      r12, r9 - avilable to use
 761          *      PID - loaded with proper value when we get here
 762          *      Upon exit, we reload everything and RFI.
 763          * Actually, it will fit now, but oh well.....a common place
 764          * to load the TLB.
 765          */
 766 tlb_4xx_index:
 767         .long   0
 768 finish_tlb_load:
 769         /* load the next available TLB index.
 770         */
 771         lwz     r9, tlb_4xx_index@l(0)
 772         addi    r9, r9, 1
 773         andi.   r9, r9, (PPC4XX_TLB_SIZE-1)
 774         stw     r9, tlb_4xx_index@l(0)
 775
 776 6:
 777         /*
 778          * Clear out the software-only bits in the PTE to generate the
 779          * TLB_DATA value.  These are the bottom 2 bits of the RPM, the
 780          * top 3 bits of the zone field, and M.
 781          */
 782         li      r12, 0x0ce2
 783         andc    r11, r11, r12
 784
 785         tlbwe   r11, r9, TLB_DATA               /* Load TLB LO */
 786         tlbwe   r10, r9, TLB_TAG                /* Load TLB HI */
 787
 788         /* Done...restore registers and get out of here.
 789         */
 790 #ifdef CONFIG_403GCX
 791         lwz     r12, 12(r0)
 792         lwz     r11, 8(r0)
 793         mtspr   SPRN_PID, r12
 794         mtcr    r11
 795         lwz     r9, 4(r0)
 796         lwz     r12, 0(r0)
 797 #else
 798         mfspr   r12, SPRN_SPRG6
 799         mfspr   r11, SPRN_SPRG7
 800         mtspr   SPRN_PID, r12
 801         mtcr    r11
 802         mfspr   r9, SPRN_SPRG5
 803         mfspr   r12, SPRN_SPRG4
 804 #endif
 805         mfspr   r11, SPRN_SPRG1
 806         mfspr   r10, SPRN_SPRG0
 807         PPC405_ERR77_SYNC
 808         rfi                     /* Should sync shadow TLBs */
 809         b       .               /* prevent prefetch past rfi */
 810
 811 /* extern void giveup_fpu(struct task_struct *prev)
 812  *
 813  * The PowerPC 4xx family of processors do not have an FPU, so this just
 814  * returns.
 815  */
 816 _GLOBAL(giveup_fpu)
 817         blr
 818
 819 /* This is where the main kernel code starts.
 820  */
 821 start_here:
 822
 823         /* ptr to current */
 824         lis     r2,init_task@h
 825         ori     r2,r2,init_task@l
 826
 827         /* ptr to phys current thread */
 828         tophys(r4,r2)
 829         addi    r4,r4,THREAD    /* init task's THREAD */
 830         mtspr   SPRN_SPRG3,r4
 831
 832         /* stack */
 833         lis     r1,init_thread_union@ha
 834         addi    r1,r1,init_thread_union@l
 835         li      r0,0
 836         stwu    r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
 837
 838         bl      early_init      /* We have to do this with MMU on */
 839
 840 /*
 841  * Decide what sort of machine this is and initialize the MMU.
 842  */
 843         mr      r3,r31
 844         mr      r4,r30
 845         mr      r5,r29
 846         mr      r6,r28
 847         mr      r7,r27
 848         bl      machine_init
 849         bl      MMU_init
 850
 851 /* Go back to running unmapped so we can load up new values
 852  * and change to using our exception vectors.
 853  * On the 4xx, all we have to do is invalidate the TLB to clear
 854  * the old 16M byte TLB mappings.
 855  */
 856         lis     r4,2f@h
 857         ori     r4,r4,2f@l
 858         tophys(r4,r4)
 859         lis     r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@h
 860         ori     r3,r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@l
 861         mtspr   SPRN_SRR0,r4
 862         mtspr   SPRN_SRR1,r3
 863         rfi
 864         b       .               /* prevent prefetch past rfi */
 865
 866 /* Load up the kernel context */
 867 2:
 868         sync                    /* Flush to memory before changing TLB */
 869         tlbia
 870         isync                   /* Flush shadow TLBs */
 871
 872         /* set up the PTE pointers for the Abatron bdiGDB.
 873         */
 874         lis     r6, swapper_pg_dir@h
 875         ori     r6, r6, swapper_pg_dir@l
 876         lis     r5, abatron_pteptrs@h
 877         ori     r5, r5, abatron_pteptrs@l
 878         stw     r5, 0xf0(r0)    /* Must match your Abatron config file */
 879         tophys(r5,r5)
 880         stw     r6, 0(r5)
 881
 882 /* Now turn on the MMU for real! */
 883         lis     r4,MSR_KERNEL@h
 884         ori     r4,r4,MSR_KERNEL@l
 885         lis     r3,start_kernel@h
 886         ori     r3,r3,start_kernel@l
 887         mtspr   SPRN_SRR0,r3
 888         mtspr   SPRN_SRR1,r4
 889         rfi                     /* enable MMU and jump to start_kernel */
 890         b       .               /* prevent prefetch past rfi */
 891
 892 /* Set up the initial MMU state so we can do the first level of
 893  * kernel initialization.  This maps the first 16 MBytes of memory 1:1
 894  * virtual to physical and more importantly sets the cache mode.
 895  */
 896 initial_mmu:
 897         tlbia                   /* Invalidate all TLB entries */
 898         isync
 899
 900         /* We should still be executing code at physical address 0x0000xxxx
 901          * at this point. However, start_here is at virtual address
 902          * 0xC000xxxx. So, set up a TLB mapping to cover this once
 903          * translation is enabled.
 904          */
 905
 906         lis     r3,KERNELBASE@h         /* Load the kernel virtual address */
 907         ori     r3,r3,KERNELBASE@l
 908         tophys(r4,r3)                   /* Load the kernel physical address */
 909
 910         iccci   r0,r3                   /* Invalidate the i-cache before use */
 911
 912         /* Load the kernel PID.
 913         */
 914         li      r0,0
 915         mtspr   SPRN_PID,r0
 916         sync
 917
 918         /* Configure and load two entries into TLB slots 62 and 63.
 919          * In case we are pinning TLBs, these are reserved in by the
 920          * other TLB functions.  If not reserving, then it doesn't
 921          * matter where they are loaded.
 922          */
 923         clrrwi  r4,r4,10                /* Mask off the real page number */
 924         ori     r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */
 925
 926         clrrwi  r3,r3,10                /* Mask off the effective page number */
 927         ori     r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M))
 928
 929         li      r0,63                    /* TLB slot 63 */
 930
 931         tlbwe   r4,r0,TLB_DATA          /* Load the data portion of the entry */
 932         tlbwe   r3,r0,TLB_TAG           /* Load the tag portion of the entry */
 933
 934 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(SERIAL_DEBUG_IO_BASE)
 935
 936         /* Load a TLB entry for the UART, so that ppc4xx_progress() can use
 937          * the UARTs nice and early.  We use a 4k real==virtual mapping. */
 938
 939         lis     r3,SERIAL_DEBUG_IO_BASE@h
 940         ori     r3,r3,SERIAL_DEBUG_IO_BASE@l
 941         mr      r4,r3
 942         clrrwi  r4,r4,12
 943         ori     r4,r4,(TLB_WR|TLB_I|TLB_M|TLB_G)
 944
 945         clrrwi  r3,r3,12
 946         ori     r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K))
 947
 948         li      r0,0                    /* TLB slot 0 */
 949         tlbwe   r4,r0,TLB_DATA
 950         tlbwe   r3,r0,TLB_TAG
 951 #endif /* CONFIG_SERIAL_DEBUG_TEXT && SERIAL_DEBUG_IO_BASE */
 952
 953         isync
 954
 955         /* Establish the exception vector base
 956         */
 957         lis     r4,KERNELBASE@h         /* EVPR only uses the high 16-bits */
 958         tophys(r0,r4)                   /* Use the physical address */
 959         mtspr   SPRN_EVPR,r0
 960
 961         blr
 962
 963 _GLOBAL(abort)
 964         mfspr   r13,SPRN_DBCR0
 965         oris    r13,r13,DBCR0_RST_SYSTEM@h
 966         mtspr   SPRN_DBCR0,r13
 967
 968 _GLOBAL(set_context)
 969
 970 #ifdef CONFIG_BDI_SWITCH
 971         /* Context switch the PTE pointer for the Abatron BDI2000.
 972          * The PGDIR is the second parameter.
 973          */
 974         lis     r5, KERNELBASE@h
 975         lwz     r5, 0xf0(r5)
 976         stw     r4, 0x4(r5)
 977 #endif
 978         sync
 979         mtspr   SPRN_PID,r3
 980         isync                           /* Need an isync to flush shadow */
 981                                         /* TLBs after changing PID */
 982         blr
 983
 984 /* We put a few things here that have to be page-aligned. This stuff
 985  * goes at the beginning of the data segment, which is page-aligned.
 986  */
 987         .data
 988 _GLOBAL(sdata)
 989 _GLOBAL(empty_zero_page)
 990         .space  4096
 991 _GLOBAL(swapper_pg_dir)
 992         .space  4096
 993
 994
 995 /* Stack for handling critical exceptions from kernel mode */
 996         .section .bss
 997         .align 12
 998 exception_stack_bottom:
 999         .space  4096
1000 critical_stack_top:
1001 _GLOBAL(exception_stack_top)
1002
1003 /* This space gets a copy of optional info passed to us by the bootstrap
1004  * which is used to pass parameters into the kernel like root=/dev/sda1, etc.
1005  */
1006 _GLOBAL(cmd_line)
1007         .space  512
1008
1009 /* Room for two PTE pointers, usually the kernel and current user pointers
1010  * to their respective root page table.
1011  */
1012 abatron_pteptrs:
1013         .space  8