arch/ppc/kernel/traps.c

   1 /*
   2  *  arch/ppc/kernel/traps.c
   3  *
   4  *  Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
   5  *
   6  *  This program is free software; you can redistribute it and/or
   7  *  modify it under the terms of the GNU General Public License
   8  *  as published by the Free Software Foundation; either version
   9  *  2 of the License, or (at your option) any later version.
  10  *
  11  *  Modified by Cort Dougan (cort@cs.nmt.edu)
  12  *  and Paul Mackerras (paulus@cs.anu.edu.au)
  13  */
  14
  15 /*
  16  * This file handles the architecture-dependent parts of hardware exceptions
  17  */
  18
  19 #include <linux/errno.h>
  20 #include <linux/sched.h>
  21 #include <linux/kernel.h>
  22 #include <linux/mm.h>
  23 #include <linux/stddef.h>
  24 #include <linux/unistd.h>
  25 #include <linux/ptrace.h>
  26 #include <linux/slab.h>
  27 #include <linux/user.h>
  28 #include <linux/a.out.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/config.h>
  31 #include <linux/init.h>
  32 #include <linux/module.h>
  33 #include <linux/prctl.h>
  34
  35 #include <asm/pgtable.h>
  36 #include <asm/uaccess.h>
  37 #include <asm/system.h>
  38 #include <asm/io.h>
  39 #include <asm/reg.h>
  40 #include <asm/xmon.h>
  41 #ifdef CONFIG_PMAC_BACKLIGHT
  42 #include <asm/backlight.h>
  43 #endif
  44 #include <asm/pmc.h>
  45
  46 #ifdef CONFIG_XMON
  47 extern int xmon_bpt(struct pt_regs *regs);
  48 extern int xmon_sstep(struct pt_regs *regs);
  49 extern int xmon_iabr_match(struct pt_regs *regs);
  50 extern int xmon_dabr_match(struct pt_regs *regs);
  51
  52 void (*debugger)(struct pt_regs *regs) = xmon;
  53 int (*debugger_bpt)(struct pt_regs *regs) = xmon_bpt;
  54 int (*debugger_sstep)(struct pt_regs *regs) = xmon_sstep;
  55 int (*debugger_iabr_match)(struct pt_regs *regs) = xmon_iabr_match;
  56 int (*debugger_dabr_match)(struct pt_regs *regs) = xmon_dabr_match;
  57 void (*debugger_fault_handler)(struct pt_regs *regs);
  58 #else
  59 #ifdef CONFIG_KGDB
  60 void (*debugger)(struct pt_regs *regs);
  61 int (*debugger_bpt)(struct pt_regs *regs);
  62 int (*debugger_sstep)(struct pt_regs *regs);
  63 int (*debugger_iabr_match)(struct pt_regs *regs);
  64 int (*debugger_dabr_match)(struct pt_regs *regs);
  65 void (*debugger_fault_handler)(struct pt_regs *regs);
  66 #else
  67 #define debugger(regs)                  do { } while (0)
  68 #define debugger_bpt(regs)              0
  69 #define debugger_sstep(regs)            0
  70 #define debugger_iabr_match(regs)       0
  71 #define debugger_dabr_match(regs)       0
  72 #define debugger_fault_handler          ((void (*)(struct pt_regs *))0)
  73 #endif
  74 #endif
  75
  76 /*
  77  * Trap & Exception support
  78  */
  79
  80 DEFINE_SPINLOCK(die_lock);
  81
  82 int die(const char * str, struct pt_regs * fp, long err)
  83 {
  84         static int die_counter;
  85         int nl = 0;
  86         console_verbose();
  87         spin_lock_irq(&die_lock);
  88 #ifdef CONFIG_PMAC_BACKLIGHT
  89         if (_machine == _MACH_Pmac) {
  90                 set_backlight_enable(1);
  91                 set_backlight_level(BACKLIGHT_MAX);
  92         }
  93 #endif
  94         printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
  95 #ifdef CONFIG_PREEMPT
  96         printk("PREEMPT ");
  97         nl = 1;
  98 #endif
  99 #ifdef CONFIG_SMP
 100         printk("SMP NR_CPUS=%d ", NR_CPUS);
 101         nl = 1;
 102 #endif
 103         if (nl)
 104                 printk("\n");
 105         show_regs(fp);
 106         spin_unlock_irq(&die_lock);
 107         /* do_exit() should take care of panic'ing from an interrupt
 108          * context so we don't handle it here
 109          */
 110         do_exit(err);
 111 }
 112
 113 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
 114 {
 115         siginfo_t info;
 116
 117         if (!user_mode(regs)) {
 118                 debugger(regs);
 119                 die("Exception in kernel mode", regs, signr);
 120         }
 121         info.si_signo = signr;
 122         info.si_errno = 0;
 123         info.si_code = code;
 124         info.si_addr = (void __user *) addr;
 125         force_sig_info(signr, &info, current);
 126
 127         /*
 128          * Init gets no signals that it doesn't have a handler for.
 129          * That's all very well, but if it has caused a synchronous
 130          * exception and we ignore the resulting signal, it will just
 131          * generate the same exception over and over again and we get
 132          * nowhere.  Better to kill it and let the kernel panic.
 133          */
 134         if (current->pid == 1) {
 135                 __sighandler_t handler;
 136
 137                 spin_lock_irq(&current->sighand->siglock);
 138                 handler = current->sighand->action[signr-1].sa.sa_handler;
 139                 spin_unlock_irq(&current->sighand->siglock);
 140                 if (handler == SIG_DFL) {
 141                         /* init has generated a synchronous exception
 142                            and it doesn't have a handler for the signal */
 143                         printk(KERN_CRIT "init has generated signal %d "
 144                                "but has no handler for it\n", signr);
 145                         do_exit(signr);
 146                 }
 147         }
 148 }
 149
 150 /*
 151  * I/O accesses can cause machine checks on powermacs.
 152  * Check if the NIP corresponds to the address of a sync
 153  * instruction for which there is an entry in the exception
 154  * table.
 155  * Note that the 601 only takes a machine check on TEA
 156  * (transfer error ack) signal assertion, and does not
 157  * set any of the top 16 bits of SRR1.
 158  *  -- paulus.
 159  */
 160 static inline int check_io_access(struct pt_regs *regs)
 161 {
 162 #ifdef CONFIG_PPC_PMAC
 163         unsigned long msr = regs->msr;
 164         const struct exception_table_entry *entry;
 165         unsigned int *nip = (unsigned int *)regs->nip;
 166
 167         if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
 168             && (entry = search_exception_tables(regs->nip)) != NULL) {
 169                 /*
 170                  * Check that it's a sync instruction, or somewhere
 171                  * in the twi; isync; nop sequence that inb/inw/inl uses.
 172                  * As the address is in the exception table
 173                  * we should be able to read the instr there.
 174                  * For the debug message, we look at the preceding
 175                  * load or store.
 176                  */
 177                 if (*nip == 0x60000000)         /* nop */
 178                         nip -= 2;
 179                 else if (*nip == 0x4c00012c)    /* isync */
 180                         --nip;
 181                 if (*nip == 0x7c0004ac || (*nip >> 26) == 3) {
 182                         /* sync or twi */
 183                         unsigned int rb;
 184
 185                         --nip;
 186                         rb = (*nip >> 11) & 0x1f;
 187                         printk(KERN_DEBUG "%s bad port %lx at %p\n",
 188                                (*nip & 0x100)? "OUT to": "IN from",
 189                                regs->gpr[rb] - _IO_BASE, nip);
 190                         regs->msr |= MSR_RI;
 191                         regs->nip = entry->fixup;
 192                         return 1;
 193                 }
 194         }
 195 #endif /* CONFIG_PPC_PMAC */
 196         return 0;
 197 }
 198
 199 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
 200 /* On 4xx, the reason for the machine check or program exception
 201    is in the ESR. */
 202 #define get_reason(regs)        ((regs)->dsisr)
 203 #ifndef CONFIG_FSL_BOOKE
 204 #define get_mc_reason(regs)     ((regs)->dsisr)
 205 #else
 206 #define get_mc_reason(regs)     (mfspr(SPRN_MCSR))
 207 #endif
 208 #define REASON_FP               ESR_FP
 209 #define REASON_ILLEGAL          (ESR_PIL | ESR_PUO)
 210 #define REASON_PRIVILEGED       ESR_PPR
 211 #define REASON_TRAP             ESR_PTR
 212
 213 /* single-step stuff */
 214 #define single_stepping(regs)   (current->thread.dbcr0 & DBCR0_IC)
 215 #define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC)
 216
 217 #else
 218 /* On non-4xx, the reason for the machine check or program
 219    exception is in the MSR. */
 220 #define get_reason(regs)        ((regs)->msr)
 221 #define get_mc_reason(regs)     ((regs)->msr)
 222 #define REASON_FP               0x100000
 223 #define REASON_ILLEGAL          0x80000
 224 #define REASON_PRIVILEGED       0x40000
 225 #define REASON_TRAP             0x20000
 226
 227 #define single_stepping(regs)   ((regs)->msr & MSR_SE)
 228 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
 229 #endif
 230
 231 /*
 232  * This is "fall-back" implementation for configurations
 233  * which don't provide platform-specific machine check info
 234  */
 235 void __attribute__ ((weak))
 236 platform_machine_check(struct pt_regs *regs)
 237 {
 238 }
 239
 240 void machine_check_exception(struct pt_regs *regs)
 241 {
 242         unsigned long reason = get_mc_reason(regs);
 243
 244         if (user_mode(regs)) {
 245                 regs->msr |= MSR_RI;
 246                 _exception(SIGBUS, regs, BUS_ADRERR, regs->nip);
 247                 return;
 248         }
 249
 250 #if defined(CONFIG_8xx) && defined(CONFIG_PCI)
 251         /* the qspan pci read routines can cause machine checks -- Cort */
 252         bad_page_fault(regs, regs->dar, SIGBUS);
 253         return;
 254 #endif
 255
 256         if (debugger_fault_handler) {
 257                 debugger_fault_handler(regs);
 258                 regs->msr |= MSR_RI;
 259                 return;
 260         }
 261
 262         if (check_io_access(regs))
 263                 return;
 264
 265 #if defined(CONFIG_4xx) && !defined(CONFIG_440A)
 266         if (reason & ESR_IMCP) {
 267                 printk("Instruction");
 268                 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
 269         } else
 270                 printk("Data");
 271         printk(" machine check in kernel mode.\n");
 272 #elif defined(CONFIG_440A)
 273         printk("Machine check in kernel mode.\n");
 274         if (reason & ESR_IMCP){
 275                 printk("Instruction Synchronous Machine Check exception\n");
 276                 mtspr(SPRN_ESR, reason & ~ESR_IMCP);
 277         }
 278         else {
 279                 u32 mcsr = mfspr(SPRN_MCSR);
 280                 if (mcsr & MCSR_IB)
 281                         printk("Instruction Read PLB Error\n");
 282                 if (mcsr & MCSR_DRB)
 283                         printk("Data Read PLB Error\n");
 284                 if (mcsr & MCSR_DWB)
 285                         printk("Data Write PLB Error\n");
 286                 if (mcsr & MCSR_TLBP)
 287                         printk("TLB Parity Error\n");
 288                 if (mcsr & MCSR_ICP){
 289                         flush_instruction_cache();
 290                         printk("I-Cache Parity Error\n");
 291                 }
 292                 if (mcsr & MCSR_DCSP)
 293                         printk("D-Cache Search Parity Error\n");
 294                 if (mcsr & MCSR_DCFP)
 295                         printk("D-Cache Flush Parity Error\n");
 296                 if (mcsr & MCSR_IMPE)
 297                         printk("Machine Check exception is imprecise\n");
 298
 299                 /* Clear MCSR */
 300                 mtspr(SPRN_MCSR, mcsr);
 301         }
 302 #elif defined (CONFIG_E500)
 303         printk("Machine check in kernel mode.\n");
 304         printk("Caused by (from MCSR=%lx): ", reason);
 305
 306         if (reason & MCSR_MCP)
 307                 printk("Machine Check Signal\n");
 308         if (reason & MCSR_ICPERR)
 309                 printk("Instruction Cache Parity Error\n");
 310         if (reason & MCSR_DCP_PERR)
 311                 printk("Data Cache Push Parity Error\n");
 312         if (reason & MCSR_DCPERR)
 313                 printk("Data Cache Parity Error\n");
 314         if (reason & MCSR_GL_CI)
 315                 printk("Guarded Load or Cache-Inhibited stwcx.\n");
 316         if (reason & MCSR_BUS_IAERR)
 317                 printk("Bus - Instruction Address Error\n");
 318         if (reason & MCSR_BUS_RAERR)
 319                 printk("Bus - Read Address Error\n");
 320         if (reason & MCSR_BUS_WAERR)
 321                 printk("Bus - Write Address Error\n");
 322         if (reason & MCSR_BUS_IBERR)
 323                 printk("Bus - Instruction Data Error\n");
 324         if (reason & MCSR_BUS_RBERR)
 325                 printk("Bus - Read Data Bus Error\n");
 326         if (reason & MCSR_BUS_WBERR)
 327                 printk("Bus - Read Data Bus Error\n");
 328         if (reason & MCSR_BUS_IPERR)
 329                 printk("Bus - Instruction Parity Error\n");
 330         if (reason & MCSR_BUS_RPERR)
 331                 printk("Bus - Read Parity Error\n");
 332 #elif defined (CONFIG_E200)
 333         printk("Machine check in kernel mode.\n");
 334         printk("Caused by (from MCSR=%lx): ", reason);
 335
 336         if (reason & MCSR_MCP)
 337                 printk("Machine Check Signal\n");
 338         if (reason & MCSR_CP_PERR)
 339                 printk("Cache Push Parity Error\n");
 340         if (reason & MCSR_CPERR)
 341                 printk("Cache Parity Error\n");
 342         if (reason & MCSR_EXCP_ERR)
 343                 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
 344         if (reason & MCSR_BUS_IRERR)
 345                 printk("Bus - Read Bus Error on instruction fetch\n");
 346         if (reason & MCSR_BUS_DRERR)
 347                 printk("Bus - Read Bus Error on data load\n");
 348         if (reason & MCSR_BUS_WRERR)
 349                 printk("Bus - Write Bus Error on buffered store or cache line push\n");
 350 #else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */
 351         printk("Machine check in kernel mode.\n");
 352         printk("Caused by (from SRR1=%lx): ", reason);
 353         switch (reason & 0x601F0000) {
 354         case 0x80000:
 355                 printk("Machine check signal\n");
 356                 break;
 357         case 0:         /* for 601 */
 358         case 0x40000:
 359         case 0x140000:  /* 7450 MSS error and TEA */
 360                 printk("Transfer error ack signal\n");
 361                 break;
 362         case 0x20000:
 363                 printk("Data parity error signal\n");
 364                 break;
 365         case 0x10000:
 366                 printk("Address parity error signal\n");
 367                 break;
 368         case 0x20000000:
 369                 printk("L1 Data Cache error\n");
 370                 break;
 371         case 0x40000000:
 372                 printk("L1 Instruction Cache error\n");
 373                 break;
 374         case 0x00100000:
 375                 printk("L2 data cache parity error\n");
 376                 break;
 377         default:
 378                 printk("Unknown values in msr\n");
 379         }
 380 #endif /* CONFIG_4xx */
 381
 382         /*
 383          * Optional platform-provided routine to print out
 384          * additional info, e.g. bus error registers.
 385          */
 386         platform_machine_check(regs);
 387
 388         debugger(regs);
 389         die("machine check", regs, SIGBUS);
 390 }
 391
 392 void SMIException(struct pt_regs *regs)
 393 {
 394         debugger(regs);
 395 #if !(defined(CONFIG_XMON) || defined(CONFIG_KGDB))
 396         show_regs(regs);
 397         panic("System Management Interrupt");
 398 #endif
 399 }
 400
 401 void unknown_exception(struct pt_regs *regs)
 402 {
 403         printk("Bad trap at PC: %lx, MSR: %lx, vector=%lx    %s\n",
 404                regs->nip, regs->msr, regs->trap, print_tainted());
 405         _exception(SIGTRAP, regs, 0, 0);
 406 }
 407
 408 void instruction_breakpoint_exception(struct pt_regs *regs)
 409 {
 410         if (debugger_iabr_match(regs))
 411                 return;
 412         _exception(SIGTRAP, regs, TRAP_BRKPT, 0);
 413 }
 414
 415 void RunModeException(struct pt_regs *regs)
 416 {
 417         _exception(SIGTRAP, regs, 0, 0);
 418 }
 419
 420 /* Illegal instruction emulation support.  Originally written to
 421  * provide the PVR to user applications using the mfspr rd, PVR.
 422  * Return non-zero if we can't emulate, or -EFAULT if the associated
 423  * memory access caused an access fault.  Return zero on success.
 424  *
 425  * There are a couple of ways to do this, either "decode" the instruction
 426  * or directly match lots of bits.  In this case, matching lots of
 427  * bits is faster and easier.
 428  *
 429  */
 430 #define INST_MFSPR_PVR          0x7c1f42a6
 431 #define INST_MFSPR_PVR_MASK     0xfc1fffff
 432
 433 #define INST_DCBA               0x7c0005ec
 434 #define INST_DCBA_MASK          0x7c0007fe
 435
 436 #define INST_MCRXR              0x7c000400
 437 #define INST_MCRXR_MASK         0x7c0007fe
 438
 439 #define INST_STRING             0x7c00042a
 440 #define INST_STRING_MASK        0x7c0007fe
 441 #define INST_STRING_GEN_MASK    0x7c00067e
 442 #define INST_LSWI               0x7c0004aa
 443 #define INST_LSWX               0x7c00042a
 444 #define INST_STSWI              0x7c0005aa
 445 #define INST_STSWX              0x7c00052a
 446
 447 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
 448 {
 449         u8 rT = (instword >> 21) & 0x1f;
 450         u8 rA = (instword >> 16) & 0x1f;
 451         u8 NB_RB = (instword >> 11) & 0x1f;
 452         u32 num_bytes;
 453         unsigned long EA;
 454         int pos = 0;
 455
 456         /* Early out if we are an invalid form of lswx */
 457         if ((instword & INST_STRING_MASK) == INST_LSWX)
 458                 if ((rT == rA) || (rT == NB_RB))
 459                         return -EINVAL;
 460
 461         EA = (rA == 0) ? 0 : regs->gpr[rA];
 462
 463         switch (instword & INST_STRING_MASK) {
 464                 case INST_LSWX:
 465                 case INST_STSWX:
 466                         EA += NB_RB;
 467                         num_bytes = regs->xer & 0x7f;
 468                         break;
 469                 case INST_LSWI:
 470                 case INST_STSWI:
 471                         num_bytes = (NB_RB == 0) ? 32 : NB_RB;
 472                         break;
 473                 default:
 474                         return -EINVAL;
 475         }
 476
 477         while (num_bytes != 0)
 478         {
 479                 u8 val;
 480                 u32 shift = 8 * (3 - (pos & 0x3));
 481
 482                 switch ((instword & INST_STRING_MASK)) {
 483                         case INST_LSWX:
 484                         case INST_LSWI:
 485                                 if (get_user(val, (u8 __user *)EA))
 486                                         return -EFAULT;
 487                                 /* first time updating this reg,
 488                                  * zero it out */
 489                                 if (pos == 0)
 490                                         regs->gpr[rT] = 0;
 491                                 regs->gpr[rT] |= val << shift;
 492                                 break;
 493                         case INST_STSWI:
 494                         case INST_STSWX:
 495                                 val = regs->gpr[rT] >> shift;
 496                                 if (put_user(val, (u8 __user *)EA))
 497                                         return -EFAULT;
 498                                 break;
 499                 }
 500                 /* move EA to next address */
 501                 EA += 1;
 502                 num_bytes--;
 503
 504                 /* manage our position within the register */
 505                 if (++pos == 4) {
 506                         pos = 0;
 507                         if (++rT == 32)
 508                                 rT = 0;
 509                 }
 510         }
 511
 512         return 0;
 513 }
 514
 515 static int emulate_instruction(struct pt_regs *regs)
 516 {
 517         u32 instword;
 518         u32 rd;
 519
 520         if (!user_mode(regs))
 521                 return -EINVAL;
 522         CHECK_FULL_REGS(regs);
 523
 524         if (get_user(instword, (u32 __user *)(regs->nip)))
 525                 return -EFAULT;
 526
 527         /* Emulate the mfspr rD, PVR.
 528          */
 529         if ((instword & INST_MFSPR_PVR_MASK) == INST_MFSPR_PVR) {
 530                 rd = (instword >> 21) & 0x1f;
 531                 regs->gpr[rd] = mfspr(SPRN_PVR);
 532                 return 0;
 533         }
 534
 535         /* Emulating the dcba insn is just a no-op.  */
 536         if ((instword & INST_DCBA_MASK) == INST_DCBA)
 537                 return 0;
 538
 539         /* Emulate the mcrxr insn.  */
 540         if ((instword & INST_MCRXR_MASK) == INST_MCRXR) {
 541                 int shift = (instword >> 21) & 0x1c;
 542                 unsigned long msk = 0xf0000000UL >> shift;
 543
 544                 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
 545                 regs->xer &= ~0xf0000000UL;
 546                 return 0;
 547         }
 548
 549         /* Emulate load/store string insn. */
 550         if ((instword & INST_STRING_GEN_MASK) == INST_STRING)
 551                 return emulate_string_inst(regs, instword);
 552
 553         return -EINVAL;
 554 }
 555
 556 /*
 557  * After we have successfully emulated an instruction, we have to
 558  * check if the instruction was being single-stepped, and if so,
 559  * pretend we got a single-step exception.  This was pointed out
 560  * by Kumar Gala.  -- paulus
 561  */
 562 static void emulate_single_step(struct pt_regs *regs)
 563 {
 564         if (single_stepping(regs)) {
 565                 clear_single_step(regs);
 566                 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
 567         }
 568 }
 569
 570 /*
 571  * Look through the list of trap instructions that are used for BUG(),
 572  * BUG_ON() and WARN_ON() and see if we hit one.  At this point we know
 573  * that the exception was caused by a trap instruction of some kind.
 574  * Returns 1 if we should continue (i.e. it was a WARN_ON) or 0
 575  * otherwise.
 576  */
 577 extern struct bug_entry __start___bug_table[], __stop___bug_table[];
 578
 579 #ifndef CONFIG_MODULES
 580 #define module_find_bug(x)      NULL
 581 #endif
 582
 583 struct bug_entry *find_bug(unsigned long bugaddr)
 584 {
 585         struct bug_entry *bug;
 586
 587         for (bug = __start___bug_table; bug < __stop___bug_table; ++bug)
 588                 if (bugaddr == bug->bug_addr)
 589                         return bug;
 590         return module_find_bug(bugaddr);
 591 }
 592
 593 int check_bug_trap(struct pt_regs *regs)
 594 {
 595         struct bug_entry *bug;
 596         unsigned long addr;
 597
 598         if (regs->msr & MSR_PR)
 599                 return 0;       /* not in kernel */
 600         addr = regs->nip;       /* address of trap instruction */
 601         if (addr < PAGE_OFFSET)
 602                 return 0;
 603         bug = find_bug(regs->nip);
 604         if (bug == NULL)
 605                 return 0;
 606         if (bug->line & BUG_WARNING_TRAP) {
 607                 /* this is a WARN_ON rather than BUG/BUG_ON */
 608 #ifdef CONFIG_XMON
 609                 xmon_printf(KERN_ERR "Badness in %s at %s:%d\n",
 610                        bug->function, bug->file,
 611                        bug->line & ~BUG_WARNING_TRAP);
 612 #endif /* CONFIG_XMON */
 613                 printk(KERN_ERR "Badness in %s at %s:%d\n",
 614                        bug->function, bug->file,
 615                        bug->line & ~BUG_WARNING_TRAP);
 616                 dump_stack();
 617                 return 1;
 618         }
 619 #ifdef CONFIG_XMON
 620         xmon_printf(KERN_CRIT "kernel BUG in %s at %s:%d!\n",
 621                bug->function, bug->file, bug->line);
 622         xmon(regs);
 623 #endif /* CONFIG_XMON */
 624         printk(KERN_CRIT "kernel BUG in %s at %s:%d!\n",
 625                bug->function, bug->file, bug->line);
 626
 627         return 0;
 628 }
 629
 630 void program_check_exception(struct pt_regs *regs)
 631 {
 632         unsigned int reason = get_reason(regs);
 633         extern int do_mathemu(struct pt_regs *regs);
 634
 635 #ifdef CONFIG_MATH_EMULATION
 636         /* (reason & REASON_ILLEGAL) would be the obvious thing here,
 637          * but there seems to be a hardware bug on the 405GP (RevD)
 638          * that means ESR is sometimes set incorrectly - either to
 639          * ESR_DST (!?) or 0.  In the process of chasing this with the
 640          * hardware people - not sure if it can happen on any illegal
 641          * instruction or only on FP instructions, whether there is a
 642          * pattern to occurences etc. -dgibson 31/Mar/2003 */
 643         if (!(reason & REASON_TRAP) && do_mathemu(regs) == 0) {
 644                 emulate_single_step(regs);
 645                 return;
 646         }
 647 #endif /* CONFIG_MATH_EMULATION */
 648
 649         if (reason & REASON_FP) {
 650                 /* IEEE FP exception */
 651                 int code = 0;
 652                 u32 fpscr;
 653
 654                 /* We must make sure the FP state is consistent with
 655                  * our MSR_FP in regs
 656                  */
 657                 preempt_disable();
 658                 if (regs->msr & MSR_FP)
 659                         giveup_fpu(current);
 660                 preempt_enable();
 661
 662                 fpscr = current->thread.fpscr;
 663                 fpscr &= fpscr << 22;   /* mask summary bits with enables */
 664                 if (fpscr & FPSCR_VX)
 665                         code = FPE_FLTINV;
 666                 else if (fpscr & FPSCR_OX)
 667                         code = FPE_FLTOVF;
 668                 else if (fpscr & FPSCR_UX)
 669                         code = FPE_FLTUND;
 670                 else if (fpscr & FPSCR_ZX)
 671                         code = FPE_FLTDIV;
 672                 else if (fpscr & FPSCR_XX)
 673                         code = FPE_FLTRES;
 674                 _exception(SIGFPE, regs, code, regs->nip);
 675                 return;
 676         }
 677
 678         if (reason & REASON_TRAP) {
 679                 /* trap exception */
 680                 if (debugger_bpt(regs))
 681                         return;
 682                 if (check_bug_trap(regs)) {
 683                         regs->nip += 4;
 684                         return;
 685                 }
 686                 _exception(SIGTRAP, regs, TRAP_BRKPT, 0);
 687                 return;
 688         }
 689
 690         /* Try to emulate it if we should. */
 691         if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
 692                 switch (emulate_instruction(regs)) {
 693                 case 0:
 694                         regs->nip += 4;
 695                         emulate_single_step(regs);
 696                         return;
 697                 case -EFAULT:
 698                         _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
 699                         return;
 700                 }
 701         }
 702
 703         if (reason & REASON_PRIVILEGED)
 704                 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
 705         else
 706                 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
 707 }
 708
 709 void single_step_exception(struct pt_regs *regs)
 710 {
 711         regs->msr &= ~(MSR_SE | MSR_BE);  /* Turn off 'trace' bits */
 712         if (debugger_sstep(regs))
 713                 return;
 714         _exception(SIGTRAP, regs, TRAP_TRACE, 0);
 715 }
 716
 717 void alignment_exception(struct pt_regs *regs)
 718 {
 719         int fixed;
 720
 721         fixed = fix_alignment(regs);
 722         if (fixed == 1) {
 723                 regs->nip += 4; /* skip over emulated instruction */
 724                 emulate_single_step(regs);
 725                 return;
 726         }
 727         if (fixed == -EFAULT) {
 728                 /* fixed == -EFAULT means the operand address was bad */
 729                 if (user_mode(regs))
 730                         _exception(SIGSEGV, regs, SEGV_ACCERR, regs->dar);
 731                 else
 732                         bad_page_fault(regs, regs->dar, SIGSEGV);
 733                 return;
 734         }
 735         _exception(SIGBUS, regs, BUS_ADRALN, regs->dar);
 736 }
 737
 738 void StackOverflow(struct pt_regs *regs)
 739 {
 740         printk(KERN_CRIT "Kernel stack overflow in process %p, r1=%lx\n",
 741                current, regs->gpr[1]);
 742         debugger(regs);
 743         show_regs(regs);
 744         panic("kernel stack overflow");
 745 }
 746
 747 void nonrecoverable_exception(struct pt_regs *regs)
 748 {
 749         printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
 750                regs->nip, regs->msr);
 751         debugger(regs);
 752         die("nonrecoverable exception", regs, SIGKILL);
 753 }
 754
 755 void trace_syscall(struct pt_regs *regs)
 756 {
 757         printk("Task: %p(%d), PC: %08lX/%08lX, Syscall: %3ld, Result: %s%ld    %s\n",
 758                current, current->pid, regs->nip, regs->link, regs->gpr[0],
 759                regs->ccr&0x10000000?"Error=":"", regs->gpr[3], print_tainted());
 760 }
 761
 762 #ifdef CONFIG_8xx
 763 void SoftwareEmulation(struct pt_regs *regs)
 764 {
 765         extern int do_mathemu(struct pt_regs *);
 766         extern int Soft_emulate_8xx(struct pt_regs *);
 767         int errcode;
 768
 769         CHECK_FULL_REGS(regs);
 770
 771         if (!user_mode(regs)) {
 772                 debugger(regs);
 773                 die("Kernel Mode Software FPU Emulation", regs, SIGFPE);
 774         }
 775
 776 #ifdef CONFIG_MATH_EMULATION
 777         errcode = do_mathemu(regs);
 778 #else
 779         errcode = Soft_emulate_8xx(regs);
 780 #endif
 781         if (errcode) {
 782                 if (errcode > 0)
 783                         _exception(SIGFPE, regs, 0, 0);
 784                 else if (errcode == -EFAULT)
 785                         _exception(SIGSEGV, regs, 0, 0);
 786                 else
 787                         _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
 788         } else
 789                 emulate_single_step(regs);
 790 }
 791 #endif /* CONFIG_8xx */
 792
 793 #if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
 794
 795 void DebugException(struct pt_regs *regs, unsigned long debug_status)
 796 {
 797         if (debug_status & DBSR_IC) {   /* instruction completion */
 798                 regs->msr &= ~MSR_DE;
 799                 if (user_mode(regs)) {
 800                         current->thread.dbcr0 &= ~DBCR0_IC;
 801                 } else {
 802                         /* Disable instruction completion */
 803                         mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
 804                         /* Clear the instruction completion event */
 805                         mtspr(SPRN_DBSR, DBSR_IC);
 806                         if (debugger_sstep(regs))
 807                                 return;
 808                 }
 809                 _exception(SIGTRAP, regs, TRAP_TRACE, 0);
 810         }
 811 }
 812 #endif /* CONFIG_4xx || CONFIG_BOOKE */
 813
 814 #if !defined(CONFIG_TAU_INT)
 815 void TAUException(struct pt_regs *regs)
 816 {
 817         printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx    %s\n",
 818                regs->nip, regs->msr, regs->trap, print_tainted());
 819 }
 820 #endif /* CONFIG_INT_TAU */
 821
 822 /*
 823  * FP unavailable trap from kernel - print a message, but let
 824  * the task use FP in the kernel until it returns to user mode.
 825  */
 826 void kernel_fp_unavailable_exception(struct pt_regs *regs)
 827 {
 828         regs->msr |= MSR_FP;
 829         printk(KERN_ERR "floating point used in kernel (task=%p, pc=%lx)\n",
 830                current, regs->nip);
 831 }
 832
 833 void altivec_unavailable_exception(struct pt_regs *regs)
 834 {
 835         static int kernel_altivec_count;
 836
 837 #ifndef CONFIG_ALTIVEC
 838         if (user_mode(regs)) {
 839                 /* A user program has executed an altivec instruction,
 840                    but this kernel doesn't support altivec. */
 841                 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
 842                 return;
 843         }
 844 #endif
 845         /* The kernel has executed an altivec instruction without
 846            first enabling altivec.  Whinge but let it do it. */
 847         if (++kernel_altivec_count < 10)
 848                 printk(KERN_ERR "AltiVec used in kernel (task=%p, pc=%lx)\n",
 849                        current, regs->nip);
 850         regs->msr |= MSR_VEC;
 851 }
 852
 853 #ifdef CONFIG_ALTIVEC
 854 void altivec_assist_exception(struct pt_regs *regs)
 855 {
 856         int err;
 857
 858         preempt_disable();
 859         if (regs->msr & MSR_VEC)
 860                 giveup_altivec(current);
 861         preempt_enable();
 862         if (!user_mode(regs)) {
 863                 printk(KERN_ERR "altivec assist exception in kernel mode"
 864                        " at %lx\n", regs->nip);
 865                 debugger(regs);
 866                 die("altivec assist exception", regs, SIGFPE);
 867                 return;
 868         }
 869
 870         err = emulate_altivec(regs);
 871         if (err == 0) {
 872                 regs->nip += 4;         /* skip emulated instruction */
 873                 emulate_single_step(regs);
 874                 return;
 875         }
 876
 877         if (err == -EFAULT) {
 878                 /* got an error reading the instruction */
 879                 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
 880         } else {
 881                 /* didn't recognize the instruction */
 882                 /* XXX quick hack for now: set the non-Java bit in the VSCR */
 883                 printk(KERN_ERR "unrecognized altivec instruction "
 884                        "in %s at %lx\n", current->comm, regs->nip);
 885                 current->thread.vscr.u[3] |= 0x10000;
 886         }
 887 }
 888 #endif /* CONFIG_ALTIVEC */
 889
 890 #ifdef CONFIG_E500
 891 void performance_monitor_exception(struct pt_regs *regs)
 892 {
 893         perf_irq(regs);
 894 }
 895 #endif
 896
 897 #ifdef CONFIG_FSL_BOOKE
 898 void CacheLockingException(struct pt_regs *regs, unsigned long address,
 899                            unsigned long error_code)
 900 {
 901         /* We treat cache locking instructions from the user
 902          * as priv ops, in the future we could try to do
 903          * something smarter
 904          */
 905         if (error_code & (ESR_DLK|ESR_ILK))
 906                 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
 907         return;
 908 }
 909 #endif /* CONFIG_FSL_BOOKE */
 910
 911 #ifdef CONFIG_SPE
 912 void SPEFloatingPointException(struct pt_regs *regs)
 913 {
 914         unsigned long spefscr;
 915         int fpexc_mode;
 916         int code = 0;
 917
 918         spefscr = current->thread.spefscr;
 919         fpexc_mode = current->thread.fpexc_mode;
 920
 921         /* Hardware does not neccessarily set sticky
 922          * underflow/overflow/invalid flags */
 923         if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
 924                 code = FPE_FLTOVF;
 925                 spefscr |= SPEFSCR_FOVFS;
 926         }
 927         else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
 928                 code = FPE_FLTUND;
 929                 spefscr |= SPEFSCR_FUNFS;
 930         }
 931         else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
 932                 code = FPE_FLTDIV;
 933         else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
 934                 code = FPE_FLTINV;
 935                 spefscr |= SPEFSCR_FINVS;
 936         }
 937         else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
 938                 code = FPE_FLTRES;
 939
 940         current->thread.spefscr = spefscr;
 941
 942         _exception(SIGFPE, regs, code, regs->nip);
 943         return;
 944 }
 945 #endif
 946
 947 #ifdef CONFIG_BOOKE_WDT
 948 /*
 949  * Default handler for a Watchdog exception,
 950  * spins until a reboot occurs
 951  */
 952 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
 953 {
 954         /* Generic WatchdogHandler, implement your own */
 955         mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
 956         return;
 957 }
 958
 959 void WatchdogException(struct pt_regs *regs)
 960 {
 961         printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
 962         WatchdogHandler(regs);
 963 }
 964 #endif
 965
 966 void __init trap_init(void)
 967 {
 968 }