2 * Board setup routines for the Sky Computers HDPU Compute Blade.
4 * Written by Brian Waite <waite@skycomputers.com>
6 * Based on code done by - Mark A. Greer <mgreer@mvista.com>
7 * Rabeeh Khoury - rabeeh@galileo.co.il
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
15 #include <linux/config.h>
17 #include <linux/pci.h>
18 #include <linux/delay.h>
19 #include <linux/irq.h>
20 #include <linux/ide.h>
21 #include <linux/seq_file.h>
22 #include <linux/platform_device.h>
24 #include <linux/initrd.h>
25 #include <linux/root_dev.h>
26 #include <linux/smp.h>
29 #include <asm/machdep.h>
31 #include <asm/mv64x60.h>
32 #include <asm/ppcboot.h>
33 #include <platforms/hdpu.h>
34 #include <linux/mv643xx.h>
35 #include <linux/hdpu_features.h>
36 #include <linux/device.h>
37 #include <linux/mtd/physmap.h>
39 #define BOARD_VENDOR "Sky Computers"
40 #define BOARD_MACHINE "HDPU-CB-A"
43 int ppcboot_bd_valid
= 0;
45 static mv64x60_handle_t bh
;
47 extern char cmd_line
[];
49 unsigned long hdpu_find_end_of_memory(void);
50 void hdpu_mpsc_progress(char *s
, unsigned short hex
);
51 void hdpu_heartbeat(void);
53 static void parse_bootinfo(unsigned long r3
,
54 unsigned long r4
, unsigned long r5
,
55 unsigned long r6
, unsigned long r7
);
56 static void hdpu_set_l1pe(void);
57 static void hdpu_cpustate_set(unsigned char new_state
);
59 static DEFINE_SPINLOCK(timebase_lock
);
60 static unsigned int timebase_upper
= 0, timebase_lower
= 0;
61 extern int smp_tb_synchronized
;
63 void __devinit
hdpu_tben_give(void);
64 void __devinit
hdpu_tben_take(void);
68 hdpu_map_irq(struct pci_dev
*dev
, unsigned char idsel
, unsigned char pin
)
70 struct pci_controller
*hose
= pci_bus_to_hose(dev
->bus
->number
);
72 if (hose
->index
== 0) {
73 static char pci_irq_table
[][4] = {
74 {HDPU_PCI_0_IRQ
, 0, 0, 0},
75 {HDPU_PCI_0_IRQ
, 0, 0, 0},
78 const long min_idsel
= 1, max_idsel
= 2, irqs_per_slot
= 4;
79 return PCI_IRQ_TABLE_LOOKUP
;
81 static char pci_irq_table
[][4] = {
82 {HDPU_PCI_1_IRQ
, 0, 0, 0},
85 const long min_idsel
= 1, max_idsel
= 1, irqs_per_slot
= 4;
86 return PCI_IRQ_TABLE_LOOKUP
;
90 static void __init
hdpu_intr_setup(void)
92 mv64x60_write(&bh
, MV64x60_GPP_IO_CNTL
,
93 (1 | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) |
94 (1 << 6) | (1 << 7) | (1 << 12) | (1 << 16) |
95 (1 << 18) | (1 << 19) | (1 << 20) | (1 << 21) |
96 (1 << 22) | (1 << 23) | (1 << 24) | (1 << 25) |
97 (1 << 26) | (1 << 27) | (1 << 28) | (1 << 29)));
99 /* XXXX Erranum FEr PCI-#8 */
100 mv64x60_clr_bits(&bh
, MV64x60_PCI0_CMD
, (1 << 5) | (1 << 9));
101 mv64x60_clr_bits(&bh
, MV64x60_PCI1_CMD
, (1 << 5) | (1 << 9));
104 * Dismiss and then enable interrupt on GPP interrupt cause
107 mv64x60_write(&bh
, MV64x60_GPP_INTR_CAUSE
, ~((1 << 8) | (1 << 13)));
108 mv64x60_set_bits(&bh
, MV64x60_GPP_INTR_MASK
, (1 << 8) | (1 << 13));
111 * Dismiss and then enable interrupt on CPU #0 high cause reg
112 * BIT25 summarizes GPP interrupts 8-15
114 mv64x60_set_bits(&bh
, MV64360_IC_CPU0_INTR_MASK_HI
, (1 << 25));
117 static void __init
hdpu_setup_peripherals(void)
121 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2BOOT_WIN
,
122 HDPU_EMB_FLASH_BASE
, HDPU_EMB_FLASH_SIZE
, 0);
123 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2BOOT_WIN
);
125 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2DEV_0_WIN
,
126 HDPU_TBEN_BASE
, HDPU_TBEN_SIZE
, 0);
127 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2DEV_0_WIN
);
129 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2DEV_1_WIN
,
130 HDPU_NEXUS_ID_BASE
, HDPU_NEXUS_ID_SIZE
, 0);
131 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2DEV_1_WIN
);
133 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2SRAM_WIN
,
134 HDPU_INTERNAL_SRAM_BASE
,
135 HDPU_INTERNAL_SRAM_SIZE
, 0);
136 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2SRAM_WIN
);
138 bh
.ci
->disable_window_32bit(&bh
, MV64x60_ENET2MEM_4_WIN
);
139 mv64x60_set_32bit_window(&bh
, MV64x60_ENET2MEM_4_WIN
, 0, 0, 0);
141 mv64x60_clr_bits(&bh
, MV64x60_PCI0_PCI_DECODE_CNTL
, (1 << 3));
142 mv64x60_clr_bits(&bh
, MV64x60_PCI1_PCI_DECODE_CNTL
, (1 << 3));
143 mv64x60_clr_bits(&bh
, MV64x60_TIMR_CNTR_0_3_CNTL
,
144 ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
146 /* Enable pipelining */
147 mv64x60_set_bits(&bh
, MV64x60_CPU_CONFIG
, (1 << 13));
148 /* Enable Snoop Pipelineing */
149 mv64x60_set_bits(&bh
, MV64360_D_UNIT_CONTROL_HIGH
, (1 << 24));
152 * Change DRAM read buffer assignment.
153 * Assign read buffer 0 dedicated only for CPU,
154 * and the rest read buffer 1.
156 val
= mv64x60_read(&bh
, MV64360_SDRAM_CONFIG
);
157 val
= val
& 0x03ffffff;
158 val
= val
| 0xf8000000;
159 mv64x60_write(&bh
, MV64360_SDRAM_CONFIG
, val
);
162 * Configure internal SRAM -
163 * Cache coherent write back, if CONFIG_MV64360_SRAM_CACHE_COHERENT set
165 * Parity error propagation
166 * Arbitration not parked for CPU only
167 * Other bits are reserved.
169 #ifdef CONFIG_MV64360_SRAM_CACHE_COHERENT
170 mv64x60_write(&bh
, MV64360_SRAM_CONFIG
, 0x001600b2);
172 mv64x60_write(&bh
, MV64360_SRAM_CONFIG
, 0x001600b0);
178 static void __init
hdpu_setup_bridge(void)
180 struct mv64x60_setup_info si
;
183 memset(&si
, 0, sizeof(si
));
185 si
.phys_reg_base
= HDPU_BRIDGE_REG_BASE
;
186 si
.pci_0
.enable_bus
= 1;
187 si
.pci_0
.pci_io
.cpu_base
= HDPU_PCI0_IO_START_PROC_ADDR
;
188 si
.pci_0
.pci_io
.pci_base_hi
= 0;
189 si
.pci_0
.pci_io
.pci_base_lo
= HDPU_PCI0_IO_START_PCI_ADDR
;
190 si
.pci_0
.pci_io
.size
= HDPU_PCI0_IO_SIZE
;
191 si
.pci_0
.pci_io
.swap
= MV64x60_CPU2PCI_SWAP_NONE
;
192 si
.pci_0
.pci_mem
[0].cpu_base
= HDPU_PCI0_MEM_START_PROC_ADDR
;
193 si
.pci_0
.pci_mem
[0].pci_base_hi
= HDPU_PCI0_MEM_START_PCI_HI_ADDR
;
194 si
.pci_0
.pci_mem
[0].pci_base_lo
= HDPU_PCI0_MEM_START_PCI_LO_ADDR
;
195 si
.pci_0
.pci_mem
[0].size
= HDPU_PCI0_MEM_SIZE
;
196 si
.pci_0
.pci_mem
[0].swap
= MV64x60_CPU2PCI_SWAP_NONE
;
197 si
.pci_0
.pci_cmd_bits
= 0;
198 si
.pci_0
.latency_timer
= 0x80;
200 si
.pci_1
.enable_bus
= 1;
201 si
.pci_1
.pci_io
.cpu_base
= HDPU_PCI1_IO_START_PROC_ADDR
;
202 si
.pci_1
.pci_io
.pci_base_hi
= 0;
203 si
.pci_1
.pci_io
.pci_base_lo
= HDPU_PCI1_IO_START_PCI_ADDR
;
204 si
.pci_1
.pci_io
.size
= HDPU_PCI1_IO_SIZE
;
205 si
.pci_1
.pci_io
.swap
= MV64x60_CPU2PCI_SWAP_NONE
;
206 si
.pci_1
.pci_mem
[0].cpu_base
= HDPU_PCI1_MEM_START_PROC_ADDR
;
207 si
.pci_1
.pci_mem
[0].pci_base_hi
= HDPU_PCI1_MEM_START_PCI_HI_ADDR
;
208 si
.pci_1
.pci_mem
[0].pci_base_lo
= HDPU_PCI1_MEM_START_PCI_LO_ADDR
;
209 si
.pci_1
.pci_mem
[0].size
= HDPU_PCI1_MEM_SIZE
;
210 si
.pci_1
.pci_mem
[0].swap
= MV64x60_CPU2PCI_SWAP_NONE
;
211 si
.pci_1
.pci_cmd_bits
= 0;
212 si
.pci_1
.latency_timer
= 0x80;
214 for (i
= 0; i
< MV64x60_CPU2MEM_WINDOWS
; i
++) {
215 #if defined(CONFIG_NOT_COHERENT_CACHE)
216 si
.cpu_prot_options
[i
] = 0;
217 si
.enet_options
[i
] = MV64360_ENET2MEM_SNOOP_NONE
;
218 si
.mpsc_options
[i
] = MV64360_MPSC2MEM_SNOOP_NONE
;
219 si
.idma_options
[i
] = MV64360_IDMA2MEM_SNOOP_NONE
;
221 si
.pci_1
.acc_cntl_options
[i
] =
222 MV64360_PCI_ACC_CNTL_SNOOP_NONE
|
223 MV64360_PCI_ACC_CNTL_SWAP_NONE
|
224 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES
|
225 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES
;
227 si
.pci_0
.acc_cntl_options
[i
] =
228 MV64360_PCI_ACC_CNTL_SNOOP_NONE
|
229 MV64360_PCI_ACC_CNTL_SWAP_NONE
|
230 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES
|
231 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES
;
234 si
.cpu_prot_options
[i
] = 0;
235 si
.enet_options
[i
] = MV64360_ENET2MEM_SNOOP_WB
; /* errata */
236 si
.mpsc_options
[i
] = MV64360_MPSC2MEM_SNOOP_WB
; /* errata */
237 si
.idma_options
[i
] = MV64360_IDMA2MEM_SNOOP_WB
; /* errata */
239 si
.pci_0
.acc_cntl_options
[i
] =
240 MV64360_PCI_ACC_CNTL_SNOOP_WB
|
241 MV64360_PCI_ACC_CNTL_SWAP_NONE
|
242 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES
|
243 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES
;
245 si
.pci_1
.acc_cntl_options
[i
] =
246 MV64360_PCI_ACC_CNTL_SNOOP_WB
|
247 MV64360_PCI_ACC_CNTL_SWAP_NONE
|
248 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES
|
249 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES
;
253 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR
| CPUSTATE_KERNEL_INIT_PCI
);
255 /* Lookup PCI host bridges */
256 mv64x60_init(&bh
, &si
);
257 pci_dram_offset
= 0; /* System mem at same addr on PCI & cpu bus */
258 ppc_md
.pci_swizzle
= common_swizzle
;
259 ppc_md
.pci_map_irq
= hdpu_map_irq
;
261 mv64x60_set_bus(&bh
, 0, 0);
262 bh
.hose_a
->first_busno
= 0;
263 bh
.hose_a
->last_busno
= 0xff;
264 bh
.hose_a
->last_busno
= pciauto_bus_scan(bh
.hose_a
, 0);
266 bh
.hose_b
->first_busno
= bh
.hose_a
->last_busno
+ 1;
267 mv64x60_set_bus(&bh
, 1, bh
.hose_b
->first_busno
);
268 bh
.hose_b
->last_busno
= 0xff;
269 bh
.hose_b
->last_busno
= pciauto_bus_scan(bh
.hose_b
,
270 bh
.hose_b
->first_busno
);
272 ppc_md
.pci_exclude_device
= mv64x60_pci_exclude_device
;
274 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR
| CPUSTATE_KERNEL_INIT_REG
);
276 * Enabling of PCI internal-vs-external arbitration
277 * is a platform- and errata-dependent decision.
282 #if defined(CONFIG_SERIAL_MPSC_CONSOLE)
283 static void __init
hdpu_early_serial_map(void)
286 static char first_time
= 1;
288 #if defined(CONFIG_KGDB_TTYS0)
290 #elif defined(CONFIG_KGDB_TTYS1)
293 #error "Invalid kgdb_tty port"
297 gt_early_mpsc_init(KGDB_PORT
,
298 B9600
| CS8
| CREAD
| HUPCL
| CLOCAL
);
307 static void hdpu_init2(void)
312 #if defined(CONFIG_MV643XX_ETH)
313 static void __init
hdpu_fixup_eth_pdata(struct platform_device
*pd
)
316 struct mv643xx_eth_platform_data
*eth_pd
;
317 eth_pd
= pd
->dev
.platform_data
;
319 eth_pd
->port_serial_control
=
320 mv64x60_read(&bh
, MV643XX_ETH_PORT_SERIAL_CONTROL_REG(pd
->id
) & ~1);
322 eth_pd
->force_phy_addr
= 1;
323 eth_pd
->phy_addr
= pd
->id
;
324 eth_pd
->tx_queue_size
= 400;
325 eth_pd
->rx_queue_size
= 800;
329 static void __init
hdpu_fixup_mpsc_pdata(struct platform_device
*pd
)
332 struct mpsc_pdata
*pdata
;
334 pdata
= (struct mpsc_pdata
*)pd
->dev
.platform_data
;
336 pdata
->max_idle
= 40;
337 if (ppcboot_bd_valid
)
338 pdata
->default_baud
= ppcboot_bd
.bi_baudrate
;
340 pdata
->default_baud
= HDPU_DEFAULT_BAUD
;
341 pdata
->brg_clk_src
= HDPU_MPSC_CLK_SRC
;
342 pdata
->brg_clk_freq
= HDPU_MPSC_CLK_FREQ
;
345 #if defined(CONFIG_HDPU_FEATURES)
346 static void __init
hdpu_fixup_cpustate_pdata(struct platform_device
*pd
)
348 struct platform_device
*pds
[1];
350 mv64x60_pd_fixup(&bh
, pds
, 1);
354 static int __init
hdpu_platform_notify(struct device
*dev
)
358 void ((*rtn
) (struct platform_device
* pdev
));
361 MPSC_CTLR_NAME
".0", hdpu_fixup_mpsc_pdata
},
362 #if defined(CONFIG_MV643XX_ETH)
364 MV643XX_ETH_NAME
".0", hdpu_fixup_eth_pdata
},
366 #if defined(CONFIG_HDPU_FEATURES)
368 HDPU_CPUSTATE_NAME
".0", hdpu_fixup_cpustate_pdata
},
371 struct platform_device
*pdev
;
374 if (dev
&& dev
->bus_id
)
375 for (i
= 0; i
< ARRAY_SIZE(dev_map
); i
++)
376 if (!strncmp(dev
->bus_id
, dev_map
[i
].bus_id
,
379 pdev
= container_of(dev
,
380 struct platform_device
,
382 dev_map
[i
].rtn(pdev
);
388 static void __init
hdpu_setup_arch(void)
391 ppc_md
.progress("hdpu_setup_arch: enter", 0);
392 #ifdef CONFIG_BLK_DEV_INITRD
394 ROOT_DEV
= Root_RAM0
;
397 #ifdef CONFIG_ROOT_NFS
400 ROOT_DEV
= Root_SDA2
;
403 ppc_md
.heartbeat
= hdpu_heartbeat
;
405 ppc_md
.heartbeat_reset
= HZ
;
406 ppc_md
.heartbeat_count
= 1;
409 ppc_md
.progress("hdpu_setup_arch: Enabling L2 cache", 0);
411 /* Enable L1 Parity Bits */
414 /* Enable L2 and L3 caches (if 745x) */
415 _set_L2CR(0x80080000);
418 ppc_md
.progress("hdpu_setup_arch: enter", 0);
422 hdpu_setup_peripherals();
424 #ifdef CONFIG_SERIAL_MPSC_CONSOLE
425 hdpu_early_serial_map();
428 printk("SKY HDPU Compute Blade \n");
431 ppc_md
.progress("hdpu_setup_arch: exit", 0);
433 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR
| CPUSTATE_KERNEL_OK
);
436 static void __init
hdpu_init_irq(void)
441 static void __init
hdpu_set_l1pe()
444 asm volatile ("mfspr %0, 1011":"=r" (ictrl
):);
445 ictrl
|= ICTRL_EICE
| ICTRL_EDC
| ICTRL_EICP
;
446 asm volatile ("mtspr 1011, %0"::"r" (ictrl
));
450 * Set BAT 1 to map 0xf1000000 to end of physical memory space.
452 static __inline__
void hdpu_set_bat(void)
455 mtspr(SPRN_DBAT1U
, 0xf10001fe);
456 mtspr(SPRN_DBAT1L
, 0xf100002a);
462 unsigned long __init
hdpu_find_end_of_memory(void)
464 return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE
,
465 MV64x60_TYPE_MV64360
);
468 static void hdpu_reset_board(void)
470 volatile int infinite
= 1;
472 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR
| CPUSTATE_KERNEL_RESET
);
476 /* Clear all the LEDs */
477 mv64x60_write(&bh
, MV64x60_GPP_VALUE_CLR
, ((1 << 4) |
478 (1 << 5) | (1 << 6)));
480 /* disable and invalidate the L2 cache */
484 /* flush and disable L1 I/D cache */
493 "isync\n" "sync\n" "mtspr 1008,5\n" "isync\n" "sync\n");
495 /* Hit the reset bit */
496 mv64x60_write(&bh
, MV64x60_GPP_VALUE_CLR
, (1 << 3));
504 static void hdpu_restart(char *cmd
)
506 volatile ulong i
= 10000000;
511 panic("restart failed\n");
514 static void hdpu_halt(void)
518 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR
| CPUSTATE_KERNEL_HALT
);
520 /* Clear all the LEDs */
521 mv64x60_write(&bh
, MV64x60_GPP_VALUE_CLR
, ((1 << 4) | (1 << 5) |
527 static void hdpu_power_off(void)
533 static int hdpu_show_cpuinfo(struct seq_file
*m
)
537 pvid
= mfspr(SPRN_PVR
);
538 seq_printf(m
, "vendor\t\t: Sky Computers\n");
539 seq_printf(m
, "machine\t\t: HDPU Compute Blade\n");
540 seq_printf(m
, "PVID\t\t: 0x%x, vendor: %s\n",
541 pvid
, (pvid
& (1 << 15) ? "IBM" : "Motorola"));
546 static void __init
hdpu_calibrate_decr(void)
550 if (ppcboot_bd_valid
)
551 freq
= ppcboot_bd
.bi_busfreq
/ 4;
555 printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
556 freq
/ 1000000, freq
% 1000000);
558 tb_ticks_per_jiffy
= freq
/ HZ
;
559 tb_to_us
= mulhwu_scale_factor(freq
, 1000000);
564 static void parse_bootinfo(unsigned long r3
,
565 unsigned long r4
, unsigned long r5
,
566 unsigned long r6
, unsigned long r7
)
569 char *cmdline_start
= NULL
;
573 if ((r3
& 0xf0000000) == 0)
575 if ((r3
& 0xf0000000) == KERNELBASE
) {
578 memcpy(&ppcboot_bd
, bd
, sizeof(ppcboot_bd
));
579 ppcboot_bd_valid
= 1;
582 #ifdef CONFIG_BLK_DEV_INITRD
583 if (r4
&& r5
&& r5
> r4
) {
584 if ((r4
& 0xf0000000) == 0)
586 if ((r5
& 0xf0000000) == 0)
588 if ((r4
& 0xf0000000) == KERNELBASE
) {
591 initrd_below_start_ok
= 1;
594 #endif /* CONFIG_BLK_DEV_INITRD */
596 if (r6
&& r7
&& r7
> r6
) {
597 if ((r6
& 0xf0000000) == 0)
599 if ((r7
& 0xf0000000) == 0)
601 if ((r6
& 0xf0000000) == KERNELBASE
) {
602 cmdline_start
= (void *)r6
;
603 cmdline_len
= (r7
- r6
);
604 strncpy(cmd_line
, cmdline_start
, cmdline_len
);
609 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
611 hdpu_ide_request_region(ide_ioreg_t from
, unsigned int extent
, const char *name
)
613 request_region(from
, extent
, name
);
617 static void hdpu_ide_release_region(ide_ioreg_t from
, unsigned int extent
)
619 release_region(from
, extent
);
624 hdpu_ide_pci_init_hwif_ports(hw_regs_t
* hw
, ide_ioreg_t data_port
,
625 ide_ioreg_t ctrl_port
, int *irq
)
629 pci_for_each_dev(dev
) {
630 if (((dev
->class >> 8) == PCI_CLASS_STORAGE_IDE
) ||
631 ((dev
->class >> 8) == PCI_CLASS_STORAGE_RAID
)) {
644 void hdpu_heartbeat(void)
646 if (mv64x60_read(&bh
, MV64x60_GPP_VALUE
) & (1 << 5))
647 mv64x60_write(&bh
, MV64x60_GPP_VALUE_CLR
, (1 << 5));
649 mv64x60_write(&bh
, MV64x60_GPP_VALUE_SET
, (1 << 5));
651 ppc_md
.heartbeat_count
= ppc_md
.heartbeat_reset
;
655 static void __init
hdpu_map_io(void)
657 io_block_mapping(0xf1000000, 0xf1000000, 0x20000, _PAGE_IO
);
661 char hdpu_smp0
[] = "SMP Cpu #0";
662 char hdpu_smp1
[] = "SMP Cpu #1";
664 static irqreturn_t
hdpu_smp_cpu0_int_handler(int irq
, void *dev_id
,
665 struct pt_regs
*regs
)
667 volatile unsigned int doorbell
;
669 doorbell
= mv64x60_read(&bh
, MV64360_CPU0_DOORBELL
);
671 /* Ack the doorbell interrupts */
672 mv64x60_write(&bh
, MV64360_CPU0_DOORBELL_CLR
, doorbell
);
675 smp_message_recv(0, regs
);
678 smp_message_recv(1, regs
);
681 smp_message_recv(2, regs
);
684 smp_message_recv(3, regs
);
689 static irqreturn_t
hdpu_smp_cpu1_int_handler(int irq
, void *dev_id
,
690 struct pt_regs
*regs
)
692 volatile unsigned int doorbell
;
694 doorbell
= mv64x60_read(&bh
, MV64360_CPU1_DOORBELL
);
696 /* Ack the doorbell interrupts */
697 mv64x60_write(&bh
, MV64360_CPU1_DOORBELL_CLR
, doorbell
);
700 smp_message_recv(0, regs
);
703 smp_message_recv(1, regs
);
706 smp_message_recv(2, regs
);
709 smp_message_recv(3, regs
);
714 static void smp_hdpu_CPU_two(void)
720 "mtspr 26, 3\n" "li 4,0\n" "mtspr 27,4\n" "rfi");
724 static int smp_hdpu_probe(void)
729 cpu_count_reg
= ioremap(HDPU_NEXUS_ID_BASE
, HDPU_NEXUS_ID_SIZE
);
731 num_cpus
= (*cpu_count_reg
>> 20) & 0x3;
732 iounmap(cpu_count_reg
);
735 /* Validate the bits in the CPLD. If we could not map the reg, return 2.
736 * If the register reported 0 or 3, return 2.
737 * Older CPLD revisions set these bits to all ones (val = 3).
739 if ((num_cpus
< 1) || (num_cpus
> 2)) {
741 ("Unable to determine the number of processors %d . deafulting to 2.\n",
749 smp_hdpu_message_pass(int target
, int msg
)
752 printk("SMP %d: smp_message_pass: unknown msg %d\n",
753 smp_processor_id(), msg
);
758 mv64x60_write(&bh
, MV64360_CPU0_DOORBELL
, 1 << msg
);
759 mv64x60_write(&bh
, MV64360_CPU1_DOORBELL
, 1 << msg
);
761 case MSG_ALL_BUT_SELF
:
762 if (smp_processor_id())
763 mv64x60_write(&bh
, MV64360_CPU0_DOORBELL
, 1 << msg
);
765 mv64x60_write(&bh
, MV64360_CPU1_DOORBELL
, 1 << msg
);
769 mv64x60_write(&bh
, MV64360_CPU0_DOORBELL
, 1 << msg
);
771 mv64x60_write(&bh
, MV64360_CPU1_DOORBELL
, 1 << msg
);
776 static void smp_hdpu_kick_cpu(int nr
)
778 volatile unsigned int *bootaddr
;
781 ppc_md
.progress("smp_hdpu_kick_cpu", 0);
783 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR
| CPUSTATE_KERNEL_CPU1_KICK
);
785 /* Disable BootCS. Must also reduce the windows size to zero. */
786 bh
.ci
->disable_window_32bit(&bh
, MV64x60_CPU2BOOT_WIN
);
787 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2BOOT_WIN
, 0, 0, 0);
789 bootaddr
= ioremap(HDPU_INTERNAL_SRAM_BASE
, HDPU_INTERNAL_SRAM_SIZE
);
792 ppc_md
.progress("smp_hdpu_kick_cpu: ioremap failed", 0);
796 memcpy((void *)(bootaddr
+ 0x40), (void *)&smp_hdpu_CPU_two
, 0x20);
798 /* map SRAM to 0xfff00000 */
799 bh
.ci
->disable_window_32bit(&bh
, MV64x60_CPU2SRAM_WIN
);
801 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2SRAM_WIN
,
802 0xfff00000, HDPU_INTERNAL_SRAM_SIZE
, 0);
803 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2SRAM_WIN
);
805 /* Enable CPU1 arbitration */
806 mv64x60_clr_bits(&bh
, MV64x60_CPU_MASTER_CNTL
, (1 << 9));
809 * Wait 100mSecond until other CPU has reached __secondary_start.
810 * When it reaches, it is permittable to rever the SRAM mapping etc...
813 *(unsigned long *)KERNELBASE
= nr
;
814 asm volatile ("dcbf 0,%0"::"r" (KERNELBASE
):"memory");
818 /* Set up window for internal sram (256KByte insize) */
819 bh
.ci
->disable_window_32bit(&bh
, MV64x60_CPU2SRAM_WIN
);
820 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2SRAM_WIN
,
821 HDPU_INTERNAL_SRAM_BASE
,
822 HDPU_INTERNAL_SRAM_SIZE
, 0);
823 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2SRAM_WIN
);
825 * Set up windows for embedded FLASH (using boot CS window).
828 bh
.ci
->disable_window_32bit(&bh
, MV64x60_CPU2BOOT_WIN
);
829 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2BOOT_WIN
,
830 HDPU_EMB_FLASH_BASE
, HDPU_EMB_FLASH_SIZE
, 0);
831 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2BOOT_WIN
);
834 static void smp_hdpu_setup_cpu(int cpu_nr
)
838 ppc_md
.progress("smp_hdpu_setup_cpu 0", 0);
839 mv64x60_write(&bh
, MV64360_CPU0_DOORBELL_CLR
, 0xff);
840 mv64x60_write(&bh
, MV64360_CPU0_DOORBELL_MASK
, 0xff);
841 request_irq(60, hdpu_smp_cpu0_int_handler
,
842 SA_INTERRUPT
, hdpu_smp0
, 0);
847 ppc_md
.progress("smp_hdpu_setup_cpu 1", 0);
849 hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR
|
850 CPUSTATE_KERNEL_CPU1_OK
);
852 /* Enable L1 Parity Bits */
855 /* Enable L2 cache */
857 _set_L2CR(0x80080000);
859 mv64x60_write(&bh
, MV64360_CPU1_DOORBELL_CLR
, 0x0);
860 mv64x60_write(&bh
, MV64360_CPU1_DOORBELL_MASK
, 0xff);
861 request_irq(28, hdpu_smp_cpu1_int_handler
,
862 SA_INTERRUPT
, hdpu_smp1
, 0);
867 void __devinit
hdpu_tben_give()
869 volatile unsigned long *val
= 0;
871 /* By writing 0 to the TBEN_BASE, the timebases is frozen */
872 val
= ioremap(HDPU_TBEN_BASE
, 4);
876 spin_lock(&timebase_lock
);
877 timebase_upper
= get_tbu();
878 timebase_lower
= get_tbl();
879 spin_unlock(&timebase_lock
);
881 while (timebase_upper
|| timebase_lower
)
884 /* By writing 1 to the TBEN_BASE, the timebases is thawed */
892 void __devinit
hdpu_tben_take()
894 while (!(timebase_upper
|| timebase_lower
))
897 spin_lock(&timebase_lock
);
898 set_tb(timebase_upper
, timebase_lower
);
901 spin_unlock(&timebase_lock
);
904 static struct smp_ops_t hdpu_smp_ops
= {
905 .message_pass
= smp_hdpu_message_pass
,
906 .probe
= smp_hdpu_probe
,
907 .kick_cpu
= smp_hdpu_kick_cpu
,
908 .setup_cpu
= smp_hdpu_setup_cpu
,
909 .give_timebase
= hdpu_tben_give
,
910 .take_timebase
= hdpu_tben_take
,
912 #endif /* CONFIG_SMP */
915 platform_init(unsigned long r3
, unsigned long r4
, unsigned long r5
,
916 unsigned long r6
, unsigned long r7
)
918 parse_bootinfo(r3
, r4
, r5
, r6
, r7
);
922 ppc_md
.setup_arch
= hdpu_setup_arch
;
923 ppc_md
.init
= hdpu_init2
;
924 ppc_md
.show_cpuinfo
= hdpu_show_cpuinfo
;
925 ppc_md
.init_IRQ
= hdpu_init_irq
;
926 ppc_md
.get_irq
= mv64360_get_irq
;
927 ppc_md
.restart
= hdpu_restart
;
928 ppc_md
.power_off
= hdpu_power_off
;
929 ppc_md
.halt
= hdpu_halt
;
930 ppc_md
.find_end_of_memory
= hdpu_find_end_of_memory
;
931 ppc_md
.calibrate_decr
= hdpu_calibrate_decr
;
932 ppc_md
.setup_io_mappings
= hdpu_map_io
;
934 bh
.p_base
= CONFIG_MV64X60_NEW_BASE
;
935 bh
.v_base
= (unsigned long *)bh
.p_base
;
939 #if defined(CONFIG_SERIAL_TEXT_DEBUG)
940 ppc_md
.progress
= hdpu_mpsc_progress
; /* embedded UART */
941 mv64x60_progress_init(bh
.p_base
);
942 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
945 smp_ops
= &hdpu_smp_ops
;
946 #endif /* CONFIG_SMP */
948 #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
949 platform_notify
= hdpu_platform_notify
;
954 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
955 /* SMP safe version of the serial text debug routine. Uses Semaphore 0 */
956 void hdpu_mpsc_progress(char *s
, unsigned short hex
)
958 while (mv64x60_read(&bh
, MV64360_WHO_AM_I
) !=
959 mv64x60_read(&bh
, MV64360_SEMAPHORE_0
)) {
961 mv64x60_mpsc_progress(s
, hex
);
962 mv64x60_write(&bh
, MV64360_SEMAPHORE_0
, 0xff);
966 static void hdpu_cpustate_set(unsigned char new_state
)
968 unsigned int state
= (new_state
<< 21);
969 mv64x60_write(&bh
, MV64x60_GPP_VALUE_CLR
, (0xff << 21));
970 mv64x60_write(&bh
, MV64x60_GPP_VALUE_CLR
, state
);
973 #ifdef CONFIG_MTD_PHYSMAP
974 static struct mtd_partition hdpu_partitions
[] = {
983 .offset
= 0x03400000,
986 .name
= "Kernel Image",
988 .offset
= 0x03C00000,
993 .offset
= 0x03EC0000,
998 .offset
= 0x03F00000,
1003 static int __init
hdpu_setup_mtd(void)
1006 physmap_set_partitions(hdpu_partitions
, 5);
1010 arch_initcall(hdpu_setup_mtd
);
1013 #ifdef CONFIG_HDPU_FEATURES
1015 static struct resource hdpu_cpustate_resources
[] = {
1017 .name
= "addr base",
1018 .start
= MV64x60_GPP_VALUE_SET
,
1019 .end
= MV64x60_GPP_VALUE_CLR
+ 1,
1020 .flags
= IORESOURCE_MEM
,
1024 static struct resource hdpu_nexus_resources
[] = {
1026 .name
= "nexus register",
1027 .start
= HDPU_NEXUS_ID_BASE
,
1028 .end
= HDPU_NEXUS_ID_BASE
+ HDPU_NEXUS_ID_SIZE
,
1029 .flags
= IORESOURCE_MEM
,
1033 static struct platform_device hdpu_cpustate_device
= {
1034 .name
= HDPU_CPUSTATE_NAME
,
1036 .num_resources
= ARRAY_SIZE(hdpu_cpustate_resources
),
1037 .resource
= hdpu_cpustate_resources
,
1040 static struct platform_device hdpu_nexus_device
= {
1041 .name
= HDPU_NEXUS_NAME
,
1043 .num_resources
= ARRAY_SIZE(hdpu_nexus_resources
),
1044 .resource
= hdpu_nexus_resources
,
1047 static int __init
hdpu_add_pds(void)
1049 platform_device_register(&hdpu_cpustate_device
);
1050 platform_device_register(&hdpu_nexus_device
);
1054 arch_initcall(hdpu_add_pds
);