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Linux-2.6.12-rc2
[deliverable/linux.git] / arch / ppc / platforms / katana.c
1 /*
2 * arch/ppc/platforms/katana.c
3 *
4 * Board setup routines for the Artesyn Katana cPCI boards.
5 *
6 * Author: Tim Montgomery <timm@artesyncp.com>
7 * Maintained by: Mark A. Greer <mgreer@mvista.com>
8 *
9 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
10 * Based on code done by - Mark A. Greer <mgreer@mvista.com>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17 /*
18 * Supports the Artesyn 750i, 752i, and 3750. The 752i is virtually identical
19 * to the 750i except that it has an mv64460 bridge.
20 */
21 #include <linux/config.h>
22 #include <linux/kernel.h>
23 #include <linux/pci.h>
24 #include <linux/kdev_t.h>
25 #include <linux/console.h>
26 #include <linux/initrd.h>
27 #include <linux/root_dev.h>
28 #include <linux/delay.h>
29 #include <linux/seq_file.h>
30 #include <linux/bootmem.h>
31 #include <linux/mtd/physmap.h>
32 #include <linux/mv643xx.h>
33 #ifdef CONFIG_BOOTIMG
34 #include <linux/bootimg.h>
35 #endif
36 #include <asm/page.h>
37 #include <asm/time.h>
38 #include <asm/smp.h>
39 #include <asm/todc.h>
40 #include <asm/bootinfo.h>
41 #include <asm/ppcboot.h>
42 #include <asm/mv64x60.h>
43 #include <platforms/katana.h>
44
45 static struct mv64x60_handle bh;
46 static katana_id_t katana_id;
47 static void __iomem *cpld_base;
48 static void __iomem *sram_base;
49
50 static u32 katana_flash_size_0;
51 static u32 katana_flash_size_1;
52
53 static u32 katana_bus_frequency;
54
55 unsigned char __res[sizeof(bd_t)];
56
57 /* PCI Interrupt routing */
58 static int __init
59 katana_irq_lookup_750i(unsigned char idsel, unsigned char pin)
60 {
61 static char pci_irq_table[][4] = {
62 /*
63 * PCI IDSEL/INTPIN->INTLINE
64 * A B C D
65 */
66 /* IDSEL 4 (PMC 1) */
67 { KATANA_PCI_INTB_IRQ_750i, KATANA_PCI_INTC_IRQ_750i,
68 KATANA_PCI_INTD_IRQ_750i, KATANA_PCI_INTA_IRQ_750i },
69 /* IDSEL 5 (PMC 2) */
70 { KATANA_PCI_INTC_IRQ_750i, KATANA_PCI_INTD_IRQ_750i,
71 KATANA_PCI_INTA_IRQ_750i, KATANA_PCI_INTB_IRQ_750i },
72 /* IDSEL 6 (T8110) */
73 {KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 },
74 };
75 const long min_idsel = 4, max_idsel = 6, irqs_per_slot = 4;
76
77 return PCI_IRQ_TABLE_LOOKUP;
78 }
79
80 static int __init
81 katana_irq_lookup_3750(unsigned char idsel, unsigned char pin)
82 {
83 static char pci_irq_table[][4] = {
84 /*
85 * PCI IDSEL/INTPIN->INTLINE
86 * A B C D
87 */
88 { KATANA_PCI_INTA_IRQ_3750, 0, 0, 0 }, /* IDSEL 3 (BCM5691) */
89 { KATANA_PCI_INTB_IRQ_3750, 0, 0, 0 }, /* IDSEL 4 (MV64360 #2)*/
90 { KATANA_PCI_INTC_IRQ_3750, 0, 0, 0 }, /* IDSEL 5 (MV64360 #3)*/
91 };
92 const long min_idsel = 3, max_idsel = 5, irqs_per_slot = 4;
93
94 return PCI_IRQ_TABLE_LOOKUP;
95 }
96
97 static int __init
98 katana_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
99 {
100 switch (katana_id) {
101 case KATANA_ID_750I:
102 case KATANA_ID_752I:
103 return katana_irq_lookup_750i(idsel, pin);
104
105 case KATANA_ID_3750:
106 return katana_irq_lookup_3750(idsel, pin);
107
108 default:
109 printk(KERN_ERR "Bogus board ID\n");
110 return 0;
111 }
112 }
113
114 /* Board info retrieval routines */
115 void __init
116 katana_get_board_id(void)
117 {
118 switch (in_8(cpld_base + KATANA_CPLD_PRODUCT_ID)) {
119 case KATANA_PRODUCT_ID_3750:
120 katana_id = KATANA_ID_3750;
121 break;
122
123 case KATANA_PRODUCT_ID_750i:
124 katana_id = KATANA_ID_750I;
125 break;
126
127 case KATANA_PRODUCT_ID_752i:
128 katana_id = KATANA_ID_752I;
129 break;
130
131 default:
132 printk(KERN_ERR "Unsupported board\n");
133 }
134 }
135
136 int __init
137 katana_get_proc_num(void)
138 {
139 u16 val;
140 u8 save_exclude;
141 static int proc = -1;
142 static u8 first_time = 1;
143
144 if (first_time) {
145 if (katana_id != KATANA_ID_3750)
146 proc = 0;
147 else {
148 save_exclude = mv64x60_pci_exclude_bridge;
149 mv64x60_pci_exclude_bridge = 0;
150
151 early_read_config_word(bh.hose_a, 0,
152 PCI_DEVFN(0,0), PCI_DEVICE_ID, &val);
153
154 mv64x60_pci_exclude_bridge = save_exclude;
155
156 switch(val) {
157 case PCI_DEVICE_ID_KATANA_3750_PROC0:
158 proc = 0;
159 break;
160
161 case PCI_DEVICE_ID_KATANA_3750_PROC1:
162 proc = 1;
163 break;
164
165 case PCI_DEVICE_ID_KATANA_3750_PROC2:
166 proc = 2;
167 break;
168
169 default:
170 printk(KERN_ERR "Bogus Device ID\n");
171 }
172 }
173
174 first_time = 0;
175 }
176
177 return proc;
178 }
179
180 static inline int
181 katana_is_monarch(void)
182 {
183 return in_8(cpld_base + KATANA_CPLD_BD_CFG_3) &
184 KATANA_CPLD_BD_CFG_3_MONARCH;
185 }
186
187 static void __init
188 katana_setup_bridge(void)
189 {
190 struct pci_controller hose;
191 struct mv64x60_setup_info si;
192 void __iomem *vaddr;
193 int i;
194 u16 val;
195 u8 save_exclude;
196
197 /*
198 * Some versions of the Katana firmware mistakenly change the vendor
199 * & device id fields in the bridge's pci device (visible via pci
200 * config accesses). This breaks mv64x60_init() because those values
201 * are used to identify the type of bridge that's there. Artesyn
202 * claims that the subsystem vendor/device id's will have the correct
203 * Marvell values so this code puts back the correct values from there.
204 */
205 memset(&hose, 0, sizeof(hose));
206 vaddr = ioremap(CONFIG_MV64X60_NEW_BASE, MV64x60_INTERNAL_SPACE_SIZE);
207 setup_indirect_pci_nomap(&hose, vaddr + MV64x60_PCI0_CONFIG_ADDR,
208 vaddr + MV64x60_PCI0_CONFIG_DATA);
209 save_exclude = mv64x60_pci_exclude_bridge;
210 mv64x60_pci_exclude_bridge = 0;
211
212 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val);
213
214 if (val != PCI_VENDOR_ID_MARVELL) {
215 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
216 PCI_SUBSYSTEM_VENDOR_ID, &val);
217 early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
218 PCI_VENDOR_ID, val);
219 early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
220 PCI_SUBSYSTEM_ID, &val);
221 early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
222 PCI_DEVICE_ID, val);
223 }
224
225 mv64x60_pci_exclude_bridge = save_exclude;
226 iounmap(vaddr);
227
228 memset(&si, 0, sizeof(si));
229
230 si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
231
232 si.pci_1.enable_bus = 1;
233 si.pci_1.pci_io.cpu_base = KATANA_PCI1_IO_START_PROC_ADDR;
234 si.pci_1.pci_io.pci_base_hi = 0;
235 si.pci_1.pci_io.pci_base_lo = KATANA_PCI1_IO_START_PCI_ADDR;
236 si.pci_1.pci_io.size = KATANA_PCI1_IO_SIZE;
237 si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
238 si.pci_1.pci_mem[0].cpu_base = KATANA_PCI1_MEM_START_PROC_ADDR;
239 si.pci_1.pci_mem[0].pci_base_hi = KATANA_PCI1_MEM_START_PCI_HI_ADDR;
240 si.pci_1.pci_mem[0].pci_base_lo = KATANA_PCI1_MEM_START_PCI_LO_ADDR;
241 si.pci_1.pci_mem[0].size = KATANA_PCI1_MEM_SIZE;
242 si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
243 si.pci_1.pci_cmd_bits = 0;
244 si.pci_1.latency_timer = 0x80;
245
246 for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
247 #if defined(CONFIG_NOT_COHERENT_CACHE)
248 si.cpu_prot_options[i] = 0;
249 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
250 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
251 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
252
253 si.pci_1.acc_cntl_options[i] =
254 MV64360_PCI_ACC_CNTL_SNOOP_NONE |
255 MV64360_PCI_ACC_CNTL_SWAP_NONE |
256 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
257 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
258 #else
259 si.cpu_prot_options[i] = 0;
260 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
261 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
262 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
263
264 si.pci_1.acc_cntl_options[i] =
265 MV64360_PCI_ACC_CNTL_SNOOP_WB |
266 MV64360_PCI_ACC_CNTL_SWAP_NONE |
267 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
268 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
269 #endif
270 }
271
272 /* Lookup PCI host bridges */
273 if (mv64x60_init(&bh, &si))
274 printk(KERN_WARNING "Bridge initialization failed.\n");
275
276 pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
277 ppc_md.pci_swizzle = common_swizzle;
278 ppc_md.pci_map_irq = katana_map_irq;
279 ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
280
281 mv64x60_set_bus(&bh, 1, 0);
282 bh.hose_b->first_busno = 0;
283 bh.hose_b->last_busno = 0xff;
284 }
285
286 /* Bridge & platform setup routines */
287 void __init
288 katana_intr_setup(void)
289 {
290 /* MPP 8, 9, and 10 */
291 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff);
292
293 /* MPP 14 */
294 if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I))
295 mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0x0f000000);
296
297 /*
298 * Define GPP 8,9,and 10 interrupt polarity as active low
299 * input signal and level triggered
300 */
301 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700);
302 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700);
303
304 if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) {
305 mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, (1<<14));
306 mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, (1<<14));
307 }
308
309 /* Config GPP intr ctlr to respond to level trigger */
310 mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10));
311
312 /* Erranum FEr PCI-#8 */
313 mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1<<5) | (1<<9));
314 mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<5) | (1<<9));
315
316 /*
317 * Dismiss and then enable interrupt on GPP interrupt cause
318 * for CPU #0
319 */
320 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700);
321 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700);
322
323 if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) {
324 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(1<<14));
325 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, (1<<14));
326 }
327
328 /*
329 * Dismiss and then enable interrupt on CPU #0 high cause reg
330 * BIT25 summarizes GPP interrupts 8-15
331 */
332 mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25));
333 }
334
335 void __init
336 katana_setup_peripherals(void)
337 {
338 u32 base;
339
340 /* Set up windows for boot CS, soldered & socketed flash, and CPLD */
341 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
342 KATANA_BOOT_WINDOW_BASE, KATANA_BOOT_WINDOW_SIZE, 0);
343 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
344
345 /* Assume firmware set up window sizes correctly for dev 0 & 1 */
346 mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, &base,
347 &katana_flash_size_0);
348
349 if (katana_flash_size_0 > 0) {
350 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
351 KATANA_SOLDERED_FLASH_BASE, katana_flash_size_0, 0);
352 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
353 }
354
355 mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, &base,
356 &katana_flash_size_1);
357
358 if (katana_flash_size_1 > 0) {
359 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
360 (KATANA_SOLDERED_FLASH_BASE + katana_flash_size_0),
361 katana_flash_size_1, 0);
362 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
363 }
364
365 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
366 KATANA_SOCKET_BASE, KATANA_SOCKETED_FLASH_SIZE, 0);
367 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
368
369 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
370 KATANA_CPLD_BASE, KATANA_CPLD_SIZE, 0);
371 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
372 cpld_base = ioremap(KATANA_CPLD_BASE, KATANA_CPLD_SIZE);
373
374 mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
375 KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
376 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
377 sram_base = ioremap(KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
378
379 /* Set up Enet->SRAM window */
380 mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
381 KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
382 bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
383
384 /* Give enet r/w access to memory region */
385 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
386 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
387 mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
388
389 mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
390 mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
391 ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
392
393 /* Must wait until window set up before retrieving board id */
394 katana_get_board_id();
395
396 /* Enumerate pci bus (must know board id before getting proc number) */
397 if (katana_get_proc_num() == 0)
398 bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, 0);
399
400 #if defined(CONFIG_NOT_COHERENT_CACHE)
401 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
402 #else
403 mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
404 #endif
405
406 /*
407 * Setting the SRAM to 0. Note that this generates parity errors on
408 * internal data path in SRAM since it's first time accessing it
409 * while after reset it's not configured.
410 */
411 memset(sram_base, 0, MV64360_SRAM_SIZE);
412
413 /* Only processor zero [on 3750] is an PCI interrupt controller */
414 if (katana_get_proc_num() == 0)
415 katana_intr_setup();
416 }
417
418 static void __init
419 katana_enable_ipmi(void)
420 {
421 u8 reset_out;
422
423 /* Enable access to IPMI ctlr by clearing IPMI PORTSEL bit in CPLD */
424 reset_out = in_8(cpld_base + KATANA_CPLD_RESET_OUT);
425 reset_out &= ~KATANA_CPLD_RESET_OUT_PORTSEL;
426 out_8(cpld_base + KATANA_CPLD_RESET_OUT, reset_out);
427 }
428
429 static void __init
430 katana_setup_arch(void)
431 {
432 if (ppc_md.progress)
433 ppc_md.progress("katana_setup_arch: enter", 0);
434
435 set_tb(0, 0);
436
437 #ifdef CONFIG_BLK_DEV_INITRD
438 if (initrd_start)
439 ROOT_DEV = Root_RAM0;
440 else
441 #endif
442 #ifdef CONFIG_ROOT_NFS
443 ROOT_DEV = Root_NFS;
444 #else
445 ROOT_DEV = Root_SDA2;
446 #endif
447
448 /*
449 * Set up the L2CR register.
450 *
451 * 750FX has only L2E, L2PE (bits 2-8 are reserved)
452 * DD2.0 has bug that requires the L2 to be in WRT mode
453 * avoid dirty data in cache
454 */
455 if (PVR_REV(mfspr(SPRN_PVR)) == 0x0200) {
456 printk(KERN_INFO "DD2.0 detected. Setting L2 cache"
457 "to Writethrough mode\n");
458 _set_L2CR(L2CR_L2E | L2CR_L2PE | L2CR_L2WT);
459 } else
460 _set_L2CR(L2CR_L2E | L2CR_L2PE);
461
462 if (ppc_md.progress)
463 ppc_md.progress("katana_setup_arch: calling setup_bridge", 0);
464
465 katana_setup_bridge();
466 katana_setup_peripherals();
467 katana_enable_ipmi();
468
469 katana_bus_frequency = katana_bus_freq(cpld_base);
470
471 printk(KERN_INFO "Artesyn Communication Products, LLC - Katana(TM)\n");
472 if (ppc_md.progress)
473 ppc_md.progress("katana_setup_arch: exit", 0);
474 }
475
476 /* Platform device data fixup routines. */
477 #if defined(CONFIG_SERIAL_MPSC)
478 static void __init
479 katana_fixup_mpsc_pdata(struct platform_device *pdev)
480 {
481 struct mpsc_pdata *pdata;
482
483 pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
484
485 pdata->max_idle = 40;
486 pdata->default_baud = KATANA_DEFAULT_BAUD;
487 pdata->brg_clk_src = KATANA_MPSC_CLK_SRC;
488 /*
489 * TCLK (not SysCLk) is routed to BRG, then to the MPSC. On most parts,
490 * TCLK == SysCLK but on 64460, they are separate pins.
491 * SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz.
492 */
493 pdata->brg_clk_freq = min(katana_bus_frequency, MV64x60_TCLK_FREQ_MAX);
494 }
495 #endif
496
497 #if defined(CONFIG_MV643XX_ETH)
498 static void __init
499 katana_fixup_eth_pdata(struct platform_device *pdev)
500 {
501 struct mv643xx_eth_platform_data *eth_pd;
502 static u16 phy_addr[] = {
503 KATANA_ETH0_PHY_ADDR,
504 KATANA_ETH1_PHY_ADDR,
505 KATANA_ETH2_PHY_ADDR,
506 };
507
508 eth_pd = pdev->dev.platform_data;
509 eth_pd->force_phy_addr = 1;
510 eth_pd->phy_addr = phy_addr[pdev->id];
511 eth_pd->tx_queue_size = KATANA_ETH_TX_QUEUE_SIZE;
512 eth_pd->rx_queue_size = KATANA_ETH_RX_QUEUE_SIZE;
513 }
514 #endif
515
516 static int __init
517 katana_platform_notify(struct device *dev)
518 {
519 static struct {
520 char *bus_id;
521 void ((*rtn)(struct platform_device *pdev));
522 } dev_map[] = {
523 #if defined(CONFIG_SERIAL_MPSC)
524 { MPSC_CTLR_NAME ".0", katana_fixup_mpsc_pdata },
525 { MPSC_CTLR_NAME ".1", katana_fixup_mpsc_pdata },
526 #endif
527 #if defined(CONFIG_MV643XX_ETH)
528 { MV643XX_ETH_NAME ".0", katana_fixup_eth_pdata },
529 { MV643XX_ETH_NAME ".1", katana_fixup_eth_pdata },
530 { MV643XX_ETH_NAME ".2", katana_fixup_eth_pdata },
531 #endif
532 };
533 struct platform_device *pdev;
534 int i;
535
536 if (dev && dev->bus_id)
537 for (i=0; i<ARRAY_SIZE(dev_map); i++)
538 if (!strncmp(dev->bus_id, dev_map[i].bus_id,
539 BUS_ID_SIZE)) {
540
541 pdev = container_of(dev,
542 struct platform_device, dev);
543 dev_map[i].rtn(pdev);
544 }
545
546 return 0;
547 }
548
549 #ifdef CONFIG_MTD_PHYSMAP
550
551 #ifndef MB
552 #define MB (1 << 20)
553 #endif
554
555 /*
556 * MTD Layout depends on amount of soldered FLASH in system. Sizes in MB.
557 *
558 * FLASH Amount: 128 64 32 16
559 * ------------- --- -- -- --
560 * Monitor: 1 1 1 1
561 * Primary Kernel: 1.5 1.5 1.5 1.5
562 * Primary fs: 30 30 <end> <end>
563 * Secondary Kernel: 1.5 1.5 N/A N/A
564 * Secondary fs: <end> <end> N/A N/A
565 * User: <overlays entire FLASH except for "Monitor" section>
566 */
567 static int __init
568 katana_setup_mtd(void)
569 {
570 u32 size;
571 int ptbl_entries;
572 static struct mtd_partition *ptbl;
573
574 size = katana_flash_size_0 + katana_flash_size_1;
575 if (!size)
576 return -ENOMEM;
577
578 ptbl_entries = (size >= (64*MB)) ? 6 : 4;
579
580 if ((ptbl = kmalloc(ptbl_entries * sizeof(struct mtd_partition),
581 GFP_KERNEL)) == NULL) {
582
583 printk(KERN_WARNING "Can't alloc MTD partition table\n");
584 return -ENOMEM;
585 }
586 memset(ptbl, 0, ptbl_entries * sizeof(struct mtd_partition));
587
588 ptbl[0].name = "Monitor";
589 ptbl[0].size = KATANA_MTD_MONITOR_SIZE;
590 ptbl[1].name = "Primary Kernel";
591 ptbl[1].offset = MTDPART_OFS_NXTBLK;
592 ptbl[1].size = 0x00180000; /* 1.5 MB */
593 ptbl[2].name = "Primary Filesystem";
594 ptbl[2].offset = MTDPART_OFS_APPEND;
595 ptbl[2].size = MTDPART_SIZ_FULL; /* Correct for 16 & 32 MB */
596 ptbl[ptbl_entries-1].name = "User FLASH";
597 ptbl[ptbl_entries-1].offset = KATANA_MTD_MONITOR_SIZE;
598 ptbl[ptbl_entries-1].size = MTDPART_SIZ_FULL;
599
600 if (size >= (64*MB)) {
601 ptbl[2].size = 30*MB;
602 ptbl[3].name = "Secondary Kernel";
603 ptbl[3].offset = MTDPART_OFS_NXTBLK;
604 ptbl[3].size = 0x00180000; /* 1.5 MB */
605 ptbl[4].name = "Secondary Filesystem";
606 ptbl[4].offset = MTDPART_OFS_APPEND;
607 ptbl[4].size = MTDPART_SIZ_FULL;
608 }
609
610 physmap_map.size = size;
611 physmap_set_partitions(ptbl, ptbl_entries);
612 return 0;
613 }
614
615 arch_initcall(katana_setup_mtd);
616 #endif
617
618 static void
619 katana_restart(char *cmd)
620 {
621 ulong i = 10000000;
622
623 /* issue hard reset to the reset command register */
624 out_8(cpld_base + KATANA_CPLD_RST_CMD, KATANA_CPLD_RST_CMD_HR);
625
626 while (i-- > 0) ;
627 panic("restart failed\n");
628 }
629
630 static void
631 katana_halt(void)
632 {
633 u8 v;
634
635 if (katana_id == KATANA_ID_752I) {
636 v = in_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF);
637 v |= HSL_PLD_HOT_SWAP_LED_BIT;
638 out_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF, v);
639 }
640
641 while (1) ;
642 /* NOTREACHED */
643 }
644
645 static void
646 katana_power_off(void)
647 {
648 katana_halt();
649 /* NOTREACHED */
650 }
651
652 static int
653 katana_show_cpuinfo(struct seq_file *m)
654 {
655 seq_printf(m, "vendor\t\t: Artesyn Communication Products, LLC\n");
656
657 seq_printf(m, "board\t\t: ");
658
659 switch (katana_id) {
660 case KATANA_ID_3750:
661 seq_printf(m, "Katana 3750\n");
662 break;
663
664 case KATANA_ID_750I:
665 seq_printf(m, "Katana 750i\n");
666 break;
667
668 case KATANA_ID_752I:
669 seq_printf(m, "Katana 752i\n");
670 break;
671
672 default:
673 seq_printf(m, "Unknown\n");
674 break;
675 }
676
677 seq_printf(m, "product ID\t: 0x%x\n",
678 in_8(cpld_base + KATANA_CPLD_PRODUCT_ID));
679 seq_printf(m, "hardware rev\t: 0x%x\n",
680 in_8(cpld_base+KATANA_CPLD_HARDWARE_VER));
681 seq_printf(m, "PLD rev\t\t: 0x%x\n",
682 in_8(cpld_base + KATANA_CPLD_PLD_VER));
683 seq_printf(m, "PLB freq\t: %ldMhz\n",
684 (long)katana_bus_frequency / 1000000);
685 seq_printf(m, "PCI\t\t: %sMonarch\n", katana_is_monarch()? "" : "Non-");
686
687 return 0;
688 }
689
690 static void __init
691 katana_calibrate_decr(void)
692 {
693 u32 freq;
694
695 freq = katana_bus_frequency / 4;
696
697 printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
698 (long)freq / 1000000, (long)freq % 1000000);
699
700 tb_ticks_per_jiffy = freq / HZ;
701 tb_to_us = mulhwu_scale_factor(freq, 1000000);
702 }
703
704 unsigned long __init
705 katana_find_end_of_memory(void)
706 {
707 return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
708 MV64x60_TYPE_MV64360);
709 }
710
711 #if defined(CONFIG_I2C_MV64XXX) && defined(CONFIG_SENSORS_M41T00)
712 extern ulong m41t00_get_rtc_time(void);
713 extern int m41t00_set_rtc_time(ulong);
714
715 static int __init
716 katana_rtc_hookup(void)
717 {
718 struct timespec tv;
719
720 ppc_md.get_rtc_time = m41t00_get_rtc_time;
721 ppc_md.set_rtc_time = m41t00_set_rtc_time;
722
723 tv.tv_nsec = 0;
724 tv.tv_sec = (ppc_md.get_rtc_time)();
725 do_settimeofday(&tv);
726
727 return 0;
728 }
729 late_initcall(katana_rtc_hookup);
730 #endif
731
732 static inline void
733 katana_set_bat(void)
734 {
735 mb();
736 mtspr(SPRN_DBAT2U, 0xf0001ffe);
737 mtspr(SPRN_DBAT2L, 0xf000002a);
738 mb();
739 }
740
741 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
742 static void __init
743 katana_map_io(void)
744 {
745 io_block_mapping(0xf8100000, 0xf8100000, 0x00020000, _PAGE_IO);
746 }
747 #endif
748
749 void __init
750 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
751 unsigned long r6, unsigned long r7)
752 {
753 parse_bootinfo(find_bootinfo());
754
755 /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
756 * are non-zero, then we should use the board info from the bd_t
757 * structure and the cmdline pointed to by r6 instead of the
758 * information from birecs, if any. Otherwise, use the information
759 * from birecs as discovered by the preceeding call to
760 * parse_bootinfo(). This rule should work with both PPCBoot, which
761 * uses a bd_t board info structure, and the kernel boot wrapper,
762 * which uses birecs.
763 */
764 if (r3 && r6) {
765 /* copy board info structure */
766 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
767 /* copy command line */
768 *(char *)(r7+KERNELBASE) = 0;
769 strcpy(cmd_line, (char *)(r6+KERNELBASE));
770 }
771
772 isa_mem_base = 0;
773
774 ppc_md.setup_arch = katana_setup_arch;
775 ppc_md.show_cpuinfo = katana_show_cpuinfo;
776 ppc_md.init_IRQ = mv64360_init_irq;
777 ppc_md.get_irq = mv64360_get_irq;
778 ppc_md.restart = katana_restart;
779 ppc_md.power_off = katana_power_off;
780 ppc_md.halt = katana_halt;
781 ppc_md.find_end_of_memory = katana_find_end_of_memory;
782 ppc_md.calibrate_decr = katana_calibrate_decr;
783
784 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
785 ppc_md.setup_io_mappings = katana_map_io;
786 ppc_md.progress = mv64x60_mpsc_progress;
787 mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
788 #endif
789
790 #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
791 platform_notify = katana_platform_notify;
792 #endif
793
794 katana_set_bat(); /* Need for katana_find_end_of_memory and progress */
795 }
Linux kernel - Deliverables
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