arch/ppc/syslib/ppc83xx_setup.c

   1 /*
   2  * MPC83XX common board code
   3  *
   4  * Maintainer: Kumar Gala <galak@kernel.crashing.org>
   5  *
   6  * Copyright 2005 Freescale Semiconductor Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the  GNU General Public License along
  19  * with this program; if not, write  to the Free Software Foundation, Inc.,
  20  * 675 Mass Ave, Cambridge, MA 02139, USA.
  21  *
  22  * Added PCI support -- Tony Li <tony.li@freescale.com>
  23  */
  24
  25 #include <linux/config.h>
  26 #include <linux/types.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/pci.h>
  30 #include <linux/serial.h>
  31 #include <linux/tty.h>  /* for linux/serial_core.h */
  32 #include <linux/serial_core.h>
  33 #include <linux/serial_8250.h>
  34
  35 #include <asm/time.h>
  36 #include <asm/mpc83xx.h>
  37 #include <asm/mmu.h>
  38 #include <asm/ppc_sys.h>
  39 #include <asm/kgdb.h>
  40 #include <asm/delay.h>
  41 #include <asm/machdep.h>
  42
  43 #include <syslib/ppc83xx_setup.h>
  44 #if defined(CONFIG_PCI)
  45 #include <asm/delay.h>
  46 #include <syslib/ppc83xx_pci.h>
  47 #endif
  48
  49 phys_addr_t immrbar;
  50
  51 /* Return the amount of memory */
  52 unsigned long __init
  53 mpc83xx_find_end_of_memory(void)
  54 {
  55         bd_t *binfo;
  56
  57         binfo = (bd_t *) __res;
  58
  59         return binfo->bi_memsize;
  60 }
  61
  62 long __init
  63 mpc83xx_time_init(void)
  64 {
  65 #define SPCR_OFFS   0x00000110
  66 #define SPCR_TBEN   0x00400000
  67
  68         bd_t *binfo = (bd_t *)__res;
  69         u32 *spcr = ioremap(binfo->bi_immr_base + SPCR_OFFS, 4);
  70
  71         *spcr |= SPCR_TBEN;
  72
  73         iounmap(spcr);
  74
  75         return 0;
  76 }
  77
  78 /* The decrementer counts at the system (internal) clock freq divided by 4 */
  79 void __init
  80 mpc83xx_calibrate_decr(void)
  81 {
  82         bd_t *binfo = (bd_t *) __res;
  83         unsigned int freq, divisor;
  84
  85         freq = binfo->bi_busfreq;
  86         divisor = 4;
  87         tb_ticks_per_jiffy = freq / HZ / divisor;
  88         tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
  89 }
  90
  91 #ifdef CONFIG_SERIAL_8250
  92 void __init
  93 mpc83xx_early_serial_map(void)
  94 {
  95 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
  96         struct uart_port serial_req;
  97 #endif
  98         struct plat_serial8250_port *pdata;
  99         bd_t *binfo = (bd_t *) __res;
 100         pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC83xx_DUART);
 101
 102         /* Setup serial port access */
 103         pdata[0].uartclk = binfo->bi_busfreq;
 104         pdata[0].mapbase += binfo->bi_immr_base;
 105         pdata[0].membase = ioremap(pdata[0].mapbase, 0x100);
 106
 107 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 108         memset(&serial_req, 0, sizeof (serial_req));
 109         serial_req.iotype = UPIO_MEM;
 110         serial_req.mapbase = pdata[0].mapbase;
 111         serial_req.membase = pdata[0].membase;
 112         serial_req.regshift = 0;
 113
 114         gen550_init(0, &serial_req);
 115 #endif
 116
 117         pdata[1].uartclk = binfo->bi_busfreq;
 118         pdata[1].mapbase += binfo->bi_immr_base;
 119         pdata[1].membase = ioremap(pdata[1].mapbase, 0x100);
 120
 121 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 122         /* Assume gen550_init() doesn't modify serial_req */
 123         serial_req.mapbase = pdata[1].mapbase;
 124         serial_req.membase = pdata[1].membase;
 125
 126         gen550_init(1, &serial_req);
 127 #endif
 128 }
 129 #endif
 130
 131 void
 132 mpc83xx_restart(char *cmd)
 133 {
 134         volatile unsigned char __iomem *reg;
 135         unsigned char tmp;
 136
 137         reg = ioremap(BCSR_PHYS_ADDR, BCSR_SIZE);
 138
 139         local_irq_disable();
 140
 141         /*
 142          * Unlock the BCSR bits so a PRST will update the contents.
 143          * Otherwise the reset asserts but doesn't clear.
 144          */
 145         tmp = in_8(reg + BCSR_MISC_REG3_OFF);
 146         tmp |= BCSR_MISC_REG3_CNFLOCK; /* low true, high false */
 147         out_8(reg + BCSR_MISC_REG3_OFF, tmp);
 148
 149         /*
 150          * Trigger a reset via a low->high transition of the
 151          * PORESET bit.
 152          */
 153         tmp = in_8(reg + BCSR_MISC_REG2_OFF);
 154         tmp &= ~BCSR_MISC_REG2_PORESET;
 155         out_8(reg + BCSR_MISC_REG2_OFF, tmp);
 156
 157         udelay(1);
 158
 159         tmp |= BCSR_MISC_REG2_PORESET;
 160         out_8(reg + BCSR_MISC_REG2_OFF, tmp);
 161
 162         for(;;);
 163 }
 164
 165 void
 166 mpc83xx_power_off(void)
 167 {
 168         local_irq_disable();
 169         for(;;);
 170 }
 171
 172 void
 173 mpc83xx_halt(void)
 174 {
 175         local_irq_disable();
 176         for(;;);
 177 }
 178
 179 #if defined(CONFIG_PCI)
 180 void __init
 181 mpc83xx_setup_pci1(struct pci_controller *hose)
 182 {
 183         u16 reg16;
 184         volatile immr_pcictrl_t * pci_ctrl;
 185         volatile immr_ios_t * ios;
 186         bd_t *binfo = (bd_t *) __res;
 187
 188         pci_ctrl = ioremap(binfo->bi_immr_base + 0x8500, sizeof(immr_pcictrl_t));
 189         ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t));
 190
 191         /*
 192          * Configure PCI Outbound Translation Windows
 193          */
 194         ios->potar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POTAR_TA_MASK;
 195         ios->pobar0 = (MPC83xx_PCI1_LOWER_MEM >> 12) & POBAR_BA_MASK;
 196         ios->pocmr0 = POCMR_EN |
 197                 (((0xffffffff - (MPC83xx_PCI1_UPPER_MEM -
 198                                 MPC83xx_PCI1_LOWER_MEM)) >> 12) & POCMR_CM_MASK);
 199
 200         /* mapped to PCI1 IO space */
 201         ios->potar1 = (MPC83xx_PCI1_LOWER_IO >> 12) & POTAR_TA_MASK;
 202         ios->pobar1 = (MPC83xx_PCI1_IO_BASE >> 12) & POBAR_BA_MASK;
 203         ios->pocmr1 = POCMR_EN | POCMR_IO |
 204                 (((0xffffffff - (MPC83xx_PCI1_UPPER_IO -
 205                                 MPC83xx_PCI1_LOWER_IO)) >> 12) & POCMR_CM_MASK);
 206
 207         /*
 208          * Configure PCI Inbound Translation Windows
 209          */
 210         pci_ctrl->pitar1 = 0x0;
 211         pci_ctrl->pibar1 = 0x0;
 212         pci_ctrl->piebar1 = 0x0;
 213         pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
 214
 215         /*
 216          * Release PCI RST signal
 217          */
 218         pci_ctrl->gcr = 0;
 219         udelay(2000);
 220         pci_ctrl->gcr = 1;
 221         udelay(2000);
 222
 223         reg16 = 0xff;
 224         early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, &reg16);
 225         reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 226         early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16);
 227
 228         /*
 229          * Clear non-reserved bits in status register.
 230          */
 231         early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff);
 232         early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80);
 233
 234         iounmap(pci_ctrl);
 235         iounmap(ios);
 236 }
 237
 238 void __init
 239 mpc83xx_setup_pci2(struct pci_controller *hose)
 240 {
 241         u16 reg16;
 242         volatile immr_pcictrl_t * pci_ctrl;
 243         volatile immr_ios_t * ios;
 244         bd_t *binfo = (bd_t *) __res;
 245
 246         pci_ctrl = ioremap(binfo->bi_immr_base + 0x8600, sizeof(immr_pcictrl_t));
 247         ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t));
 248
 249         /*
 250          * Configure PCI Outbound Translation Windows
 251          */
 252         ios->potar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POTAR_TA_MASK;
 253         ios->pobar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POBAR_BA_MASK;
 254         ios->pocmr3 = POCMR_EN | POCMR_DST |
 255                 (((0xffffffff - (MPC83xx_PCI2_UPPER_MEM -
 256                                 MPC83xx_PCI2_LOWER_MEM)) >> 12) & POCMR_CM_MASK);
 257
 258         /* mapped to PCI2 IO space */
 259         ios->potar4 = (MPC83xx_PCI2_LOWER_IO >> 12) & POTAR_TA_MASK;
 260         ios->pobar4 = (MPC83xx_PCI2_IO_BASE >> 12) & POBAR_BA_MASK;
 261         ios->pocmr4 = POCMR_EN | POCMR_DST | POCMR_IO |
 262                 (((0xffffffff - (MPC83xx_PCI2_UPPER_IO -
 263                                 MPC83xx_PCI2_LOWER_IO)) >> 12) & POCMR_CM_MASK);
 264
 265         /*
 266          * Configure PCI Inbound Translation Windows
 267          */
 268         pci_ctrl->pitar1 = 0x0;
 269         pci_ctrl->pibar1 = 0x0;
 270         pci_ctrl->piebar1 = 0x0;
 271         pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
 272
 273         /*
 274          * Release PCI RST signal
 275          */
 276         pci_ctrl->gcr = 0;
 277         udelay(2000);
 278         pci_ctrl->gcr = 1;
 279         udelay(2000);
 280
 281         reg16 = 0xff;
 282         early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, &reg16);
 283         reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 284         early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16);
 285
 286         /*
 287          * Clear non-reserved bits in status register.
 288          */
 289         early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff);
 290         early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80);
 291
 292         iounmap(pci_ctrl);
 293         iounmap(ios);
 294 }
 295
 296 /*
 297  * PCI buses can be enabled only if SYS board combinates with PIB
 298  * (Platform IO Board) board which provide 3 PCI slots. There is 2 PCI buses
 299  * and 3 PCI slots, so people must configure the routes between them before
 300  * enable PCI bus. This routes are under the control of PCA9555PW device which
 301  * can be accessed via I2C bus 2 and are configured by firmware. Refer to
 302  * Freescale to get more information about firmware configuration.
 303  */
 304
 305 extern int mpc83xx_exclude_device(u_char bus, u_char devfn);
 306 extern int mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel,
 307                 unsigned char pin);
 308 void __init
 309 mpc83xx_setup_hose(void)
 310 {
 311         u32 val32;
 312         volatile immr_clk_t * clk;
 313         struct pci_controller * hose1;
 314 #ifdef CONFIG_MPC83xx_PCI2
 315         struct pci_controller * hose2;
 316 #endif
 317         bd_t * binfo = (bd_t *)__res;
 318
 319         clk = ioremap(binfo->bi_immr_base + 0xA00,
 320                         sizeof(immr_clk_t));
 321
 322         /*
 323          * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
 324          */
 325         val32 = clk->occr;
 326         udelay(2000);
 327         clk->occr = 0xff000000;
 328         udelay(2000);
 329
 330         iounmap(clk);
 331
 332         hose1 = pcibios_alloc_controller();
 333         if(!hose1)
 334                 return;
 335
 336         ppc_md.pci_swizzle = common_swizzle;
 337         ppc_md.pci_map_irq = mpc83xx_map_irq;
 338
 339         hose1->bus_offset = 0;
 340         hose1->first_busno = 0;
 341         hose1->last_busno = 0xff;
 342
 343         setup_indirect_pci(hose1, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
 344                         binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
 345         hose1->set_cfg_type = 1;
 346
 347         mpc83xx_setup_pci1(hose1);
 348
 349         hose1->pci_mem_offset = MPC83xx_PCI1_MEM_OFFSET;
 350         hose1->mem_space.start = MPC83xx_PCI1_LOWER_MEM;
 351         hose1->mem_space.end = MPC83xx_PCI1_UPPER_MEM;
 352
 353         hose1->io_base_phys = MPC83xx_PCI1_IO_BASE;
 354         hose1->io_space.start = MPC83xx_PCI1_LOWER_IO;
 355         hose1->io_space.end = MPC83xx_PCI1_UPPER_IO;
 356 #ifdef CONFIG_MPC83xx_PCI2
 357         isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
 358                         MPC83xx_PCI1_IO_SIZE + MPC83xx_PCI2_IO_SIZE);
 359 #else
 360         isa_io_base = (unsigned long)ioremap(MPC83xx_PCI1_IO_BASE,
 361                         MPC83xx_PCI1_IO_SIZE);
 362 #endif /* CONFIG_MPC83xx_PCI2 */
 363         hose1->io_base_virt = (void *)isa_io_base;
 364         /* setup resources */
 365         pci_init_resource(&hose1->io_resource,
 366                         MPC83xx_PCI1_LOWER_IO,
 367                         MPC83xx_PCI1_UPPER_IO,
 368                         IORESOURCE_IO, "PCI host bridge 1");
 369         pci_init_resource(&hose1->mem_resources[0],
 370                         MPC83xx_PCI1_LOWER_MEM,
 371                         MPC83xx_PCI1_UPPER_MEM,
 372                         IORESOURCE_MEM, "PCI host bridge 1");
 373
 374         ppc_md.pci_exclude_device = mpc83xx_exclude_device;
 375         hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
 376
 377 #ifdef CONFIG_MPC83xx_PCI2
 378         hose2 = pcibios_alloc_controller();
 379         if(!hose2)
 380                 return;
 381
 382         hose2->bus_offset = hose1->last_busno + 1;
 383         hose2->first_busno = hose1->last_busno + 1;
 384         hose2->last_busno = 0xff;
 385         setup_indirect_pci(hose2, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
 386                         binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
 387         hose2->set_cfg_type = 1;
 388
 389         mpc83xx_setup_pci2(hose2);
 390
 391         hose2->pci_mem_offset = MPC83xx_PCI2_MEM_OFFSET;
 392         hose2->mem_space.start = MPC83xx_PCI2_LOWER_MEM;
 393         hose2->mem_space.end = MPC83xx_PCI2_UPPER_MEM;
 394
 395         hose2->io_base_phys = MPC83xx_PCI2_IO_BASE;
 396         hose2->io_space.start = MPC83xx_PCI2_LOWER_IO;
 397         hose2->io_space.end = MPC83xx_PCI2_UPPER_IO;
 398         hose2->io_base_virt = (void *)(isa_io_base + MPC83xx_PCI1_IO_SIZE);
 399         /* setup resources */
 400         pci_init_resource(&hose2->io_resource,
 401                         MPC83xx_PCI2_LOWER_IO,
 402                         MPC83xx_PCI2_UPPER_IO,
 403                         IORESOURCE_IO, "PCI host bridge 2");
 404         pci_init_resource(&hose2->mem_resources[0],
 405                         MPC83xx_PCI2_LOWER_MEM,
 406                         MPC83xx_PCI2_UPPER_MEM,
 407                         IORESOURCE_MEM, "PCI host bridge 2");
 408
 409         hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
 410 #endif /* CONFIG_MPC83xx_PCI2 */
 411 }
 412 #endif /*CONFIG_PCI*/