4 * Copyright (C) 2001 Allan Trautman, IBM Corporation
6 * iSeries specific routines for PCI.
8 * Based on code from pci.c and iSeries_pci.c 32bit
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/kernel.h>
25 #include <linux/list.h>
26 #include <linux/string.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/ide.h>
30 #include <linux/pci.h>
35 #include <asm/machdep.h>
36 #include <asm/pci-bridge.h>
37 #include <asm/ppcdebug.h>
38 #include <asm/iommu.h>
40 #include <asm/iSeries/HvCallPci.h>
41 #include <asm/iSeries/HvCallXm.h>
42 #include <asm/iSeries/iSeries_irq.h>
43 #include <asm/iSeries/iSeries_pci.h>
44 #include <asm/iSeries/mf.h>
48 extern unsigned long io_page_mask
;
51 * Forward declares of prototypes.
53 static struct iSeries_Device_Node
*find_Device_Node(int bus
, int devfn
);
54 static void scan_PHB_slots(struct pci_controller
*Phb
);
55 static void scan_EADS_bridge(HvBusNumber Bus
, HvSubBusNumber SubBus
, int IdSel
);
56 static int scan_bridge_slot(HvBusNumber Bus
, struct HvCallPci_BridgeInfo
*Info
);
58 LIST_HEAD(iSeries_Global_Device_List
);
60 static int DeviceCount
;
62 /* Counters and control flags. */
63 static long Pci_Io_Read_Count
;
64 static long Pci_Io_Write_Count
;
66 static long Pci_Cfg_Read_Count
;
67 static long Pci_Cfg_Write_Count
;
69 static long Pci_Error_Count
;
71 static int Pci_Retry_Max
= 3; /* Only retry 3 times */
72 static int Pci_Error_Flag
= 1; /* Set Retry Error on. */
74 static struct pci_ops iSeries_pci_ops
;
78 * Each Entry size is 4 MB * 1024 Entries = 4GB I/O address space.
80 #define IOMM_TABLE_MAX_ENTRIES 1024
81 #define IOMM_TABLE_ENTRY_SIZE 0x0000000000400000UL
82 #define BASE_IO_MEMORY 0xE000000000000000UL
84 static unsigned long max_io_memory
= 0xE000000000000000UL
;
85 static long current_iomm_table_entry
;
90 static struct iSeries_Device_Node
**iomm_table
;
91 static u8
*iobar_table
;
94 * Static and Global variables
96 static char *pci_io_text
= "iSeries PCI I/O";
97 static DEFINE_SPINLOCK(iomm_table_lock
);
100 * iomm_table_initialize
102 * Allocates and initalizes the Address Translation Table and Bar
103 * Tables to get them ready for use. Must be called before any
104 * I/O space is handed out to the device BARs.
106 static void iomm_table_initialize(void)
108 spin_lock(&iomm_table_lock
);
109 iomm_table
= kmalloc(sizeof(*iomm_table
) * IOMM_TABLE_MAX_ENTRIES
,
111 iobar_table
= kmalloc(sizeof(*iobar_table
) * IOMM_TABLE_MAX_ENTRIES
,
113 spin_unlock(&iomm_table_lock
);
114 if ((iomm_table
== NULL
) || (iobar_table
== NULL
))
115 panic("PCI: I/O tables allocation failed.\n");
119 * iomm_table_allocate_entry
121 * Adds pci_dev entry in address translation table
123 * - Allocates the number of entries required in table base on BAR
125 * - Allocates starting at BASE_IO_MEMORY and increases.
126 * - The size is round up to be a multiple of entry size.
127 * - CurrentIndex is incremented to keep track of the last entry.
128 * - Builds the resource entry for allocated BARs.
130 static void iomm_table_allocate_entry(struct pci_dev
*dev
, int bar_num
)
132 struct resource
*bar_res
= &dev
->resource
[bar_num
];
133 long bar_size
= pci_resource_len(dev
, bar_num
);
136 * No space to allocate, quick exit, skip Allocation.
141 * Set Resource values.
143 spin_lock(&iomm_table_lock
);
144 bar_res
->name
= pci_io_text
;
146 IOMM_TABLE_ENTRY_SIZE
* current_iomm_table_entry
;
147 bar_res
->start
+= BASE_IO_MEMORY
;
148 bar_res
->end
= bar_res
->start
+ bar_size
- 1;
150 * Allocate the number of table entries needed for BAR.
152 while (bar_size
> 0 ) {
153 iomm_table
[current_iomm_table_entry
] = dev
->sysdata
;
154 iobar_table
[current_iomm_table_entry
] = bar_num
;
155 bar_size
-= IOMM_TABLE_ENTRY_SIZE
;
156 ++current_iomm_table_entry
;
158 max_io_memory
= BASE_IO_MEMORY
+
159 (IOMM_TABLE_ENTRY_SIZE
* current_iomm_table_entry
);
160 spin_unlock(&iomm_table_lock
);
164 * allocate_device_bars
166 * - Allocates ALL pci_dev BAR's and updates the resources with the
167 * BAR value. BARS with zero length will have the resources
168 * The HvCallPci_getBarParms is used to get the size of the BAR
169 * space. It calls iomm_table_allocate_entry to allocate
171 * - Loops through The Bar resources(0 - 5) including the ROM
174 static void allocate_device_bars(struct pci_dev
*dev
)
176 struct resource
*bar_res
;
179 for (bar_num
= 0; bar_num
<= PCI_ROM_RESOURCE
; ++bar_num
) {
180 bar_res
= &dev
->resource
[bar_num
];
181 iomm_table_allocate_entry(dev
, bar_num
);
186 * Log error information to system console.
187 * Filter out the device not there errors.
188 * PCI: EADs Connect Failed 0x18.58.10 Rc: 0x00xx
189 * PCI: Read Vendor Failed 0x18.58.10 Rc: 0x00xx
190 * PCI: Connect Bus Unit Failed 0x18.58.10 Rc: 0x00xx
192 static void pci_Log_Error(char *Error_Text
, int Bus
, int SubBus
,
193 int AgentId
, int HvRc
)
197 printk(KERN_ERR
"PCI: %s Failed: 0x%02X.%02X.%02X Rc: 0x%04X",
198 Error_Text
, Bus
, SubBus
, AgentId
, HvRc
);
202 * build_device_node(u16 Bus, int SubBus, u8 DevFn)
204 static struct iSeries_Device_Node
*build_device_node(HvBusNumber Bus
,
205 HvSubBusNumber SubBus
, int AgentId
, int Function
)
207 struct iSeries_Device_Node
*node
;
209 PPCDBG(PPCDBG_BUSWALK
,
210 "-build_device_node 0x%02X.%02X.%02X Function: %02X\n",
211 Bus
, SubBus
, AgentId
, Function
);
213 node
= kmalloc(sizeof(struct iSeries_Device_Node
), GFP_KERNEL
);
217 memset(node
, 0, sizeof(struct iSeries_Device_Node
));
218 list_add_tail(&node
->Device_List
, &iSeries_Global_Device_List
);
220 node
->DsaAddr
= ((u64
)Bus
<< 48) + ((u64
)SubBus
<< 40) + ((u64
)0x10 << 32);
222 node
->DsaAddr
.DsaAddr
= 0;
223 node
->DsaAddr
.Dsa
.busNumber
= Bus
;
224 node
->DsaAddr
.Dsa
.subBusNumber
= SubBus
;
225 node
->DsaAddr
.Dsa
.deviceId
= 0x10;
226 node
->AgentId
= AgentId
;
227 node
->DevFn
= PCI_DEVFN(ISERIES_ENCODE_DEVICE(AgentId
), Function
);
229 iSeries_Get_Location_Code(node
);
234 * unsigned long __init find_and_init_phbs(void)
237 * This function checks for all possible system PCI host bridges that connect
238 * PCI buses. The system hypervisor is queried as to the guest partition
239 * ownership status. A pci_controller is built for any bus which is partially
240 * owned or fully owned by this guest partition.
242 unsigned long __init
find_and_init_phbs(void)
244 struct pci_controller
*phb
;
247 PPCDBG(PPCDBG_BUSWALK
, "find_and_init_phbs Entry\n");
249 /* Check all possible buses. */
250 for (bus
= 0; bus
< 256; bus
++) {
251 int ret
= HvCallXm_testBus(bus
);
253 printk("bus %d appears to exist\n", bus
);
255 phb
= (struct pci_controller
*)kmalloc(sizeof(struct pci_controller
), GFP_KERNEL
);
258 pci_setup_pci_controller(phb
);
260 phb
->pci_mem_offset
= phb
->local_number
= bus
;
261 phb
->first_busno
= bus
;
262 phb
->last_busno
= bus
;
263 phb
->ops
= &iSeries_pci_ops
;
265 PPCDBG(PPCDBG_BUSWALK
, "PCI:Create iSeries pci_controller(%p), Bus: %04X\n",
268 /* Find and connect the devices. */
272 * Check for Unexpected Return code, a clue that something
275 else if (ret
!= 0x0301)
276 printk(KERN_ERR
"Unexpected Return on Probe(0x%04X): 0x%04X",
283 * iSeries_pcibios_init
285 * Chance to initialize and structures or variable before PCI Bus walk.
287 void iSeries_pcibios_init(void)
289 PPCDBG(PPCDBG_BUSWALK
, "iSeries_pcibios_init Entry.\n");
290 iomm_table_initialize();
291 find_and_init_phbs();
293 PPCDBG(PPCDBG_BUSWALK
, "iSeries_pcibios_init Exit.\n");
297 * iSeries_pci_final_fixup(void)
299 void __init
iSeries_pci_final_fixup(void)
301 struct pci_dev
*pdev
= NULL
;
302 struct iSeries_Device_Node
*node
;
306 PPCDBG(PPCDBG_BUSWALK
, "iSeries_pcibios_fixup Entry.\n");
308 /* Fix up at the device node and pci_dev relationship */
309 mf_display_src(0xC9000100);
311 printk("pcibios_final_fixup\n");
312 for_each_pci_dev(pdev
) {
313 node
= find_Device_Node(pdev
->bus
->number
, pdev
->devfn
);
314 printk("pci dev %p (%x.%x), node %p\n", pdev
,
315 pdev
->bus
->number
, pdev
->devfn
, node
);
319 pdev
->sysdata
= (void *)node
;
321 PPCDBG(PPCDBG_BUSWALK
,
322 "pdev 0x%p <==> DevNode 0x%p\n",
324 allocate_device_bars(pdev
);
325 iSeries_Device_Information(pdev
, Buffer
,
327 printk("%d. %s\n", DeviceCount
, Buffer
);
328 iommu_devnode_init_iSeries(node
);
330 printk("PCI: Device Tree not found for 0x%016lX\n",
331 (unsigned long)pdev
);
332 pdev
->irq
= node
->Irq
;
334 iSeries_activate_IRQs();
335 mf_display_src(0xC9000200);
338 void pcibios_fixup_bus(struct pci_bus
*PciBus
)
340 PPCDBG(PPCDBG_BUSWALK
, "iSeries_pcibios_fixup_bus(0x%04X) Entry.\n",
344 void pcibios_fixup_resources(struct pci_dev
*pdev
)
346 PPCDBG(PPCDBG_BUSWALK
, "fixup_resources pdev %p\n", pdev
);
350 * Loop through each node function to find usable EADs bridges.
352 static void scan_PHB_slots(struct pci_controller
*Phb
)
354 struct HvCallPci_DeviceInfo
*DevInfo
;
355 HvBusNumber bus
= Phb
->local_number
; /* System Bus */
356 const HvSubBusNumber SubBus
= 0; /* EADs is always 0. */
359 const int MaxAgents
= 8;
361 DevInfo
= (struct HvCallPci_DeviceInfo
*)
362 kmalloc(sizeof(struct HvCallPci_DeviceInfo
), GFP_KERNEL
);
367 * Probe for EADs Bridges
369 for (IdSel
= 1; IdSel
< MaxAgents
; ++IdSel
) {
370 HvRc
= HvCallPci_getDeviceInfo(bus
, SubBus
, IdSel
,
371 ISERIES_HV_ADDR(DevInfo
),
372 sizeof(struct HvCallPci_DeviceInfo
));
374 if (DevInfo
->deviceType
== HvCallPci_NodeDevice
)
375 scan_EADS_bridge(bus
, SubBus
, IdSel
);
377 printk("PCI: Invalid System Configuration(0x%02X)"
378 " for bus 0x%02x id 0x%02x.\n",
379 DevInfo
->deviceType
, bus
, IdSel
);
382 pci_Log_Error("getDeviceInfo", bus
, SubBus
, IdSel
, HvRc
);
387 static void scan_EADS_bridge(HvBusNumber bus
, HvSubBusNumber SubBus
,
390 struct HvCallPci_BridgeInfo
*BridgeInfo
;
395 BridgeInfo
= (struct HvCallPci_BridgeInfo
*)
396 kmalloc(sizeof(struct HvCallPci_BridgeInfo
), GFP_KERNEL
);
397 if (BridgeInfo
== NULL
)
400 /* Note: hvSubBus and irq is always be 0 at this level! */
401 for (Function
= 0; Function
< 8; ++Function
) {
402 AgentId
= ISERIES_PCI_AGENTID(IdSel
, Function
);
403 HvRc
= HvCallXm_connectBusUnit(bus
, SubBus
, AgentId
, 0);
405 printk("found device at bus %d idsel %d func %d (AgentId %x)\n",
406 bus
, IdSel
, Function
, AgentId
);
407 /* Connect EADs: 0x18.00.12 = 0x00 */
408 PPCDBG(PPCDBG_BUSWALK
,
409 "PCI:Connect EADs: 0x%02X.%02X.%02X\n",
410 bus
, SubBus
, AgentId
);
411 HvRc
= HvCallPci_getBusUnitInfo(bus
, SubBus
, AgentId
,
412 ISERIES_HV_ADDR(BridgeInfo
),
413 sizeof(struct HvCallPci_BridgeInfo
));
415 printk("bridge info: type %x subbus %x maxAgents %x maxsubbus %x logslot %x\n",
416 BridgeInfo
->busUnitInfo
.deviceType
,
417 BridgeInfo
->subBusNumber
,
418 BridgeInfo
->maxAgents
,
419 BridgeInfo
->maxSubBusNumber
,
420 BridgeInfo
->logicalSlotNumber
);
421 PPCDBG(PPCDBG_BUSWALK
,
422 "PCI: BridgeInfo, Type:0x%02X, SubBus:0x%02X, MaxAgents:0x%02X, MaxSubBus: 0x%02X, LSlot: 0x%02X\n",
423 BridgeInfo
->busUnitInfo
.deviceType
,
424 BridgeInfo
->subBusNumber
,
425 BridgeInfo
->maxAgents
,
426 BridgeInfo
->maxSubBusNumber
,
427 BridgeInfo
->logicalSlotNumber
);
429 if (BridgeInfo
->busUnitInfo
.deviceType
==
430 HvCallPci_BridgeDevice
) {
431 /* Scan_Bridge_Slot...: 0x18.00.12 */
432 scan_bridge_slot(bus
, BridgeInfo
);
434 printk("PCI: Invalid Bridge Configuration(0x%02X)",
435 BridgeInfo
->busUnitInfo
.deviceType
);
437 } else if (HvRc
!= 0x000B)
438 pci_Log_Error("EADs Connect",
439 bus
, SubBus
, AgentId
, HvRc
);
445 * This assumes that the node slot is always on the primary bus!
447 static int scan_bridge_slot(HvBusNumber Bus
,
448 struct HvCallPci_BridgeInfo
*BridgeInfo
)
450 struct iSeries_Device_Node
*node
;
451 HvSubBusNumber SubBus
= BridgeInfo
->subBusNumber
;
455 int IdSel
= ISERIES_GET_DEVICE_FROM_SUBBUS(SubBus
);
456 int Function
= ISERIES_GET_FUNCTION_FROM_SUBBUS(SubBus
);
457 HvAgentId EADsIdSel
= ISERIES_PCI_AGENTID(IdSel
, Function
);
459 /* iSeries_allocate_IRQ.: 0x18.00.12(0xA3) */
460 Irq
= iSeries_allocate_IRQ(Bus
, 0, EADsIdSel
);
461 PPCDBG(PPCDBG_BUSWALK
,
462 "PCI:- allocate and assign IRQ 0x%02X.%02X.%02X = 0x%02X\n",
463 Bus
, 0, EADsIdSel
, Irq
);
466 * Connect all functions of any device found.
468 for (IdSel
= 1; IdSel
<= BridgeInfo
->maxAgents
; ++IdSel
) {
469 for (Function
= 0; Function
< 8; ++Function
) {
470 HvAgentId AgentId
= ISERIES_PCI_AGENTID(IdSel
, Function
);
471 HvRc
= HvCallXm_connectBusUnit(Bus
, SubBus
,
474 pci_Log_Error("Connect Bus Unit",
475 Bus
, SubBus
, AgentId
, HvRc
);
479 HvRc
= HvCallPci_configLoad16(Bus
, SubBus
, AgentId
,
480 PCI_VENDOR_ID
, &VendorId
);
482 pci_Log_Error("Read Vendor",
483 Bus
, SubBus
, AgentId
, HvRc
);
486 printk("read vendor ID: %x\n", VendorId
);
488 /* FoundDevice: 0x18.28.10 = 0x12AE */
489 PPCDBG(PPCDBG_BUSWALK
,
490 "PCI:- FoundDevice: 0x%02X.%02X.%02X = 0x%04X, irq %d\n",
491 Bus
, SubBus
, AgentId
, VendorId
, Irq
);
492 HvRc
= HvCallPci_configStore8(Bus
, SubBus
, AgentId
,
493 PCI_INTERRUPT_LINE
, Irq
);
495 pci_Log_Error("PciCfgStore Irq Failed!",
496 Bus
, SubBus
, AgentId
, HvRc
);
499 node
= build_device_node(Bus
, SubBus
, EADsIdSel
, Function
);
501 node
->LogicalSlot
= BridgeInfo
->logicalSlotNumber
;
503 } /* for (Function = 0; Function < 8; ++Function) */
504 } /* for (IdSel = 1; IdSel <= MaxAgents; ++IdSel) */
509 * I/0 Memory copy MUST use mmio commands on iSeries
510 * To do; For performance, include the hv call directly
512 void iSeries_memset_io(volatile void __iomem
*dest
, char c
, size_t Count
)
515 long NumberOfBytes
= Count
;
517 while (NumberOfBytes
> 0) {
518 iSeries_Write_Byte(ByteValue
, dest
++);
522 EXPORT_SYMBOL(iSeries_memset_io
);
524 void iSeries_memcpy_toio(volatile void __iomem
*dest
, void *source
, size_t count
)
527 long NumberOfBytes
= count
;
529 while (NumberOfBytes
> 0) {
530 iSeries_Write_Byte(*src
++, dest
++);
534 EXPORT_SYMBOL(iSeries_memcpy_toio
);
536 void iSeries_memcpy_fromio(void *dest
, const volatile void __iomem
*src
, size_t count
)
539 long NumberOfBytes
= count
;
541 while (NumberOfBytes
> 0) {
542 *dst
++ = iSeries_Read_Byte(src
++);
546 EXPORT_SYMBOL(iSeries_memcpy_fromio
);
549 * Look down the chain to find the matching Device Device
551 static struct iSeries_Device_Node
*find_Device_Node(int bus
, int devfn
)
553 struct list_head
*pos
;
555 list_for_each(pos
, &iSeries_Global_Device_List
) {
556 struct iSeries_Device_Node
*node
=
557 list_entry(pos
, struct iSeries_Device_Node
, Device_List
);
559 if ((bus
== ISERIES_BUS(node
)) && (devfn
== node
->DevFn
))
567 * Returns the device node for the passed pci_dev
568 * Sanity Check Node PciDev to passed pci_dev
569 * If none is found, returns a NULL which the client must handle.
571 static struct iSeries_Device_Node
*get_Device_Node(struct pci_dev
*pdev
)
573 struct iSeries_Device_Node
*node
;
575 node
= pdev
->sysdata
;
576 if (node
== NULL
|| node
->PciDev
!= pdev
)
577 node
= find_Device_Node(pdev
->bus
->number
, pdev
->devfn
);
583 * Config space read and write functions.
584 * For now at least, we look for the device node for the bus and devfn
585 * that we are asked to access. It may be possible to translate the devfn
586 * to a subbus and deviceid more directly.
588 static u64 hv_cfg_read_func
[4] = {
589 HvCallPciConfigLoad8
, HvCallPciConfigLoad16
,
590 HvCallPciConfigLoad32
, HvCallPciConfigLoad32
593 static u64 hv_cfg_write_func
[4] = {
594 HvCallPciConfigStore8
, HvCallPciConfigStore16
,
595 HvCallPciConfigStore32
, HvCallPciConfigStore32
599 * Read PCI config space
601 static int iSeries_pci_read_config(struct pci_bus
*bus
, unsigned int devfn
,
602 int offset
, int size
, u32
*val
)
604 struct iSeries_Device_Node
*node
= find_Device_Node(bus
->number
, devfn
);
606 struct HvCallPci_LoadReturn ret
;
609 return PCIBIOS_DEVICE_NOT_FOUND
;
612 return PCIBIOS_BAD_REGISTER_NUMBER
;
615 fn
= hv_cfg_read_func
[(size
- 1) & 3];
616 HvCall3Ret16(fn
, &ret
, node
->DsaAddr
.DsaAddr
, offset
, 0);
620 return PCIBIOS_DEVICE_NOT_FOUND
; /* or something */
628 * Write PCI config space
631 static int iSeries_pci_write_config(struct pci_bus
*bus
, unsigned int devfn
,
632 int offset
, int size
, u32 val
)
634 struct iSeries_Device_Node
*node
= find_Device_Node(bus
->number
, devfn
);
639 return PCIBIOS_DEVICE_NOT_FOUND
;
641 return PCIBIOS_BAD_REGISTER_NUMBER
;
643 fn
= hv_cfg_write_func
[(size
- 1) & 3];
644 ret
= HvCall4(fn
, node
->DsaAddr
.DsaAddr
, offset
, val
, 0);
647 return PCIBIOS_DEVICE_NOT_FOUND
;
652 static struct pci_ops iSeries_pci_ops
= {
653 .read
= iSeries_pci_read_config
,
654 .write
= iSeries_pci_write_config
659 * -> On Failure, print and log information.
660 * Increment Retry Count, if exceeds max, panic partition.
661 * -> If in retry, print and log success
663 * PCI: Device 23.90 ReadL I/O Error( 0): 0x1234
664 * PCI: Device 23.90 ReadL Retry( 1)
665 * PCI: Device 23.90 ReadL Retry Successful(1)
667 static int CheckReturnCode(char *TextHdr
, struct iSeries_Device_Node
*DevNode
,
673 printk("PCI: %s: Device 0x%04X:%02X I/O Error(%2d): 0x%04X\n",
674 TextHdr
, DevNode
->DsaAddr
.Dsa
.busNumber
, DevNode
->DevFn
,
675 DevNode
->IoRetry
, (int)ret
);
677 * Bump the retry and check for retry count exceeded.
678 * If, Exceeded, panic the system.
680 if ((DevNode
->IoRetry
> Pci_Retry_Max
) &&
681 (Pci_Error_Flag
> 0)) {
682 mf_display_src(0xB6000103);
684 panic("PCI: Hardware I/O Error, SRC B6000103, "
685 "Automatic Reboot Disabled.\n");
687 return -1; /* Retry Try */
689 /* If retry was in progress, log success and rest retry count */
690 if (DevNode
->IoRetry
> 0)
691 DevNode
->IoRetry
= 0;
696 * Translate the I/O Address into a device node, bar, and bar offset.
697 * Note: Make sure the passed variable end up on the stack to avoid
698 * the exposure of being device global.
700 static inline struct iSeries_Device_Node
*xlate_iomm_address(
701 const volatile void __iomem
*IoAddress
,
702 u64
*dsaptr
, u64
*BarOffsetPtr
)
704 unsigned long OrigIoAddr
;
705 unsigned long BaseIoAddr
;
706 unsigned long TableIndex
;
707 struct iSeries_Device_Node
*DevNode
;
709 OrigIoAddr
= (unsigned long __force
)IoAddress
;
710 if ((OrigIoAddr
< BASE_IO_MEMORY
) || (OrigIoAddr
>= max_io_memory
))
712 BaseIoAddr
= OrigIoAddr
- BASE_IO_MEMORY
;
713 TableIndex
= BaseIoAddr
/ IOMM_TABLE_ENTRY_SIZE
;
714 DevNode
= iomm_table
[TableIndex
];
716 if (DevNode
!= NULL
) {
717 int barnum
= iobar_table
[TableIndex
];
718 *dsaptr
= DevNode
->DsaAddr
.DsaAddr
| (barnum
<< 24);
719 *BarOffsetPtr
= BaseIoAddr
% IOMM_TABLE_ENTRY_SIZE
;
721 panic("PCI: Invalid PCI IoAddress detected!\n");
726 * Read MM I/O Instructions for the iSeries
727 * On MM I/O error, all ones are returned and iSeries_pci_IoError is cal
728 * else, data is returned in big Endian format.
730 * iSeries_Read_Byte = Read Byte ( 8 bit)
731 * iSeries_Read_Word = Read Word (16 bit)
732 * iSeries_Read_Long = Read Long (32 bit)
734 u8
iSeries_Read_Byte(const volatile void __iomem
*IoAddress
)
738 struct HvCallPci_LoadReturn ret
;
739 struct iSeries_Device_Node
*DevNode
=
740 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
742 if (DevNode
== NULL
) {
743 static unsigned long last_jiffies
;
744 static int num_printed
;
746 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
747 last_jiffies
= jiffies
;
750 if (num_printed
++ < 10)
751 printk(KERN_ERR
"iSeries_Read_Byte: invalid access at IO address %p\n", IoAddress
);
756 HvCall3Ret16(HvCallPciBarLoad8
, &ret
, dsa
, BarOffset
, 0);
757 } while (CheckReturnCode("RDB", DevNode
, ret
.rc
) != 0);
759 return (u8
)ret
.value
;
761 EXPORT_SYMBOL(iSeries_Read_Byte
);
763 u16
iSeries_Read_Word(const volatile void __iomem
*IoAddress
)
767 struct HvCallPci_LoadReturn ret
;
768 struct iSeries_Device_Node
*DevNode
=
769 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
771 if (DevNode
== NULL
) {
772 static unsigned long last_jiffies
;
773 static int num_printed
;
775 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
776 last_jiffies
= jiffies
;
779 if (num_printed
++ < 10)
780 printk(KERN_ERR
"iSeries_Read_Word: invalid access at IO address %p\n", IoAddress
);
785 HvCall3Ret16(HvCallPciBarLoad16
, &ret
, dsa
,
787 } while (CheckReturnCode("RDW", DevNode
, ret
.rc
) != 0);
789 return swab16((u16
)ret
.value
);
791 EXPORT_SYMBOL(iSeries_Read_Word
);
793 u32
iSeries_Read_Long(const volatile void __iomem
*IoAddress
)
797 struct HvCallPci_LoadReturn ret
;
798 struct iSeries_Device_Node
*DevNode
=
799 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
801 if (DevNode
== NULL
) {
802 static unsigned long last_jiffies
;
803 static int num_printed
;
805 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
806 last_jiffies
= jiffies
;
809 if (num_printed
++ < 10)
810 printk(KERN_ERR
"iSeries_Read_Long: invalid access at IO address %p\n", IoAddress
);
815 HvCall3Ret16(HvCallPciBarLoad32
, &ret
, dsa
,
817 } while (CheckReturnCode("RDL", DevNode
, ret
.rc
) != 0);
819 return swab32((u32
)ret
.value
);
821 EXPORT_SYMBOL(iSeries_Read_Long
);
824 * Write MM I/O Instructions for the iSeries
826 * iSeries_Write_Byte = Write Byte (8 bit)
827 * iSeries_Write_Word = Write Word(16 bit)
828 * iSeries_Write_Long = Write Long(32 bit)
830 void iSeries_Write_Byte(u8 data
, volatile void __iomem
*IoAddress
)
835 struct iSeries_Device_Node
*DevNode
=
836 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
838 if (DevNode
== NULL
) {
839 static unsigned long last_jiffies
;
840 static int num_printed
;
842 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
843 last_jiffies
= jiffies
;
846 if (num_printed
++ < 10)
847 printk(KERN_ERR
"iSeries_Write_Byte: invalid access at IO address %p\n", IoAddress
);
851 ++Pci_Io_Write_Count
;
852 rc
= HvCall4(HvCallPciBarStore8
, dsa
, BarOffset
, data
, 0);
853 } while (CheckReturnCode("WWB", DevNode
, rc
) != 0);
855 EXPORT_SYMBOL(iSeries_Write_Byte
);
857 void iSeries_Write_Word(u16 data
, volatile void __iomem
*IoAddress
)
862 struct iSeries_Device_Node
*DevNode
=
863 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
865 if (DevNode
== NULL
) {
866 static unsigned long last_jiffies
;
867 static int num_printed
;
869 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
870 last_jiffies
= jiffies
;
873 if (num_printed
++ < 10)
874 printk(KERN_ERR
"iSeries_Write_Word: invalid access at IO address %p\n", IoAddress
);
878 ++Pci_Io_Write_Count
;
879 rc
= HvCall4(HvCallPciBarStore16
, dsa
, BarOffset
, swab16(data
), 0);
880 } while (CheckReturnCode("WWW", DevNode
, rc
) != 0);
882 EXPORT_SYMBOL(iSeries_Write_Word
);
884 void iSeries_Write_Long(u32 data
, volatile void __iomem
*IoAddress
)
889 struct iSeries_Device_Node
*DevNode
=
890 xlate_iomm_address(IoAddress
, &dsa
, &BarOffset
);
892 if (DevNode
== NULL
) {
893 static unsigned long last_jiffies
;
894 static int num_printed
;
896 if ((jiffies
- last_jiffies
) > 60 * HZ
) {
897 last_jiffies
= jiffies
;
900 if (num_printed
++ < 10)
901 printk(KERN_ERR
"iSeries_Write_Long: invalid access at IO address %p\n", IoAddress
);
905 ++Pci_Io_Write_Count
;
906 rc
= HvCall4(HvCallPciBarStore32
, dsa
, BarOffset
, swab32(data
), 0);
907 } while (CheckReturnCode("WWL", DevNode
, rc
) != 0);
909 EXPORT_SYMBOL(iSeries_Write_Long
);