a009d4dd70cb0ddf93133a52ca33717b9e755f31
3 * Copyright IBM Corp. 1999, 2000
4 * Author(s): Hartmut Penner (hp@de.ibm.com)
5 * Ulrich Weigand (weigand@de.ibm.com)
6 * Martin Schwidefsky (schwidefsky@de.ibm.com)
8 * Derived from "include/asm-i386/pgtable.h"
11 #ifndef _ASM_S390_PGTABLE_H
12 #define _ASM_S390_PGTABLE_H
15 * The Linux memory management assumes a three-level page table setup. For
16 * s390 31 bit we "fold" the mid level into the top-level page table, so
17 * that we physically have the same two-level page table as the s390 mmu
18 * expects in 31 bit mode. For s390 64 bit we use three of the five levels
19 * the hardware provides (region first and region second tables are not
22 * The "pgd_xxx()" functions are trivial for a folded two-level
23 * setup: the pgd is never bad, and a pmd always exists (as it's folded
26 * This file contains the functions and defines necessary to modify and use
27 * the S390 page table tree.
30 #include <linux/sched.h>
31 #include <linux/mm_types.h>
35 extern pgd_t swapper_pg_dir
[] __attribute__ ((aligned (4096)));
36 extern void paging_init(void);
37 extern void vmem_map_init(void);
40 * The S390 doesn't have any external MMU info: the kernel page
41 * tables contain all the necessary information.
43 #define update_mmu_cache(vma, address, ptep) do { } while (0)
44 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0)
47 * ZERO_PAGE is a global shared page that is always zero; used
48 * for zero-mapped memory areas etc..
51 extern unsigned long empty_zero_page
;
52 extern unsigned long zero_page_mask
;
54 #define ZERO_PAGE(vaddr) \
55 (virt_to_page((void *)(empty_zero_page + \
56 (((unsigned long)(vaddr)) &zero_page_mask))))
57 #define __HAVE_COLOR_ZERO_PAGE
59 #endif /* !__ASSEMBLY__ */
62 * PMD_SHIFT determines the size of the area a second-level page
64 * PGDIR_SHIFT determines what a third-level page table entry can map
69 # define PGDIR_SHIFT 20
70 #else /* CONFIG_64BIT */
73 # define PGDIR_SHIFT 42
74 #endif /* CONFIG_64BIT */
76 #define PMD_SIZE (1UL << PMD_SHIFT)
77 #define PMD_MASK (~(PMD_SIZE-1))
78 #define PUD_SIZE (1UL << PUD_SHIFT)
79 #define PUD_MASK (~(PUD_SIZE-1))
80 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
81 #define PGDIR_MASK (~(PGDIR_SIZE-1))
84 * entries per page directory level: the S390 is two-level, so
85 * we don't really have any PMD directory physically.
86 * for S390 segment-table entries are combined to one PGD
87 * that leads to 1024 pte per pgd
89 #define PTRS_PER_PTE 256
91 #define PTRS_PER_PMD 1
92 #define PTRS_PER_PUD 1
93 #else /* CONFIG_64BIT */
94 #define PTRS_PER_PMD 2048
95 #define PTRS_PER_PUD 2048
96 #endif /* CONFIG_64BIT */
97 #define PTRS_PER_PGD 2048
99 #define FIRST_USER_ADDRESS 0
101 #define pte_ERROR(e) \
102 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e))
103 #define pmd_ERROR(e) \
104 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e))
105 #define pud_ERROR(e) \
106 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e))
107 #define pgd_ERROR(e) \
108 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e))
112 * The vmalloc and module area will always be on the topmost area of the kernel
113 * mapping. We reserve 96MB (31bit) / 128GB (64bit) for vmalloc and modules.
114 * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where
115 * modules will reside. That makes sure that inter module branches always
116 * happen without trampolines and in addition the placement within a 2GB frame
117 * is branch prediction unit friendly.
119 extern unsigned long VMALLOC_START
;
120 extern unsigned long VMALLOC_END
;
121 extern struct page
*vmemmap
;
123 #define VMEM_MAX_PHYS ((unsigned long) vmemmap)
126 extern unsigned long MODULES_VADDR
;
127 extern unsigned long MODULES_END
;
128 #define MODULES_VADDR MODULES_VADDR
129 #define MODULES_END MODULES_END
130 #define MODULES_LEN (1UL << 31)
134 * A 31 bit pagetable entry of S390 has following format:
137 * 00000000001111111111222222222233
138 * 01234567890123456789012345678901
140 * I Page-Invalid Bit: Page is not available for address-translation
141 * P Page-Protection Bit: Store access not possible for page
143 * A 31 bit segmenttable entry of S390 has following format:
144 * | P-table origin | |PTL
146 * 00000000001111111111222222222233
147 * 01234567890123456789012345678901
149 * I Segment-Invalid Bit: Segment is not available for address-translation
150 * C Common-Segment Bit: Segment is not private (PoP 3-30)
151 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256)
153 * The 31 bit segmenttable origin of S390 has following format:
155 * |S-table origin | | STL |
157 * 00000000001111111111222222222233
158 * 01234567890123456789012345678901
160 * X Space-Switch event:
161 * G Segment-Invalid Bit: *
162 * P Private-Space Bit: Segment is not private (PoP 3-30)
163 * S Storage-Alteration:
164 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048)
166 * A 64 bit pagetable entry of S390 has following format:
168 * 0000000000111111111122222222223333333333444444444455555555556666
169 * 0123456789012345678901234567890123456789012345678901234567890123
171 * I Page-Invalid Bit: Page is not available for address-translation
172 * P Page-Protection Bit: Store access not possible for page
173 * C Change-bit override: HW is not required to set change bit
175 * A 64 bit segmenttable entry of S390 has following format:
176 * | P-table origin | TT
177 * 0000000000111111111122222222223333333333444444444455555555556666
178 * 0123456789012345678901234567890123456789012345678901234567890123
180 * I Segment-Invalid Bit: Segment is not available for address-translation
181 * C Common-Segment Bit: Segment is not private (PoP 3-30)
182 * P Page-Protection Bit: Store access not possible for page
185 * A 64 bit region table entry of S390 has following format:
186 * | S-table origin | TF TTTL
187 * 0000000000111111111122222222223333333333444444444455555555556666
188 * 0123456789012345678901234567890123456789012345678901234567890123
190 * I Segment-Invalid Bit: Segment is not available for address-translation
195 * The 64 bit regiontable origin of S390 has following format:
196 * | region table origon | DTTL
197 * 0000000000111111111122222222223333333333444444444455555555556666
198 * 0123456789012345678901234567890123456789012345678901234567890123
200 * X Space-Switch event:
201 * G Segment-Invalid Bit:
202 * P Private-Space Bit:
203 * S Storage-Alteration:
207 * A storage key has the following format:
211 * F : fetch protection bit
216 /* Hardware bits in the page table entry */
217 #define _PAGE_CO 0x100 /* HW Change-bit override */
218 #define _PAGE_RO 0x200 /* HW read-only bit */
219 #define _PAGE_INVALID 0x400 /* HW invalid bit */
221 /* Software bits in the page table entry */
222 #define _PAGE_SWT 0x001 /* SW pte type bit t */
223 #define _PAGE_SWX 0x002 /* SW pte type bit x */
224 #define _PAGE_SWC 0x004 /* SW pte changed bit (for KVM) */
225 #define _PAGE_SWR 0x008 /* SW pte referenced bit (for KVM) */
226 #define _PAGE_SPECIAL 0x010 /* SW associated with special page */
227 #define __HAVE_ARCH_PTE_SPECIAL
229 /* Set of bits not changed in pte_modify */
230 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_SWC | _PAGE_SWR)
232 /* Six different types of pages. */
233 #define _PAGE_TYPE_EMPTY 0x400
234 #define _PAGE_TYPE_NONE 0x401
235 #define _PAGE_TYPE_SWAP 0x403
236 #define _PAGE_TYPE_FILE 0x601 /* bit 0x002 is used for offset !! */
237 #define _PAGE_TYPE_RO 0x200
238 #define _PAGE_TYPE_RW 0x000
241 * Only four types for huge pages, using the invalid bit and protection bit
242 * of a segment table entry.
244 #define _HPAGE_TYPE_EMPTY 0x020 /* _SEGMENT_ENTRY_INV */
245 #define _HPAGE_TYPE_NONE 0x220
246 #define _HPAGE_TYPE_RO 0x200 /* _SEGMENT_ENTRY_RO */
247 #define _HPAGE_TYPE_RW 0x000
250 * PTE type bits are rather complicated. handle_pte_fault uses pte_present,
251 * pte_none and pte_file to find out the pte type WITHOUT holding the page
252 * table lock. ptep_clear_flush on the other hand uses ptep_clear_flush to
253 * invalidate a given pte. ipte sets the hw invalid bit and clears all tlbs
254 * for the page. The page table entry is set to _PAGE_TYPE_EMPTY afterwards.
255 * This change is done while holding the lock, but the intermediate step
256 * of a previously valid pte with the hw invalid bit set can be observed by
257 * handle_pte_fault. That makes it necessary that all valid pte types with
258 * the hw invalid bit set must be distinguishable from the four pte types
259 * empty, none, swap and file.
262 * _PAGE_TYPE_EMPTY 1000 -> 1000
263 * _PAGE_TYPE_NONE 1001 -> 1001
264 * _PAGE_TYPE_SWAP 1011 -> 1011
265 * _PAGE_TYPE_FILE 11?1 -> 11?1
266 * _PAGE_TYPE_RO 0100 -> 1100
267 * _PAGE_TYPE_RW 0000 -> 1000
269 * pte_none is true for bits combinations 1000, 1010, 1100, 1110
270 * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001
271 * pte_file is true for bits combinations 1101, 1111
272 * swap pte is 1011 and 0001, 0011, 0101, 0111 are invalid.
277 /* Bits in the segment table address-space-control-element */
278 #define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */
279 #define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */
280 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
281 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
282 #define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */
284 /* Bits in the segment table entry */
285 #define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */
286 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
287 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
288 #define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */
289 #define _SEGMENT_ENTRY_PTL 0x0f /* page table length */
291 #define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL)
292 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV)
294 /* Page status table bits for virtualization */
295 #define RCP_ACC_BITS 0xf0000000UL
296 #define RCP_FP_BIT 0x08000000UL
297 #define RCP_PCL_BIT 0x00800000UL
298 #define RCP_HR_BIT 0x00400000UL
299 #define RCP_HC_BIT 0x00200000UL
300 #define RCP_GR_BIT 0x00040000UL
301 #define RCP_GC_BIT 0x00020000UL
303 /* User dirty / referenced bit for KVM's migration feature */
304 #define KVM_UR_BIT 0x00008000UL
305 #define KVM_UC_BIT 0x00004000UL
307 #else /* CONFIG_64BIT */
309 /* Bits in the segment/region table address-space-control-element */
310 #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */
311 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
312 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
313 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
314 #define _ASCE_REAL_SPACE 0x20 /* real space control */
315 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
316 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */
317 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */
318 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */
319 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
320 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */
322 /* Bits in the region table entry */
323 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */
324 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
325 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
326 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
327 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
328 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
329 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */
331 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH)
332 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INV)
333 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH)
334 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INV)
335 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH)
336 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INV)
338 #define _REGION3_ENTRY_LARGE 0x400 /* RTTE-format control, large page */
340 /* Bits in the segment table entry */
341 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */
342 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
343 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
345 #define _SEGMENT_ENTRY (0)
346 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV)
348 #define _SEGMENT_ENTRY_LARGE 0x400 /* STE-format control, large page */
349 #define _SEGMENT_ENTRY_CO 0x100 /* change-recording override */
350 #define _SEGMENT_ENTRY_SPLIT_BIT 0 /* THP splitting bit number */
351 #define _SEGMENT_ENTRY_SPLIT (1UL << _SEGMENT_ENTRY_SPLIT_BIT)
353 /* Set of bits not changed in pmd_modify */
354 #define _SEGMENT_CHG_MASK (_SEGMENT_ENTRY_ORIGIN | _SEGMENT_ENTRY_LARGE \
355 | _SEGMENT_ENTRY_SPLIT | _SEGMENT_ENTRY_CO)
357 /* Page status table bits for virtualization */
358 #define RCP_ACC_BITS 0xf000000000000000UL
359 #define RCP_FP_BIT 0x0800000000000000UL
360 #define RCP_PCL_BIT 0x0080000000000000UL
361 #define RCP_HR_BIT 0x0040000000000000UL
362 #define RCP_HC_BIT 0x0020000000000000UL
363 #define RCP_GR_BIT 0x0004000000000000UL
364 #define RCP_GC_BIT 0x0002000000000000UL
366 /* User dirty / referenced bit for KVM's migration feature */
367 #define KVM_UR_BIT 0x0000800000000000UL
368 #define KVM_UC_BIT 0x0000400000000000UL
370 #endif /* CONFIG_64BIT */
373 * A user page table pointer has the space-switch-event bit, the
374 * private-space-control bit and the storage-alteration-event-control
375 * bit set. A kernel page table pointer doesn't need them.
377 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
381 * Page protection definitions.
383 #define PAGE_NONE __pgprot(_PAGE_TYPE_NONE)
384 #define PAGE_RO __pgprot(_PAGE_TYPE_RO)
385 #define PAGE_RW __pgprot(_PAGE_TYPE_RW)
387 #define PAGE_KERNEL PAGE_RW
388 #define PAGE_SHARED PAGE_KERNEL
389 #define PAGE_COPY PAGE_RO
392 * On s390 the page table entry has an invalid bit and a read-only bit.
393 * Read permission implies execute permission and write permission
394 * implies read permission.
397 #define __P000 PAGE_NONE
398 #define __P001 PAGE_RO
399 #define __P010 PAGE_RO
400 #define __P011 PAGE_RO
401 #define __P100 PAGE_RO
402 #define __P101 PAGE_RO
403 #define __P110 PAGE_RO
404 #define __P111 PAGE_RO
406 #define __S000 PAGE_NONE
407 #define __S001 PAGE_RO
408 #define __S010 PAGE_RW
409 #define __S011 PAGE_RW
410 #define __S100 PAGE_RO
411 #define __S101 PAGE_RO
412 #define __S110 PAGE_RW
413 #define __S111 PAGE_RW
415 static inline int mm_exclusive(struct mm_struct
*mm
)
417 return likely(mm
== current
->active_mm
&&
418 atomic_read(&mm
->context
.attach_count
) <= 1);
421 static inline int mm_has_pgste(struct mm_struct
*mm
)
424 if (unlikely(mm
->context
.has_pgste
))
430 * pgd/pmd/pte query functions
434 static inline int pgd_present(pgd_t pgd
) { return 1; }
435 static inline int pgd_none(pgd_t pgd
) { return 0; }
436 static inline int pgd_bad(pgd_t pgd
) { return 0; }
438 static inline int pud_present(pud_t pud
) { return 1; }
439 static inline int pud_none(pud_t pud
) { return 0; }
440 static inline int pud_large(pud_t pud
) { return 0; }
441 static inline int pud_bad(pud_t pud
) { return 0; }
443 #else /* CONFIG_64BIT */
445 static inline int pgd_present(pgd_t pgd
)
447 if ((pgd_val(pgd
) & _REGION_ENTRY_TYPE_MASK
) < _REGION_ENTRY_TYPE_R2
)
449 return (pgd_val(pgd
) & _REGION_ENTRY_ORIGIN
) != 0UL;
452 static inline int pgd_none(pgd_t pgd
)
454 if ((pgd_val(pgd
) & _REGION_ENTRY_TYPE_MASK
) < _REGION_ENTRY_TYPE_R2
)
456 return (pgd_val(pgd
) & _REGION_ENTRY_INV
) != 0UL;
459 static inline int pgd_bad(pgd_t pgd
)
462 * With dynamic page table levels the pgd can be a region table
463 * entry or a segment table entry. Check for the bit that are
464 * invalid for either table entry.
467 ~_SEGMENT_ENTRY_ORIGIN
& ~_REGION_ENTRY_INV
&
468 ~_REGION_ENTRY_TYPE_MASK
& ~_REGION_ENTRY_LENGTH
;
469 return (pgd_val(pgd
) & mask
) != 0;
472 static inline int pud_present(pud_t pud
)
474 if ((pud_val(pud
) & _REGION_ENTRY_TYPE_MASK
) < _REGION_ENTRY_TYPE_R3
)
476 return (pud_val(pud
) & _REGION_ENTRY_ORIGIN
) != 0UL;
479 static inline int pud_none(pud_t pud
)
481 if ((pud_val(pud
) & _REGION_ENTRY_TYPE_MASK
) < _REGION_ENTRY_TYPE_R3
)
483 return (pud_val(pud
) & _REGION_ENTRY_INV
) != 0UL;
486 static inline int pud_large(pud_t pud
)
488 if ((pud_val(pud
) & _REGION_ENTRY_TYPE_MASK
) != _REGION_ENTRY_TYPE_R3
)
490 return !!(pud_val(pud
) & _REGION3_ENTRY_LARGE
);
493 static inline int pud_bad(pud_t pud
)
496 * With dynamic page table levels the pud can be a region table
497 * entry or a segment table entry. Check for the bit that are
498 * invalid for either table entry.
501 ~_SEGMENT_ENTRY_ORIGIN
& ~_REGION_ENTRY_INV
&
502 ~_REGION_ENTRY_TYPE_MASK
& ~_REGION_ENTRY_LENGTH
;
503 return (pud_val(pud
) & mask
) != 0;
506 #endif /* CONFIG_64BIT */
508 static inline int pmd_present(pmd_t pmd
)
510 unsigned long mask
= _SEGMENT_ENTRY_INV
| _SEGMENT_ENTRY_RO
;
511 return (pmd_val(pmd
) & mask
) == _HPAGE_TYPE_NONE
||
512 !(pmd_val(pmd
) & _SEGMENT_ENTRY_INV
);
515 static inline int pmd_none(pmd_t pmd
)
517 return (pmd_val(pmd
) & _SEGMENT_ENTRY_INV
) &&
518 !(pmd_val(pmd
) & _SEGMENT_ENTRY_RO
);
521 static inline int pmd_large(pmd_t pmd
)
524 return !!(pmd_val(pmd
) & _SEGMENT_ENTRY_LARGE
);
530 static inline int pmd_bad(pmd_t pmd
)
532 unsigned long mask
= ~_SEGMENT_ENTRY_ORIGIN
& ~_SEGMENT_ENTRY_INV
;
533 return (pmd_val(pmd
) & mask
) != _SEGMENT_ENTRY
;
536 #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
537 extern void pmdp_splitting_flush(struct vm_area_struct
*vma
,
538 unsigned long addr
, pmd_t
*pmdp
);
540 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
541 extern int pmdp_set_access_flags(struct vm_area_struct
*vma
,
542 unsigned long address
, pmd_t
*pmdp
,
543 pmd_t entry
, int dirty
);
545 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
546 extern int pmdp_clear_flush_young(struct vm_area_struct
*vma
,
547 unsigned long address
, pmd_t
*pmdp
);
549 #define __HAVE_ARCH_PMD_WRITE
550 static inline int pmd_write(pmd_t pmd
)
552 return (pmd_val(pmd
) & _SEGMENT_ENTRY_RO
) == 0;
555 static inline int pmd_young(pmd_t pmd
)
560 static inline int pte_none(pte_t pte
)
562 return (pte_val(pte
) & _PAGE_INVALID
) && !(pte_val(pte
) & _PAGE_SWT
);
565 static inline int pte_present(pte_t pte
)
567 unsigned long mask
= _PAGE_RO
| _PAGE_INVALID
| _PAGE_SWT
| _PAGE_SWX
;
568 return (pte_val(pte
) & mask
) == _PAGE_TYPE_NONE
||
569 (!(pte_val(pte
) & _PAGE_INVALID
) &&
570 !(pte_val(pte
) & _PAGE_SWT
));
573 static inline int pte_file(pte_t pte
)
575 unsigned long mask
= _PAGE_RO
| _PAGE_INVALID
| _PAGE_SWT
;
576 return (pte_val(pte
) & mask
) == _PAGE_TYPE_FILE
;
579 static inline int pte_special(pte_t pte
)
581 return (pte_val(pte
) & _PAGE_SPECIAL
);
584 #define __HAVE_ARCH_PTE_SAME
585 static inline int pte_same(pte_t a
, pte_t b
)
587 return pte_val(a
) == pte_val(b
);
590 static inline pgste_t
pgste_get_lock(pte_t
*ptep
)
592 unsigned long new = 0;
600 " nihh %0,0xff7f\n" /* clear RCP_PCL_BIT in old */
601 " oihh %1,0x0080\n" /* set RCP_PCL_BIT in new */
604 : "=&d" (old
), "=&d" (new), "=Q" (ptep
[PTRS_PER_PTE
])
605 : "Q" (ptep
[PTRS_PER_PTE
]) : "cc");
610 static inline void pgste_set_unlock(pte_t
*ptep
, pgste_t pgste
)
614 " nihh %1,0xff7f\n" /* clear RCP_PCL_BIT */
616 : "=Q" (ptep
[PTRS_PER_PTE
])
617 : "d" (pgste_val(pgste
)), "Q" (ptep
[PTRS_PER_PTE
]) : "cc");
622 static inline pgste_t
pgste_update_all(pte_t
*ptep
, pgste_t pgste
)
625 unsigned long address
, bits
;
628 if (!pte_present(*ptep
))
630 address
= pte_val(*ptep
) & PAGE_MASK
;
631 skey
= page_get_storage_key(address
);
632 bits
= skey
& (_PAGE_CHANGED
| _PAGE_REFERENCED
);
633 /* Clear page changed & referenced bit in the storage key */
634 if (bits
& _PAGE_CHANGED
)
635 page_set_storage_key(address
, skey
^ bits
, 1);
637 page_reset_referenced(address
);
638 /* Transfer page changed & referenced bit to guest bits in pgste */
639 pgste_val(pgste
) |= bits
<< 48; /* RCP_GR_BIT & RCP_GC_BIT */
640 /* Get host changed & referenced bits from pgste */
641 bits
|= (pgste_val(pgste
) & (RCP_HR_BIT
| RCP_HC_BIT
)) >> 52;
642 /* Clear host bits in pgste. */
643 pgste_val(pgste
) &= ~(RCP_HR_BIT
| RCP_HC_BIT
);
644 pgste_val(pgste
) &= ~(RCP_ACC_BITS
| RCP_FP_BIT
);
645 /* Copy page access key and fetch protection bit to pgste */
647 (unsigned long) (skey
& (_PAGE_ACC_BITS
| _PAGE_FP_BIT
)) << 56;
648 /* Transfer changed and referenced to kvm user bits */
649 pgste_val(pgste
) |= bits
<< 45; /* KVM_UR_BIT & KVM_UC_BIT */
650 /* Transfer changed & referenced to pte sofware bits */
651 pte_val(*ptep
) |= bits
<< 1; /* _PAGE_SWR & _PAGE_SWC */
657 static inline pgste_t
pgste_update_young(pte_t
*ptep
, pgste_t pgste
)
662 if (!pte_present(*ptep
))
664 young
= page_reset_referenced(pte_val(*ptep
) & PAGE_MASK
);
665 /* Transfer page referenced bit to pte software bit (host view) */
666 if (young
|| (pgste_val(pgste
) & RCP_HR_BIT
))
667 pte_val(*ptep
) |= _PAGE_SWR
;
668 /* Clear host referenced bit in pgste. */
669 pgste_val(pgste
) &= ~RCP_HR_BIT
;
670 /* Transfer page referenced bit to guest bit in pgste */
671 pgste_val(pgste
) |= (unsigned long) young
<< 50; /* set RCP_GR_BIT */
677 static inline void pgste_set_pte(pte_t
*ptep
, pgste_t pgste
, pte_t entry
)
680 unsigned long address
;
681 unsigned long okey
, nkey
;
683 if (!pte_present(entry
))
685 address
= pte_val(entry
) & PAGE_MASK
;
686 okey
= nkey
= page_get_storage_key(address
);
687 nkey
&= ~(_PAGE_ACC_BITS
| _PAGE_FP_BIT
);
688 /* Set page access key and fetch protection bit from pgste */
689 nkey
|= (pgste_val(pgste
) & (RCP_ACC_BITS
| RCP_FP_BIT
)) >> 56;
691 page_set_storage_key(address
, nkey
, 1);
696 * struct gmap_struct - guest address space
697 * @mm: pointer to the parent mm_struct
698 * @table: pointer to the page directory
699 * @asce: address space control element for gmap page table
700 * @crst_list: list of all crst tables used in the guest address space
703 struct list_head list
;
704 struct mm_struct
*mm
;
705 unsigned long *table
;
707 struct list_head crst_list
;
711 * struct gmap_rmap - reverse mapping for segment table entries
712 * @next: pointer to the next gmap_rmap structure in the list
713 * @entry: pointer to a segment table entry
716 struct list_head list
;
717 unsigned long *entry
;
721 * struct gmap_pgtable - gmap information attached to a page table
722 * @vmaddr: address of the 1MB segment in the process virtual memory
723 * @mapper: list of segment table entries maping a page table
725 struct gmap_pgtable
{
726 unsigned long vmaddr
;
727 struct list_head mapper
;
730 struct gmap
*gmap_alloc(struct mm_struct
*mm
);
731 void gmap_free(struct gmap
*gmap
);
732 void gmap_enable(struct gmap
*gmap
);
733 void gmap_disable(struct gmap
*gmap
);
734 int gmap_map_segment(struct gmap
*gmap
, unsigned long from
,
735 unsigned long to
, unsigned long length
);
736 int gmap_unmap_segment(struct gmap
*gmap
, unsigned long to
, unsigned long len
);
737 unsigned long __gmap_fault(unsigned long address
, struct gmap
*);
738 unsigned long gmap_fault(unsigned long address
, struct gmap
*);
739 void gmap_discard(unsigned long from
, unsigned long to
, struct gmap
*);
742 * Certain architectures need to do special things when PTEs
743 * within a page table are directly modified. Thus, the following
744 * hook is made available.
746 static inline void set_pte_at(struct mm_struct
*mm
, unsigned long addr
,
747 pte_t
*ptep
, pte_t entry
)
751 if (mm_has_pgste(mm
)) {
752 pgste
= pgste_get_lock(ptep
);
753 pgste_set_pte(ptep
, pgste
, entry
);
755 pgste_set_unlock(ptep
, pgste
);
761 * query functions pte_write/pte_dirty/pte_young only work if
762 * pte_present() is true. Undefined behaviour if not..
764 static inline int pte_write(pte_t pte
)
766 return (pte_val(pte
) & _PAGE_RO
) == 0;
769 static inline int pte_dirty(pte_t pte
)
772 if (pte_val(pte
) & _PAGE_SWC
)
778 static inline int pte_young(pte_t pte
)
781 if (pte_val(pte
) & _PAGE_SWR
)
788 * pgd/pmd/pte modification functions
791 static inline void pgd_clear(pgd_t
*pgd
)
794 if ((pgd_val(*pgd
) & _REGION_ENTRY_TYPE_MASK
) == _REGION_ENTRY_TYPE_R2
)
795 pgd_val(*pgd
) = _REGION2_ENTRY_EMPTY
;
799 static inline void pud_clear(pud_t
*pud
)
802 if ((pud_val(*pud
) & _REGION_ENTRY_TYPE_MASK
) == _REGION_ENTRY_TYPE_R3
)
803 pud_val(*pud
) = _REGION3_ENTRY_EMPTY
;
807 static inline void pmd_clear(pmd_t
*pmdp
)
809 pmd_val(*pmdp
) = _SEGMENT_ENTRY_EMPTY
;
812 static inline void pte_clear(struct mm_struct
*mm
, unsigned long addr
, pte_t
*ptep
)
814 pte_val(*ptep
) = _PAGE_TYPE_EMPTY
;
818 * The following pte modification functions only work if
819 * pte_present() is true. Undefined behaviour if not..
821 static inline pte_t
pte_modify(pte_t pte
, pgprot_t newprot
)
823 pte_val(pte
) &= _PAGE_CHG_MASK
;
824 pte_val(pte
) |= pgprot_val(newprot
);
828 static inline pte_t
pte_wrprotect(pte_t pte
)
830 /* Do not clobber _PAGE_TYPE_NONE pages! */
831 if (!(pte_val(pte
) & _PAGE_INVALID
))
832 pte_val(pte
) |= _PAGE_RO
;
836 static inline pte_t
pte_mkwrite(pte_t pte
)
838 pte_val(pte
) &= ~_PAGE_RO
;
842 static inline pte_t
pte_mkclean(pte_t pte
)
845 pte_val(pte
) &= ~_PAGE_SWC
;
850 static inline pte_t
pte_mkdirty(pte_t pte
)
855 static inline pte_t
pte_mkold(pte_t pte
)
858 pte_val(pte
) &= ~_PAGE_SWR
;
863 static inline pte_t
pte_mkyoung(pte_t pte
)
868 static inline pte_t
pte_mkspecial(pte_t pte
)
870 pte_val(pte
) |= _PAGE_SPECIAL
;
874 #ifdef CONFIG_HUGETLB_PAGE
875 static inline pte_t
pte_mkhuge(pte_t pte
)
878 * PROT_NONE needs to be remapped from the pte type to the ste type.
879 * The HW invalid bit is also different for pte and ste. The pte
880 * invalid bit happens to be the same as the ste _SEGMENT_ENTRY_LARGE
881 * bit, so we don't have to clear it.
883 if (pte_val(pte
) & _PAGE_INVALID
) {
884 if (pte_val(pte
) & _PAGE_SWT
)
885 pte_val(pte
) |= _HPAGE_TYPE_NONE
;
886 pte_val(pte
) |= _SEGMENT_ENTRY_INV
;
889 * Clear SW pte bits SWT and SWX, there are no SW bits in a segment
892 pte_val(pte
) &= ~(_PAGE_SWT
| _PAGE_SWX
);
894 * Also set the change-override bit because we don't need dirty bit
895 * tracking for hugetlbfs pages.
897 pte_val(pte
) |= (_SEGMENT_ENTRY_LARGE
| _SEGMENT_ENTRY_CO
);
903 * Get (and clear) the user dirty bit for a pte.
905 static inline int ptep_test_and_clear_user_dirty(struct mm_struct
*mm
,
911 if (mm_has_pgste(mm
)) {
912 pgste
= pgste_get_lock(ptep
);
913 pgste
= pgste_update_all(ptep
, pgste
);
914 dirty
= !!(pgste_val(pgste
) & KVM_UC_BIT
);
915 pgste_val(pgste
) &= ~KVM_UC_BIT
;
916 pgste_set_unlock(ptep
, pgste
);
923 * Get (and clear) the user referenced bit for a pte.
925 static inline int ptep_test_and_clear_user_young(struct mm_struct
*mm
,
931 if (mm_has_pgste(mm
)) {
932 pgste
= pgste_get_lock(ptep
);
933 pgste
= pgste_update_young(ptep
, pgste
);
934 young
= !!(pgste_val(pgste
) & KVM_UR_BIT
);
935 pgste_val(pgste
) &= ~KVM_UR_BIT
;
936 pgste_set_unlock(ptep
, pgste
);
941 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
942 static inline int ptep_test_and_clear_young(struct vm_area_struct
*vma
,
943 unsigned long addr
, pte_t
*ptep
)
948 if (mm_has_pgste(vma
->vm_mm
)) {
949 pgste
= pgste_get_lock(ptep
);
950 pgste
= pgste_update_young(ptep
, pgste
);
952 *ptep
= pte_mkold(pte
);
953 pgste_set_unlock(ptep
, pgste
);
954 return pte_young(pte
);
959 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
960 static inline int ptep_clear_flush_young(struct vm_area_struct
*vma
,
961 unsigned long address
, pte_t
*ptep
)
963 /* No need to flush TLB
964 * On s390 reference bits are in storage key and never in TLB
965 * With virtualization we handle the reference bit, without we
966 * we can simply return */
967 return ptep_test_and_clear_young(vma
, address
, ptep
);
970 static inline void __ptep_ipte(unsigned long address
, pte_t
*ptep
)
972 if (!(pte_val(*ptep
) & _PAGE_INVALID
)) {
974 /* pto must point to the start of the segment table */
975 pte_t
*pto
= (pte_t
*) (((unsigned long) ptep
) & 0x7ffffc00);
977 /* ipte in zarch mode can do the math */
982 : "=m" (*ptep
) : "m" (*ptep
),
983 "a" (pto
), "a" (address
));
988 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
989 * both clear the TLB for the unmapped pte. The reason is that
990 * ptep_get_and_clear is used in common code (e.g. change_pte_range)
991 * to modify an active pte. The sequence is
992 * 1) ptep_get_and_clear
995 * On s390 the tlb needs to get flushed with the modification of the pte
996 * if the pte is active. The only way how this can be implemented is to
997 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range
1000 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
1001 static inline pte_t
ptep_get_and_clear(struct mm_struct
*mm
,
1002 unsigned long address
, pte_t
*ptep
)
1007 mm
->context
.flush_mm
= 1;
1008 if (mm_has_pgste(mm
))
1009 pgste
= pgste_get_lock(ptep
);
1012 if (!mm_exclusive(mm
))
1013 __ptep_ipte(address
, ptep
);
1014 pte_val(*ptep
) = _PAGE_TYPE_EMPTY
;
1016 if (mm_has_pgste(mm
)) {
1017 pgste
= pgste_update_all(&pte
, pgste
);
1018 pgste_set_unlock(ptep
, pgste
);
1023 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1024 static inline pte_t
ptep_modify_prot_start(struct mm_struct
*mm
,
1025 unsigned long address
,
1030 mm
->context
.flush_mm
= 1;
1031 if (mm_has_pgste(mm
))
1032 pgste_get_lock(ptep
);
1035 if (!mm_exclusive(mm
))
1036 __ptep_ipte(address
, ptep
);
1040 static inline void ptep_modify_prot_commit(struct mm_struct
*mm
,
1041 unsigned long address
,
1042 pte_t
*ptep
, pte_t pte
)
1045 if (mm_has_pgste(mm
))
1046 pgste_set_unlock(ptep
, *(pgste_t
*)(ptep
+ PTRS_PER_PTE
));
1049 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH
1050 static inline pte_t
ptep_clear_flush(struct vm_area_struct
*vma
,
1051 unsigned long address
, pte_t
*ptep
)
1056 if (mm_has_pgste(vma
->vm_mm
))
1057 pgste
= pgste_get_lock(ptep
);
1060 __ptep_ipte(address
, ptep
);
1061 pte_val(*ptep
) = _PAGE_TYPE_EMPTY
;
1063 if (mm_has_pgste(vma
->vm_mm
)) {
1064 pgste
= pgste_update_all(&pte
, pgste
);
1065 pgste_set_unlock(ptep
, pgste
);
1071 * The batched pte unmap code uses ptep_get_and_clear_full to clear the
1072 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all
1073 * tlbs of an mm if it can guarantee that the ptes of the mm_struct
1074 * cannot be accessed while the batched unmap is running. In this case
1075 * full==1 and a simple pte_clear is enough. See tlb.h.
1077 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
1078 static inline pte_t
ptep_get_and_clear_full(struct mm_struct
*mm
,
1079 unsigned long address
,
1080 pte_t
*ptep
, int full
)
1085 if (mm_has_pgste(mm
))
1086 pgste
= pgste_get_lock(ptep
);
1090 __ptep_ipte(address
, ptep
);
1091 pte_val(*ptep
) = _PAGE_TYPE_EMPTY
;
1093 if (mm_has_pgste(mm
)) {
1094 pgste
= pgste_update_all(&pte
, pgste
);
1095 pgste_set_unlock(ptep
, pgste
);
1100 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
1101 static inline pte_t
ptep_set_wrprotect(struct mm_struct
*mm
,
1102 unsigned long address
, pte_t
*ptep
)
1107 if (pte_write(pte
)) {
1108 mm
->context
.flush_mm
= 1;
1109 if (mm_has_pgste(mm
))
1110 pgste
= pgste_get_lock(ptep
);
1112 if (!mm_exclusive(mm
))
1113 __ptep_ipte(address
, ptep
);
1114 *ptep
= pte_wrprotect(pte
);
1116 if (mm_has_pgste(mm
))
1117 pgste_set_unlock(ptep
, pgste
);
1122 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
1123 static inline int ptep_set_access_flags(struct vm_area_struct
*vma
,
1124 unsigned long address
, pte_t
*ptep
,
1125 pte_t entry
, int dirty
)
1129 if (pte_same(*ptep
, entry
))
1131 if (mm_has_pgste(vma
->vm_mm
))
1132 pgste
= pgste_get_lock(ptep
);
1134 __ptep_ipte(address
, ptep
);
1137 if (mm_has_pgste(vma
->vm_mm
))
1138 pgste_set_unlock(ptep
, pgste
);
1143 * Conversion functions: convert a page and protection to a page entry,
1144 * and a page entry and page directory to the page they refer to.
1146 static inline pte_t
mk_pte_phys(unsigned long physpage
, pgprot_t pgprot
)
1149 pte_val(__pte
) = physpage
+ pgprot_val(pgprot
);
1153 static inline pte_t
mk_pte(struct page
*page
, pgprot_t pgprot
)
1155 unsigned long physpage
= page_to_phys(page
);
1157 return mk_pte_phys(physpage
, pgprot
);
1160 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
1161 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
1162 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
1163 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
1165 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
1166 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
1168 #ifndef CONFIG_64BIT
1170 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1171 #define pud_deref(pmd) ({ BUG(); 0UL; })
1172 #define pgd_deref(pmd) ({ BUG(); 0UL; })
1174 #define pud_offset(pgd, address) ((pud_t *) pgd)
1175 #define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address))
1177 #else /* CONFIG_64BIT */
1179 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1180 #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN)
1181 #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN)
1183 static inline pud_t
*pud_offset(pgd_t
*pgd
, unsigned long address
)
1185 pud_t
*pud
= (pud_t
*) pgd
;
1186 if ((pgd_val(*pgd
) & _REGION_ENTRY_TYPE_MASK
) == _REGION_ENTRY_TYPE_R2
)
1187 pud
= (pud_t
*) pgd_deref(*pgd
);
1188 return pud
+ pud_index(address
);
1191 static inline pmd_t
*pmd_offset(pud_t
*pud
, unsigned long address
)
1193 pmd_t
*pmd
= (pmd_t
*) pud
;
1194 if ((pud_val(*pud
) & _REGION_ENTRY_TYPE_MASK
) == _REGION_ENTRY_TYPE_R3
)
1195 pmd
= (pmd_t
*) pud_deref(*pud
);
1196 return pmd
+ pmd_index(address
);
1199 #endif /* CONFIG_64BIT */
1201 #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot))
1202 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
1203 #define pte_page(x) pfn_to_page(pte_pfn(x))
1205 #define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
1207 /* Find an entry in the lowest level page table.. */
1208 #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr))
1209 #define pte_offset_kernel(pmd, address) pte_offset(pmd,address)
1210 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
1211 #define pte_unmap(pte) do { } while (0)
1213 static inline void __pmd_idte(unsigned long address
, pmd_t
*pmdp
)
1215 unsigned long sto
= (unsigned long) pmdp
-
1216 pmd_index(address
) * sizeof(pmd_t
);
1218 if (!(pmd_val(*pmdp
) & _SEGMENT_ENTRY_INV
)) {
1220 " .insn rrf,0xb98e0000,%2,%3,0,0"
1222 : "m" (*pmdp
), "a" (sto
),
1223 "a" ((address
& HPAGE_MASK
))
1229 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1231 #define SEGMENT_NONE __pgprot(_HPAGE_TYPE_NONE)
1232 #define SEGMENT_RO __pgprot(_HPAGE_TYPE_RO)
1233 #define SEGMENT_RW __pgprot(_HPAGE_TYPE_RW)
1235 #define __HAVE_ARCH_PGTABLE_DEPOSIT
1236 extern void pgtable_trans_huge_deposit(struct mm_struct
*mm
, pgtable_t pgtable
);
1238 #define __HAVE_ARCH_PGTABLE_WITHDRAW
1239 extern pgtable_t
pgtable_trans_huge_withdraw(struct mm_struct
*mm
);
1241 static inline int pmd_trans_splitting(pmd_t pmd
)
1243 return pmd_val(pmd
) & _SEGMENT_ENTRY_SPLIT
;
1246 static inline void set_pmd_at(struct mm_struct
*mm
, unsigned long addr
,
1247 pmd_t
*pmdp
, pmd_t entry
)
1252 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot
)
1255 * pgprot is PAGE_NONE, PAGE_RO, or PAGE_RW (see __Pxxx / __Sxxx)
1256 * Convert to segment table entry format.
1258 if (pgprot_val(pgprot
) == pgprot_val(PAGE_NONE
))
1259 return pgprot_val(SEGMENT_NONE
);
1260 if (pgprot_val(pgprot
) == pgprot_val(PAGE_RO
))
1261 return pgprot_val(SEGMENT_RO
);
1262 return pgprot_val(SEGMENT_RW
);
1265 static inline pmd_t
pmd_modify(pmd_t pmd
, pgprot_t newprot
)
1267 pmd_val(pmd
) &= _SEGMENT_CHG_MASK
;
1268 pmd_val(pmd
) |= massage_pgprot_pmd(newprot
);
1272 static inline pmd_t
pmd_mkhuge(pmd_t pmd
)
1274 pmd_val(pmd
) |= _SEGMENT_ENTRY_LARGE
;
1278 static inline pmd_t
pmd_mkwrite(pmd_t pmd
)
1280 /* Do not clobber _HPAGE_TYPE_NONE pages! */
1281 if (!(pmd_val(pmd
) & _SEGMENT_ENTRY_INV
))
1282 pmd_val(pmd
) &= ~_SEGMENT_ENTRY_RO
;
1286 static inline pmd_t
pmd_wrprotect(pmd_t pmd
)
1288 pmd_val(pmd
) |= _SEGMENT_ENTRY_RO
;
1292 static inline pmd_t
pmd_mkdirty(pmd_t pmd
)
1294 /* No dirty bit in the segment table entry. */
1298 static inline pmd_t
pmd_mkold(pmd_t pmd
)
1300 /* No referenced bit in the segment table entry. */
1304 static inline pmd_t
pmd_mkyoung(pmd_t pmd
)
1306 /* No referenced bit in the segment table entry. */
1310 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1311 static inline int pmdp_test_and_clear_young(struct vm_area_struct
*vma
,
1312 unsigned long address
, pmd_t
*pmdp
)
1314 unsigned long pmd_addr
= pmd_val(*pmdp
) & HPAGE_MASK
;
1319 if (MACHINE_HAS_RRBM
) {
1320 counter
= PTRS_PER_PTE
>> 6;
1322 "0: .insn rre,0xb9ae0000,%0,%3\n" /* rrbm */
1326 : "=&d" (tmp
), "+&d" (rc
), "+d" (counter
),
1328 : "a" (64 * 4096UL) : "cc");
1331 counter
= PTRS_PER_PTE
;
1338 : "+d" (rc
), "+d" (counter
), "+a" (pmd_addr
)
1339 : "a" (4096UL) : "cc");
1344 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR
1345 static inline pmd_t
pmdp_get_and_clear(struct mm_struct
*mm
,
1346 unsigned long address
, pmd_t
*pmdp
)
1350 __pmd_idte(address
, pmdp
);
1355 #define __HAVE_ARCH_PMDP_CLEAR_FLUSH
1356 static inline pmd_t
pmdp_clear_flush(struct vm_area_struct
*vma
,
1357 unsigned long address
, pmd_t
*pmdp
)
1359 return pmdp_get_and_clear(vma
->vm_mm
, address
, pmdp
);
1362 #define __HAVE_ARCH_PMDP_INVALIDATE
1363 static inline void pmdp_invalidate(struct vm_area_struct
*vma
,
1364 unsigned long address
, pmd_t
*pmdp
)
1366 __pmd_idte(address
, pmdp
);
1369 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
1370 static inline void pmdp_set_wrprotect(struct mm_struct
*mm
,
1371 unsigned long address
, pmd_t
*pmdp
)
1375 if (pmd_write(pmd
)) {
1376 __pmd_idte(address
, pmdp
);
1377 set_pmd_at(mm
, address
, pmdp
, pmd_wrprotect(pmd
));
1381 static inline pmd_t
mk_pmd_phys(unsigned long physpage
, pgprot_t pgprot
)
1384 pmd_val(__pmd
) = physpage
+ massage_pgprot_pmd(pgprot
);
1388 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot))
1389 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot))
1391 static inline int pmd_trans_huge(pmd_t pmd
)
1393 return pmd_val(pmd
) & _SEGMENT_ENTRY_LARGE
;
1396 static inline int has_transparent_hugepage(void)
1398 return MACHINE_HAS_HPAGE
? 1 : 0;
1401 static inline unsigned long pmd_pfn(pmd_t pmd
)
1403 return pmd_val(pmd
) >> PAGE_SHIFT
;
1405 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1408 * 31 bit swap entry format:
1409 * A page-table entry has some bits we have to treat in a special way.
1410 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification
1411 * exception will occur instead of a page translation exception. The
1412 * specifiation exception has the bad habit not to store necessary
1413 * information in the lowcore.
1414 * Bit 21 and bit 22 are the page invalid bit and the page protection
1415 * bit. We set both to indicate a swapped page.
1416 * Bit 30 and 31 are used to distinguish the different page types. For
1417 * a swapped page these bits need to be zero.
1418 * This leaves the bits 1-19 and bits 24-29 to store type and offset.
1419 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19
1420 * plus 24 for the offset.
1421 * 0| offset |0110|o|type |00|
1422 * 0 0000000001111111111 2222 2 22222 33
1423 * 0 1234567890123456789 0123 4 56789 01
1425 * 64 bit swap entry format:
1426 * A page-table entry has some bits we have to treat in a special way.
1427 * Bits 52 and bit 55 have to be zero, otherwise an specification
1428 * exception will occur instead of a page translation exception. The
1429 * specifiation exception has the bad habit not to store necessary
1430 * information in the lowcore.
1431 * Bit 53 and bit 54 are the page invalid bit and the page protection
1432 * bit. We set both to indicate a swapped page.
1433 * Bit 62 and 63 are used to distinguish the different page types. For
1434 * a swapped page these bits need to be zero.
1435 * This leaves the bits 0-51 and bits 56-61 to store type and offset.
1436 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51
1437 * plus 56 for the offset.
1438 * | offset |0110|o|type |00|
1439 * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66
1440 * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23
1442 #ifndef CONFIG_64BIT
1443 #define __SWP_OFFSET_MASK (~0UL >> 12)
1445 #define __SWP_OFFSET_MASK (~0UL >> 11)
1447 static inline pte_t
mk_swap_pte(unsigned long type
, unsigned long offset
)
1450 offset
&= __SWP_OFFSET_MASK
;
1451 pte_val(pte
) = _PAGE_TYPE_SWAP
| ((type
& 0x1f) << 2) |
1452 ((offset
& 1UL) << 7) | ((offset
& ~1UL) << 11);
1456 #define __swp_type(entry) (((entry).val >> 2) & 0x1f)
1457 #define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1))
1458 #define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
1460 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1461 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
1463 #ifndef CONFIG_64BIT
1464 # define PTE_FILE_MAX_BITS 26
1465 #else /* CONFIG_64BIT */
1466 # define PTE_FILE_MAX_BITS 59
1467 #endif /* CONFIG_64BIT */
1469 #define pte_to_pgoff(__pte) \
1470 ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f))
1472 #define pgoff_to_pte(__off) \
1473 ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \
1474 | _PAGE_TYPE_FILE })
1476 #endif /* !__ASSEMBLY__ */
1478 #define kern_addr_valid(addr) (1)
1480 extern int vmem_add_mapping(unsigned long start
, unsigned long size
);
1481 extern int vmem_remove_mapping(unsigned long start
, unsigned long size
);
1482 extern int s390_enable_sie(void);
1485 * No page table caches to initialise
1487 #define pgtable_cache_init() do { } while (0)
1489 #include <asm-generic/pgtable.h>
1491 #endif /* _S390_PAGE_H */
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