arch/s390/include/asm/processor.h

   1 /*
   2  *  S390 version
   3  *    Copyright IBM Corp. 1999
   4  *    Author(s): Hartmut Penner (hp@de.ibm.com),
   5  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
   6  *
   7  *  Derived from "include/asm-i386/processor.h"
   8  *    Copyright (C) 1994, Linus Torvalds
   9  */
  10
  11 #ifndef __ASM_S390_PROCESSOR_H
  12 #define __ASM_S390_PROCESSOR_H
  13
  14 #ifndef __ASSEMBLY__
  15
  16 #include <linux/linkage.h>
  17 #include <linux/irqflags.h>
  18 #include <asm/cpu.h>
  19 #include <asm/page.h>
  20 #include <asm/ptrace.h>
  21 #include <asm/setup.h>
  22 #include <asm/runtime_instr.h>
  23
  24 /*
  25  * Default implementation of macro that returns current
  26  * instruction pointer ("program counter").
  27  */
  28 #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
  29
  30 static inline void get_cpu_id(struct cpuid *ptr)
  31 {
  32         asm volatile("stidp %0" : "=Q" (*ptr));
  33 }
  34
  35 extern void s390_adjust_jiffies(void);
  36 extern const struct seq_operations cpuinfo_op;
  37 extern int sysctl_ieee_emulation_warnings;
  38 extern void execve_tail(void);
  39
  40 /*
  41  * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
  42  */
  43 #ifndef CONFIG_64BIT
  44
  45 #define TASK_SIZE               (1UL << 31)
  46 #define TASK_MAX_SIZE           (1UL << 31)
  47 #define TASK_UNMAPPED_BASE      (1UL << 30)
  48
  49 #else /* CONFIG_64BIT */
  50
  51 #define TASK_SIZE_OF(tsk)       ((tsk)->mm->context.asce_limit)
  52 #define TASK_UNMAPPED_BASE      (test_thread_flag(TIF_31BIT) ? \
  53                                         (1UL << 30) : (1UL << 41))
  54 #define TASK_SIZE               TASK_SIZE_OF(current)
  55 #define TASK_MAX_SIZE           (1UL << 53)
  56
  57 #endif /* CONFIG_64BIT */
  58
  59 #ifndef CONFIG_64BIT
  60 #define STACK_TOP               (1UL << 31)
  61 #define STACK_TOP_MAX           (1UL << 31)
  62 #else /* CONFIG_64BIT */
  63 #define STACK_TOP               (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
  64 #define STACK_TOP_MAX           (1UL << 42)
  65 #endif /* CONFIG_64BIT */
  66
  67 #define HAVE_ARCH_PICK_MMAP_LAYOUT
  68
  69 typedef struct {
  70         __u32 ar4;
  71 } mm_segment_t;
  72
  73 /*
  74  * Thread structure
  75  */
  76 struct thread_struct {
  77         s390_fp_regs fp_regs;
  78         unsigned int  acrs[NUM_ACRS];
  79         unsigned long ksp;              /* kernel stack pointer             */
  80         mm_segment_t mm_segment;
  81         unsigned long gmap_addr;        /* address of last gmap fault. */
  82         struct per_regs per_user;       /* User specified PER registers */
  83         struct per_event per_event;     /* Cause of the last PER trap */
  84         unsigned long per_flags;        /* Flags to control debug behavior */
  85         /* pfault_wait is used to block the process on a pfault event */
  86         unsigned long pfault_wait;
  87         struct list_head list;
  88         /* cpu runtime instrumentation */
  89         struct runtime_instr_cb *ri_cb;
  90         int ri_signum;
  91 #ifdef CONFIG_64BIT
  92         unsigned char trap_tdb[256];    /* Transaction abort diagnose block */
  93 #endif
  94 };
  95
  96 /* Flag to disable transactions. */
  97 #define PER_FLAG_NO_TE                  1UL
  98 /* Flag to enable random transaction aborts. */
  99 #define PER_FLAG_TE_ABORT_RAND          2UL
 100 /* Flag to specify random transaction abort mode:
 101  * - abort each transaction at a random instruction before TEND if set.
 102  * - abort random transactions at a random instruction if cleared.
 103  */
 104 #define PER_FLAG_TE_ABORT_RAND_TEND     4UL
 105
 106 typedef struct thread_struct thread_struct;
 107
 108 /*
 109  * Stack layout of a C stack frame.
 110  */
 111 #ifndef __PACK_STACK
 112 struct stack_frame {
 113         unsigned long back_chain;
 114         unsigned long empty1[5];
 115         unsigned long gprs[10];
 116         unsigned int  empty2[8];
 117 };
 118 #else
 119 struct stack_frame {
 120         unsigned long empty1[5];
 121         unsigned int  empty2[8];
 122         unsigned long gprs[10];
 123         unsigned long back_chain;
 124 };
 125 #endif
 126
 127 #define ARCH_MIN_TASKALIGN      8
 128
 129 #define INIT_THREAD {                                                   \
 130         .ksp = sizeof(init_stack) + (unsigned long) &init_stack,        \
 131 }
 132
 133 /*
 134  * Do necessary setup to start up a new thread.
 135  */
 136 #define start_thread(regs, new_psw, new_stackp) do {                    \
 137         regs->psw.mask  = PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA;    \
 138         regs->psw.addr  = new_psw | PSW_ADDR_AMODE;                     \
 139         regs->gprs[15]  = new_stackp;                                   \
 140         execve_tail();                                                  \
 141 } while (0)
 142
 143 #define start_thread31(regs, new_psw, new_stackp) do {                  \
 144         regs->psw.mask  = PSW_USER_BITS | PSW_MASK_BA;                  \
 145         regs->psw.addr  = new_psw | PSW_ADDR_AMODE;                     \
 146         regs->gprs[15]  = new_stackp;                                   \
 147         crst_table_downgrade(current->mm, 1UL << 31);                   \
 148         execve_tail();                                                  \
 149 } while (0)
 150
 151 /* Forward declaration, a strange C thing */
 152 struct task_struct;
 153 struct mm_struct;
 154 struct seq_file;
 155
 156 #ifdef CONFIG_64BIT
 157 extern void show_cacheinfo(struct seq_file *m);
 158 #else
 159 static inline void show_cacheinfo(struct seq_file *m) { }
 160 #endif
 161
 162 /* Free all resources held by a thread. */
 163 extern void release_thread(struct task_struct *);
 164
 165 /*
 166  * Return saved PC of a blocked thread.
 167  */
 168 extern unsigned long thread_saved_pc(struct task_struct *t);
 169
 170 unsigned long get_wchan(struct task_struct *p);
 171 #define task_pt_regs(tsk) ((struct pt_regs *) \
 172         (task_stack_page(tsk) + THREAD_SIZE) - 1)
 173 #define KSTK_EIP(tsk)   (task_pt_regs(tsk)->psw.addr)
 174 #define KSTK_ESP(tsk)   (task_pt_regs(tsk)->gprs[15])
 175
 176 /* Has task runtime instrumentation enabled ? */
 177 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
 178
 179 static inline unsigned short stap(void)
 180 {
 181         unsigned short cpu_address;
 182
 183         asm volatile("stap %0" : "=m" (cpu_address));
 184         return cpu_address;
 185 }
 186
 187 /*
 188  * Give up the time slice of the virtual PU.
 189  */
 190 static inline void cpu_relax(void)
 191 {
 192         if (MACHINE_HAS_DIAG44)
 193                 asm volatile("diag 0,0,68");
 194         barrier();
 195 }
 196
 197 #define arch_mutex_cpu_relax()  barrier()
 198
 199 static inline void psw_set_key(unsigned int key)
 200 {
 201         asm volatile("spka 0(%0)" : : "d" (key));
 202 }
 203
 204 /*
 205  * Set PSW to specified value.
 206  */
 207 static inline void __load_psw(psw_t psw)
 208 {
 209 #ifndef CONFIG_64BIT
 210         asm volatile("lpsw  %0" : : "Q" (psw) : "cc");
 211 #else
 212         asm volatile("lpswe %0" : : "Q" (psw) : "cc");
 213 #endif
 214 }
 215
 216 /*
 217  * Set PSW mask to specified value, while leaving the
 218  * PSW addr pointing to the next instruction.
 219  */
 220 static inline void __load_psw_mask (unsigned long mask)
 221 {
 222         unsigned long addr;
 223         psw_t psw;
 224
 225         psw.mask = mask;
 226
 227 #ifndef CONFIG_64BIT
 228         asm volatile(
 229                 "       basr    %0,0\n"
 230                 "0:     ahi     %0,1f-0b\n"
 231                 "       st      %0,%O1+4(%R1)\n"
 232                 "       lpsw    %1\n"
 233                 "1:"
 234                 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
 235 #else /* CONFIG_64BIT */
 236         asm volatile(
 237                 "       larl    %0,1f\n"
 238                 "       stg     %0,%O1+8(%R1)\n"
 239                 "       lpswe   %1\n"
 240                 "1:"
 241                 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
 242 #endif /* CONFIG_64BIT */
 243 }
 244
 245 /*
 246  * Rewind PSW instruction address by specified number of bytes.
 247  */
 248 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
 249 {
 250 #ifndef CONFIG_64BIT
 251         if (psw.addr & PSW_ADDR_AMODE)
 252                 /* 31 bit mode */
 253                 return (psw.addr - ilc) | PSW_ADDR_AMODE;
 254         /* 24 bit mode */
 255         return (psw.addr - ilc) & ((1UL << 24) - 1);
 256 #else
 257         unsigned long mask;
 258
 259         mask = (psw.mask & PSW_MASK_EA) ? -1UL :
 260                (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
 261                                           (1UL << 24) - 1;
 262         return (psw.addr - ilc) & mask;
 263 #endif
 264 }
 265
 266 /*
 267  * Function to drop a processor into disabled wait state
 268  */
 269 static inline void __noreturn disabled_wait(unsigned long code)
 270 {
 271         unsigned long ctl_buf;
 272         psw_t dw_psw;
 273
 274         dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
 275         dw_psw.addr = code;
 276         /*
 277          * Store status and then load disabled wait psw,
 278          * the processor is dead afterwards
 279          */
 280 #ifndef CONFIG_64BIT
 281         asm volatile(
 282                 "       stctl   0,0,0(%2)\n"
 283                 "       ni      0(%2),0xef\n"   /* switch off protection */
 284                 "       lctl    0,0,0(%2)\n"
 285                 "       stpt    0xd8\n"         /* store timer */
 286                 "       stckc   0xe0\n"         /* store clock comparator */
 287                 "       stpx    0x108\n"        /* store prefix register */
 288                 "       stam    0,15,0x120\n"   /* store access registers */
 289                 "       std     0,0x160\n"      /* store f0 */
 290                 "       std     2,0x168\n"      /* store f2 */
 291                 "       std     4,0x170\n"      /* store f4 */
 292                 "       std     6,0x178\n"      /* store f6 */
 293                 "       stm     0,15,0x180\n"   /* store general registers */
 294                 "       stctl   0,15,0x1c0\n"   /* store control registers */
 295                 "       oi      0x1c0,0x10\n"   /* fake protection bit */
 296                 "       lpsw    0(%1)"
 297                 : "=m" (ctl_buf)
 298                 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
 299 #else /* CONFIG_64BIT */
 300         asm volatile(
 301                 "       stctg   0,0,0(%2)\n"
 302                 "       ni      4(%2),0xef\n"   /* switch off protection */
 303                 "       lctlg   0,0,0(%2)\n"
 304                 "       lghi    1,0x1000\n"
 305                 "       stpt    0x328(1)\n"     /* store timer */
 306                 "       stckc   0x330(1)\n"     /* store clock comparator */
 307                 "       stpx    0x318(1)\n"     /* store prefix register */
 308                 "       stam    0,15,0x340(1)\n"/* store access registers */
 309                 "       stfpc   0x31c(1)\n"     /* store fpu control */
 310                 "       std     0,0x200(1)\n"   /* store f0 */
 311                 "       std     1,0x208(1)\n"   /* store f1 */
 312                 "       std     2,0x210(1)\n"   /* store f2 */
 313                 "       std     3,0x218(1)\n"   /* store f3 */
 314                 "       std     4,0x220(1)\n"   /* store f4 */
 315                 "       std     5,0x228(1)\n"   /* store f5 */
 316                 "       std     6,0x230(1)\n"   /* store f6 */
 317                 "       std     7,0x238(1)\n"   /* store f7 */
 318                 "       std     8,0x240(1)\n"   /* store f8 */
 319                 "       std     9,0x248(1)\n"   /* store f9 */
 320                 "       std     10,0x250(1)\n"  /* store f10 */
 321                 "       std     11,0x258(1)\n"  /* store f11 */
 322                 "       std     12,0x260(1)\n"  /* store f12 */
 323                 "       std     13,0x268(1)\n"  /* store f13 */
 324                 "       std     14,0x270(1)\n"  /* store f14 */
 325                 "       std     15,0x278(1)\n"  /* store f15 */
 326                 "       stmg    0,15,0x280(1)\n"/* store general registers */
 327                 "       stctg   0,15,0x380(1)\n"/* store control registers */
 328                 "       oi      0x384(1),0x10\n"/* fake protection bit */
 329                 "       lpswe   0(%1)"
 330                 : "=m" (ctl_buf)
 331                 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
 332 #endif /* CONFIG_64BIT */
 333         while (1);
 334 }
 335
 336 /*
 337  * Use to set psw mask except for the first byte which
 338  * won't be changed by this function.
 339  */
 340 static inline void
 341 __set_psw_mask(unsigned long mask)
 342 {
 343         __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8)));
 344 }
 345
 346 #define local_mcck_enable() \
 347         __set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT | PSW_MASK_MCHECK)
 348 #define local_mcck_disable() \
 349         __set_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT)
 350
 351 /*
 352  * Basic Machine Check/Program Check Handler.
 353  */
 354
 355 extern void s390_base_mcck_handler(void);
 356 extern void s390_base_pgm_handler(void);
 357 extern void s390_base_ext_handler(void);
 358
 359 extern void (*s390_base_mcck_handler_fn)(void);
 360 extern void (*s390_base_pgm_handler_fn)(void);
 361 extern void (*s390_base_ext_handler_fn)(void);
 362
 363 #define ARCH_LOW_ADDRESS_LIMIT  0x7fffffffUL
 364
 365 extern int memcpy_real(void *, void *, size_t);
 366 extern void memcpy_absolute(void *, void *, size_t);
 367
 368 #define mem_assign_absolute(dest, val) {                        \
 369         __typeof__(dest) __tmp = (val);                         \
 370                                                                 \
 371         BUILD_BUG_ON(sizeof(__tmp) != sizeof(val));             \
 372         memcpy_absolute(&(dest), &__tmp, sizeof(__tmp));        \
 373 }
 374
 375 /*
 376  * Helper macro for exception table entries
 377  */
 378 #define EX_TABLE(_fault, _target)       \
 379         ".section __ex_table,\"a\"\n"   \
 380         ".align 4\n"                    \
 381         ".long  (" #_fault ") - .\n"    \
 382         ".long  (" #_target ") - .\n"   \
 383         ".previous\n"
 384
 385 #else /* __ASSEMBLY__ */
 386
 387 #define EX_TABLE(_fault, _target)       \
 388         .section __ex_table,"a" ;       \
 389         .align  4 ;                     \
 390         .long   (_fault) - . ;          \
 391         .long   (_target) - . ;         \
 392         .previous
 393
 394 #endif /* __ASSEMBLY__ */
 395
 396 #endif /* __ASM_S390_PROCESSOR_H */