s390/irq: enforce correct irqclass_sub_desc array size
[deliverable/linux.git] / arch / s390 / kernel / irq.c
1 /*
2 * Copyright IBM Corp. 2004, 2011
3 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
4 * Holger Smolinski <Holger.Smolinski@de.ibm.com>,
5 * Thomas Spatzier <tspat@de.ibm.com>,
6 *
7 * This file contains interrupt related functions.
8 */
9
10 #include <linux/kernel_stat.h>
11 #include <linux/interrupt.h>
12 #include <linux/seq_file.h>
13 #include <linux/proc_fs.h>
14 #include <linux/profile.h>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/ftrace.h>
18 #include <linux/errno.h>
19 #include <linux/slab.h>
20 #include <linux/cpu.h>
21 #include <linux/irq.h>
22 #include <asm/irq_regs.h>
23 #include <asm/cputime.h>
24 #include <asm/lowcore.h>
25 #include <asm/irq.h>
26 #include <asm/hw_irq.h>
27 #include "entry.h"
28
29 DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat);
30 EXPORT_PER_CPU_SYMBOL_GPL(irq_stat);
31
32 struct irq_class {
33 int irq;
34 char *name;
35 char *desc;
36 };
37
38 /*
39 * The list of "main" irq classes on s390. This is the list of interrupts
40 * that appear both in /proc/stat ("intr" line) and /proc/interrupts.
41 * Historically only external and I/O interrupts have been part of /proc/stat.
42 * We can't add the split external and I/O sub classes since the first field
43 * in the "intr" line in /proc/stat is supposed to be the sum of all other
44 * fields.
45 * Since the external and I/O interrupt fields are already sums we would end
46 * up with having a sum which accounts each interrupt twice.
47 */
48 static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = {
49 {.irq = EXT_INTERRUPT, .name = "EXT"},
50 {.irq = IO_INTERRUPT, .name = "I/O"},
51 {.irq = THIN_INTERRUPT, .name = "AIO"},
52 };
53
54 /*
55 * The list of split external and I/O interrupts that appear only in
56 * /proc/interrupts.
57 * In addition this list contains non external / I/O events like NMIs.
58 */
59 static const struct irq_class irqclass_sub_desc[] = {
60 {.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"},
61 {.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"},
62 {.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"},
63 {.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"},
64 {.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"},
65 {.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"},
66 {.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"},
67 {.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"},
68 {.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"},
69 {.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"},
70 {.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"},
71 {.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"},
72 {.irq = IRQEXT_CMR, .name = "CMR", .desc = "[EXT] CPU-Measurement: RI"},
73 {.irq = IRQEXT_FTP, .name = "FTP", .desc = "[EXT] HMC FTP Service"},
74 {.irq = IRQIO_CIO, .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"},
75 {.irq = IRQIO_QAI, .name = "QAI", .desc = "[I/O] QDIO Adapter Interrupt"},
76 {.irq = IRQIO_DAS, .name = "DAS", .desc = "[I/O] DASD"},
77 {.irq = IRQIO_C15, .name = "C15", .desc = "[I/O] 3215"},
78 {.irq = IRQIO_C70, .name = "C70", .desc = "[I/O] 3270"},
79 {.irq = IRQIO_TAP, .name = "TAP", .desc = "[I/O] Tape"},
80 {.irq = IRQIO_VMR, .name = "VMR", .desc = "[I/O] Unit Record Devices"},
81 {.irq = IRQIO_LCS, .name = "LCS", .desc = "[I/O] LCS"},
82 {.irq = IRQIO_CLW, .name = "CLW", .desc = "[I/O] CLAW"},
83 {.irq = IRQIO_CTC, .name = "CTC", .desc = "[I/O] CTC"},
84 {.irq = IRQIO_APB, .name = "APB", .desc = "[I/O] AP Bus"},
85 {.irq = IRQIO_ADM, .name = "ADM", .desc = "[I/O] EADM Subchannel"},
86 {.irq = IRQIO_CSC, .name = "CSC", .desc = "[I/O] CHSC Subchannel"},
87 {.irq = IRQIO_PCI, .name = "PCI", .desc = "[I/O] PCI Interrupt" },
88 {.irq = IRQIO_MSI, .name = "MSI", .desc = "[I/O] MSI Interrupt" },
89 {.irq = IRQIO_VIR, .name = "VIR", .desc = "[I/O] Virtual I/O Devices"},
90 {.irq = IRQIO_VAI, .name = "VAI", .desc = "[I/O] Virtual I/O Devices AI"},
91 {.irq = NMI_NMI, .name = "NMI", .desc = "[NMI] Machine Check"},
92 {.irq = CPU_RST, .name = "RST", .desc = "[CPU] CPU Restart"},
93 };
94
95 void __init init_IRQ(void)
96 {
97 BUILD_BUG_ON(ARRAY_SIZE(irqclass_sub_desc) != NR_ARCH_IRQS);
98 init_cio_interrupts();
99 init_airq_interrupts();
100 init_ext_interrupts();
101 }
102
103 void do_IRQ(struct pt_regs *regs, int irq)
104 {
105 struct pt_regs *old_regs;
106
107 old_regs = set_irq_regs(regs);
108 irq_enter();
109 if (S390_lowcore.int_clock >= S390_lowcore.clock_comparator)
110 /* Serve timer interrupts first. */
111 clock_comparator_work();
112 generic_handle_irq(irq);
113 irq_exit();
114 set_irq_regs(old_regs);
115 }
116
117 /*
118 * show_interrupts is needed by /proc/interrupts.
119 */
120 int show_interrupts(struct seq_file *p, void *v)
121 {
122 int index = *(loff_t *) v;
123 int cpu, irq;
124
125 get_online_cpus();
126 if (index == 0) {
127 seq_puts(p, " ");
128 for_each_online_cpu(cpu)
129 seq_printf(p, "CPU%d ", cpu);
130 seq_putc(p, '\n');
131 }
132 if (index < NR_IRQS) {
133 if (index >= NR_IRQS_BASE)
134 goto out;
135 seq_printf(p, "%s: ", irqclass_main_desc[index].name);
136 irq = irqclass_main_desc[index].irq;
137 for_each_online_cpu(cpu)
138 seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu));
139 seq_putc(p, '\n');
140 goto out;
141 }
142 for (index = 0; index < NR_ARCH_IRQS; index++) {
143 seq_printf(p, "%s: ", irqclass_sub_desc[index].name);
144 irq = irqclass_sub_desc[index].irq;
145 for_each_online_cpu(cpu)
146 seq_printf(p, "%10u ",
147 per_cpu(irq_stat, cpu).irqs[irq]);
148 if (irqclass_sub_desc[index].desc)
149 seq_printf(p, " %s", irqclass_sub_desc[index].desc);
150 seq_putc(p, '\n');
151 }
152 out:
153 put_online_cpus();
154 return 0;
155 }
156
157 unsigned int arch_dynirq_lower_bound(unsigned int from)
158 {
159 return from < NR_IRQS_BASE ? NR_IRQS_BASE : from;
160 }
161
162 /*
163 * Switch to the asynchronous interrupt stack for softirq execution.
164 */
165 void do_softirq_own_stack(void)
166 {
167 unsigned long old, new;
168
169 /* Get current stack pointer. */
170 asm volatile("la %0,0(15)" : "=a" (old));
171 /* Check against async. stack address range. */
172 new = S390_lowcore.async_stack;
173 if (((new - old) >> (PAGE_SHIFT + THREAD_ORDER)) != 0) {
174 /* Need to switch to the async. stack. */
175 new -= STACK_FRAME_OVERHEAD;
176 ((struct stack_frame *) new)->back_chain = old;
177 asm volatile(" la 15,0(%0)\n"
178 " basr 14,%2\n"
179 " la 15,0(%1)\n"
180 : : "a" (new), "a" (old),
181 "a" (__do_softirq)
182 : "0", "1", "2", "3", "4", "5", "14",
183 "cc", "memory" );
184 } else {
185 /* We are already on the async stack. */
186 __do_softirq();
187 }
188 }
189
190 /*
191 * ext_int_hash[index] is the list head for all external interrupts that hash
192 * to this index.
193 */
194 static struct hlist_head ext_int_hash[32] ____cacheline_aligned;
195
196 struct ext_int_info {
197 ext_int_handler_t handler;
198 struct hlist_node entry;
199 struct rcu_head rcu;
200 u16 code;
201 };
202
203 /* ext_int_hash_lock protects the handler lists for external interrupts */
204 static DEFINE_SPINLOCK(ext_int_hash_lock);
205
206 static inline int ext_hash(u16 code)
207 {
208 BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash)));
209
210 return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1);
211 }
212
213 int register_external_irq(u16 code, ext_int_handler_t handler)
214 {
215 struct ext_int_info *p;
216 unsigned long flags;
217 int index;
218
219 p = kmalloc(sizeof(*p), GFP_ATOMIC);
220 if (!p)
221 return -ENOMEM;
222 p->code = code;
223 p->handler = handler;
224 index = ext_hash(code);
225
226 spin_lock_irqsave(&ext_int_hash_lock, flags);
227 hlist_add_head_rcu(&p->entry, &ext_int_hash[index]);
228 spin_unlock_irqrestore(&ext_int_hash_lock, flags);
229 return 0;
230 }
231 EXPORT_SYMBOL(register_external_irq);
232
233 int unregister_external_irq(u16 code, ext_int_handler_t handler)
234 {
235 struct ext_int_info *p;
236 unsigned long flags;
237 int index = ext_hash(code);
238
239 spin_lock_irqsave(&ext_int_hash_lock, flags);
240 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
241 if (p->code == code && p->handler == handler) {
242 hlist_del_rcu(&p->entry);
243 kfree_rcu(p, rcu);
244 }
245 }
246 spin_unlock_irqrestore(&ext_int_hash_lock, flags);
247 return 0;
248 }
249 EXPORT_SYMBOL(unregister_external_irq);
250
251 static irqreturn_t do_ext_interrupt(int irq, void *dummy)
252 {
253 struct pt_regs *regs = get_irq_regs();
254 struct ext_code ext_code;
255 struct ext_int_info *p;
256 int index;
257
258 ext_code = *(struct ext_code *) &regs->int_code;
259 if (ext_code.code != EXT_IRQ_CLK_COMP)
260 set_cpu_flag(CIF_NOHZ_DELAY);
261
262 index = ext_hash(ext_code.code);
263 rcu_read_lock();
264 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
265 if (unlikely(p->code != ext_code.code))
266 continue;
267 p->handler(ext_code, regs->int_parm, regs->int_parm_long);
268 }
269 rcu_read_unlock();
270 return IRQ_HANDLED;
271 }
272
273 static struct irqaction external_interrupt = {
274 .name = "EXT",
275 .handler = do_ext_interrupt,
276 };
277
278 void __init init_ext_interrupts(void)
279 {
280 int idx;
281
282 for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++)
283 INIT_HLIST_HEAD(&ext_int_hash[idx]);
284
285 irq_set_chip_and_handler(EXT_INTERRUPT,
286 &dummy_irq_chip, handle_percpu_irq);
287 setup_irq(EXT_INTERRUPT, &external_interrupt);
288 }
289
290 static DEFINE_SPINLOCK(irq_subclass_lock);
291 static unsigned char irq_subclass_refcount[64];
292
293 void irq_subclass_register(enum irq_subclass subclass)
294 {
295 spin_lock(&irq_subclass_lock);
296 if (!irq_subclass_refcount[subclass])
297 ctl_set_bit(0, subclass);
298 irq_subclass_refcount[subclass]++;
299 spin_unlock(&irq_subclass_lock);
300 }
301 EXPORT_SYMBOL(irq_subclass_register);
302
303 void irq_subclass_unregister(enum irq_subclass subclass)
304 {
305 spin_lock(&irq_subclass_lock);
306 irq_subclass_refcount[subclass]--;
307 if (!irq_subclass_refcount[subclass])
308 ctl_clear_bit(0, subclass);
309 spin_unlock(&irq_subclass_lock);
310 }
311 EXPORT_SYMBOL(irq_subclass_unregister);
This page took 0.235842 seconds and 5 git commands to generate.