arch/sh/drivers/pci/pci-sh7751.c

   1 /*
   2  * Low-Level PCI Support for the SH7751
   3  *
   4  *  Copyright (C) 2003 - 2009  Paul Mundt
   5  *  Copyright (C) 2001  Dustin McIntire
   6  *
   7  *  With cleanup by Paul van Gool <pvangool@mimotech.com>, 2003.
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License.  See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/types.h>
  16 #include <linux/errno.h>
  17 #include <linux/io.h>
  18 #include "pci-sh4.h"
  19 #include <asm/addrspace.h>
  20
  21 static int __init __area_sdram_check(struct pci_channel *chan,
  22                                      unsigned int area)
  23 {
  24         unsigned long word;
  25
  26         word = __raw_readl(SH7751_BCR1);
  27         /* check BCR for SDRAM in area */
  28         if (((word >> area) & 1) == 0) {
  29                 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n",
  30                        area, word);
  31                 return 0;
  32         }
  33         pci_write_reg(chan, word, SH4_PCIBCR1);
  34
  35         word = __raw_readw(SH7751_BCR2);
  36         /* check BCR2 for 32bit SDRAM interface*/
  37         if (((word >> (area << 1)) & 0x3) != 0x3) {
  38                 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%lx\n",
  39                        area, word);
  40                 return 0;
  41         }
  42         pci_write_reg(chan, word, SH4_PCIBCR2);
  43
  44         return 1;
  45 }
  46
  47 static struct resource sh7751_io_resource = {
  48         .name   = "SH7751_IO",
  49         .start  = SH7751_PCI_IO_BASE,
  50         .end    = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
  51         .flags  = IORESOURCE_IO
  52 };
  53
  54 static struct resource sh7751_mem_resource = {
  55         .name   = "SH7751_mem",
  56         .start  = SH7751_PCI_MEMORY_BASE,
  57         .end    = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
  58         .flags  = IORESOURCE_MEM
  59 };
  60
  61 static struct pci_channel sh7751_pci_controller = {
  62         .pci_ops        = &sh4_pci_ops,
  63         .mem_resource   = &sh7751_mem_resource,
  64         .mem_offset     = 0x00000000,
  65         .io_resource    = &sh7751_io_resource,
  66         .io_offset      = 0x00000000,
  67         .io_map_base    = SH7751_PCI_IO_BASE,
  68 };
  69
  70 static struct sh4_pci_address_map sh7751_pci_map = {
  71         .window0        = {
  72                 .base   = SH7751_CS3_BASE_ADDR,
  73                 .size   = 0x04000000,
  74         },
  75 };
  76
  77 static int __init sh7751_pci_init(void)
  78 {
  79         struct pci_channel *chan = &sh7751_pci_controller;
  80         unsigned int id;
  81         u32 word, reg;
  82         int ret;
  83
  84         printk(KERN_NOTICE "PCI: Starting intialization.\n");
  85
  86         chan->reg_base = 0xfe200000;
  87
  88         /* check for SH7751/SH7751R hardware */
  89         id = pci_read_reg(chan, SH7751_PCICONF0);
  90         if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
  91             id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
  92                 pr_debug("PCI: This is not an SH7751(R) (%x)\n", id);
  93                 return -ENODEV;
  94         }
  95
  96         if ((ret = sh4_pci_check_direct(chan)) != 0)
  97                 return ret;
  98
  99         /* Set the BCR's to enable PCI access */
 100         reg = ctrl_inl(SH7751_BCR1);
 101         reg |= 0x80000;
 102         ctrl_outl(reg, SH7751_BCR1);
 103
 104         /* Turn the clocks back on (not done in reset)*/
 105         pci_write_reg(chan, 0, SH4_PCICLKR);
 106         /* Clear Powerdown IRQ's (not done in reset) */
 107         word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0;
 108         pci_write_reg(chan, word, SH4_PCIPINT);
 109
 110         /* set the command/status bits to:
 111          * Wait Cycle Control + Parity Enable + Bus Master +
 112          * Mem space enable
 113          */
 114         word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
 115                SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
 116         pci_write_reg(chan, word, SH7751_PCICONF1);
 117
 118         /* define this host as the host bridge */
 119         word = PCI_BASE_CLASS_BRIDGE << 24;
 120         pci_write_reg(chan, word, SH7751_PCICONF2);
 121
 122         /* Set IO and Mem windows to local address
 123          * Make PCI and local address the same for easy 1 to 1 mapping
 124          */
 125         word = sh7751_pci_map.window0.size - 1;
 126         pci_write_reg(chan, word, SH4_PCILSR0);
 127         /* Set the values on window 0 PCI config registers */
 128         word = P2SEGADDR(sh7751_pci_map.window0.base);
 129         pci_write_reg(chan, word, SH4_PCILAR0);
 130         pci_write_reg(chan, word, SH7751_PCICONF5);
 131
 132         /* Set the local 16MB PCI memory space window to
 133          * the lowest PCI mapped address
 134          */
 135         word = chan->mem_resource->start & SH4_PCIMBR_MASK;
 136         pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word);
 137         pci_write_reg(chan, word , SH4_PCIMBR);
 138
 139         /* Make sure the MSB's of IO window are set to access PCI space
 140          * correctly */
 141         word = chan->io_resource->start & SH4_PCIIOBR_MASK;
 142         pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word);
 143         pci_write_reg(chan, word, SH4_PCIIOBR);
 144
 145         /* Set PCI WCRx, BCRx's, copy from BSC locations */
 146
 147         /* check BCR for SDRAM in specified area */
 148         switch (sh7751_pci_map.window0.base) {
 149         case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(chan, 0); break;
 150         case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(chan, 1); break;
 151         case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(chan, 2); break;
 152         case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(chan, 3); break;
 153         case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(chan, 4); break;
 154         case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(chan, 5); break;
 155         case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(chan, 6); break;
 156         }
 157
 158         if (!word)
 159                 return -1;
 160
 161         /* configure the wait control registers */
 162         word = ctrl_inl(SH7751_WCR1);
 163         pci_write_reg(chan, word, SH4_PCIWCR1);
 164         word = ctrl_inl(SH7751_WCR2);
 165         pci_write_reg(chan, word, SH4_PCIWCR2);
 166         word = ctrl_inl(SH7751_WCR3);
 167         pci_write_reg(chan, word, SH4_PCIWCR3);
 168         word = ctrl_inl(SH7751_MCR);
 169         pci_write_reg(chan, word, SH4_PCIMCR);
 170
 171         /* NOTE: I'm ignoring the PCI error IRQs for now..
 172          * TODO: add support for the internal error interrupts and
 173          * DMA interrupts...
 174          */
 175
 176         pci_fixup_pcic(chan);
 177
 178         /* SH7751 init done, set central function init complete */
 179         /* use round robin mode to stop a device starving/overruning */
 180         word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
 181         pci_write_reg(chan, word, SH4_PCICR);
 182
 183         register_pci_controller(chan);
 184
 185         return 0;
 186 }
 187 arch_initcall(sh7751_pci_init);