arch/sh/drivers/pci/pci.c

   1 /*
   2  * arch/sh/drivers/pci/pci.c
   3  *
   4  * Copyright (c) 2002 M. R. Brown  <mrbrown@linux-sh.org>
   5  * Copyright (c) 2004 - 2006 Paul Mundt  <lethal@linux-sh.org>
   6  *
   7  * These functions are collected here to reduce duplication of common
   8  * code amongst the many platform-specific PCI support code files.
   9  *
  10  * These routines require the following board-specific routines:
  11  * void pcibios_fixup_irqs();
  12  *
  13  * See include/asm-sh/pci.h for more information.
  14  *
  15  * This file is subject to the terms and conditions of the GNU General Public
  16  * License.  See the file "COPYING" in the main directory of this archive
  17  * for more details.
  18  */
  19 #include <linux/kernel.h>
  20 #include <linux/pci.h>
  21 #include <linux/init.h>
  22 #include <asm/io.h>
  23
  24 static int __init pcibios_init(void)
  25 {
  26         struct pci_channel *p;
  27         struct pci_bus *bus;
  28         int busno;
  29
  30 #ifdef CONFIG_PCI_AUTO
  31         /* assign resources */
  32         busno = 0;
  33         for (p = board_pci_channels; p->pci_ops != NULL; p++)
  34                 busno = pciauto_assign_resources(busno, p) + 1;
  35 #endif
  36
  37         /* scan the buses */
  38         busno = 0;
  39         for (p= board_pci_channels; p->pci_ops != NULL; p++) {
  40                 bus = pci_scan_bus(busno, p->pci_ops, p);
  41                 busno = bus->subordinate+1;
  42         }
  43
  44         /* board-specific fixups */
  45         pcibios_fixup_irqs();
  46
  47         return 0;
  48 }
  49
  50 subsys_initcall(pcibios_init);
  51
  52 void
  53 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
  54                         struct resource *res, int resource)
  55 {
  56         u32 new, check;
  57         int reg;
  58
  59         new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
  60         if (resource < 6) {
  61                 reg = PCI_BASE_ADDRESS_0 + 4*resource;
  62         } else if (resource == PCI_ROM_RESOURCE) {
  63                 res->flags |= IORESOURCE_ROM_ENABLE;
  64                 new |= PCI_ROM_ADDRESS_ENABLE;
  65                 reg = dev->rom_base_reg;
  66         } else {
  67                 /*
  68                  * Somebody might have asked allocation of a non-standard
  69                  * resource
  70                  */
  71                 return;
  72         }
  73
  74         pci_write_config_dword(dev, reg, new);
  75         pci_read_config_dword(dev, reg, &check);
  76         if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ?
  77                 PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
  78                 printk(KERN_ERR "PCI: Error while updating region "
  79                        "%s/%d (%08x != %08x)\n", pci_name(dev), resource,
  80                        new, check);
  81         }
  82 }
  83
  84 void pcibios_align_resource(void *data, struct resource *res,
  85                             resource_size_t size, resource_size_t align)
  86                             __attribute__ ((weak));
  87
  88 /*
  89  * We need to avoid collisions with `mirrored' VGA ports
  90  * and other strange ISA hardware, so we always want the
  91  * addresses to be allocated in the 0x000-0x0ff region
  92  * modulo 0x400.
  93  */
  94 void pcibios_align_resource(void *data, struct resource *res,
  95                             resource_size_t size, resource_size_t align)
  96 {
  97         if (res->flags & IORESOURCE_IO) {
  98                 resource_size_t start = res->start;
  99
 100                 if (start & 0x300) {
 101                         start = (start + 0x3ff) & ~0x3ff;
 102                         res->start = start;
 103                 }
 104         }
 105 }
 106
 107 int pcibios_enable_device(struct pci_dev *dev, int mask)
 108 {
 109         u16 cmd, old_cmd;
 110         int idx;
 111         struct resource *r;
 112
 113         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 114         old_cmd = cmd;
 115         for(idx=0; idx<6; idx++) {
 116                 if (!(mask & (1 << idx)))
 117                         continue;
 118                 r = &dev->resource[idx];
 119                 if (!r->start && r->end) {
 120                         printk(KERN_ERR "PCI: Device %s not available because "
 121                                "of resource collisions\n", pci_name(dev));
 122                         return -EINVAL;
 123                 }
 124                 if (r->flags & IORESOURCE_IO)
 125                         cmd |= PCI_COMMAND_IO;
 126                 if (r->flags & IORESOURCE_MEM)
 127                         cmd |= PCI_COMMAND_MEMORY;
 128         }
 129         if (dev->resource[PCI_ROM_RESOURCE].start)
 130                 cmd |= PCI_COMMAND_MEMORY;
 131         if (cmd != old_cmd) {
 132                 printk(KERN_INFO "PCI: Enabling device %s (%04x -> %04x)\n",
 133                        pci_name(dev), old_cmd, cmd);
 134                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 135         }
 136         return 0;
 137 }
 138
 139 /*
 140  *  If we set up a device for bus mastering, we need to check and set
 141  *  the latency timer as it may not be properly set.
 142  */
 143 unsigned int pcibios_max_latency = 255;
 144
 145 void pcibios_set_master(struct pci_dev *dev)
 146 {
 147         u8 lat;
 148         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 149         if (lat < 16)
 150                 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
 151         else if (lat > pcibios_max_latency)
 152                 lat = pcibios_max_latency;
 153         else
 154                 return;
 155         printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n",
 156                pci_name(dev), lat);
 157         pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
 158 }
 159
 160 void __init pcibios_update_irq(struct pci_dev *dev, int irq)
 161 {
 162         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 163 }
 164
 165 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
 166 {
 167         unsigned long start = pci_resource_start(dev, bar);
 168         unsigned long len = pci_resource_len(dev, bar);
 169         unsigned long flags = pci_resource_flags(dev, bar);
 170
 171         if (!len || !start)
 172                 return NULL;
 173         if (maxlen && len > maxlen)
 174                 len = maxlen;
 175
 176         /*
 177          * Presently the IORESOURCE_MEM case is a bit special, most
 178          * SH7751 style PCI controllers have PCI memory at a fixed
 179          * location in the address space where no remapping is desired
 180          * (traditionally at 0xfd000000). Once this changes, the
 181          * IORESOURCE_MEM case will have to switch to using ioremap() and
 182          * more care will have to be taken to inhibit page table mapping
 183          * for legacy cores.
 184          *
 185          * For now everything wraps to ioport_map(), since boards that
 186          * have PCI will be able to check the address range properly on
 187          * their own.
 188          *                      -- PFM.
 189          */
 190         if (flags & (IORESOURCE_IO | IORESOURCE_MEM))
 191                 return ioport_map(start, len);
 192
 193         return NULL;
 194 }
 195
 196 void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
 197 {
 198         iounmap(addr);
 199 }
 200
 201 EXPORT_SYMBOL(pci_iomap);
 202 EXPORT_SYMBOL(pci_iounmap);