arch/sh/include/asm/entry-macros.S

   1 ! entry.S macro define
   2
   3         .macro  cli
   4         stc     sr, r0
   5         or      #0xf0, r0
   6         ldc     r0, sr
   7         .endm
   8
   9         .macro  sti
  10         mov     #0xfffffff0, r11
  11         extu.b  r11, r11
  12         not     r11, r11
  13         stc     sr, r10
  14         and     r11, r10
  15 #ifdef CONFIG_CPU_HAS_SR_RB
  16         stc     k_g_imask, r11
  17         or      r11, r10
  18 #endif
  19         ldc     r10, sr
  20         .endm
  21
  22         .macro  get_current_thread_info, ti, tmp
  23 #ifdef CONFIG_CPU_HAS_SR_RB
  24         stc     r7_bank, \ti
  25 #else
  26         mov     #((THREAD_SIZE - 1) >> 10) ^ 0xff, \tmp
  27         shll8   \tmp
  28         shll2   \tmp
  29         mov     r15, \ti
  30         and     \tmp, \ti
  31 #endif
  32         .endm
  33
  34 #ifdef CONFIG_TRACE_IRQFLAGS
  35
  36         .macro  TRACE_IRQS_ON
  37         mov.l   r0, @-r15
  38         mov.l   r1, @-r15
  39         mov.l   r2, @-r15
  40         mov.l   r3, @-r15
  41         mov.l   r4, @-r15
  42         mov.l   r5, @-r15
  43         mov.l   r6, @-r15
  44         mov.l   r7, @-r15
  45
  46         mov.l   7834f, r0
  47         jsr     @r0
  48          nop
  49
  50         mov.l   @r15+, r7
  51         mov.l   @r15+, r6
  52         mov.l   @r15+, r5
  53         mov.l   @r15+, r4
  54         mov.l   @r15+, r3
  55         mov.l   @r15+, r2
  56         mov.l   @r15+, r1
  57         mov.l   @r15+, r0
  58         mov.l   7834f, r0
  59
  60         bra     7835f
  61          nop
  62         .balign 4
  63 7834:   .long   trace_hardirqs_on
  64 7835:
  65         .endm
  66         .macro  TRACE_IRQS_OFF
  67
  68         mov.l   r0, @-r15
  69         mov.l   r1, @-r15
  70         mov.l   r2, @-r15
  71         mov.l   r3, @-r15
  72         mov.l   r4, @-r15
  73         mov.l   r5, @-r15
  74         mov.l   r6, @-r15
  75         mov.l   r7, @-r15
  76
  77         mov.l   7834f, r0
  78         jsr     @r0
  79          nop
  80
  81         mov.l   @r15+, r7
  82         mov.l   @r15+, r6
  83         mov.l   @r15+, r5
  84         mov.l   @r15+, r4
  85         mov.l   @r15+, r3
  86         mov.l   @r15+, r2
  87         mov.l   @r15+, r1
  88         mov.l   @r15+, r0
  89         mov.l   7834f, r0
  90
  91         bra     7835f
  92          nop
  93         .balign 4
  94 7834:   .long   trace_hardirqs_off
  95 7835:
  96         .endm
  97
  98 #else
  99         .macro  TRACE_IRQS_ON
 100         .endm
 101
 102         .macro  TRACE_IRQS_OFF
 103         .endm
 104 #endif
 105
 106 #if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4)
 107 # define PREF(x)        pref    @x
 108 #else
 109 # define PREF(x)        nop
 110 #endif
 111
 112         /*
 113          * Macro for use within assembly. Because the DWARF unwinder
 114          * needs to use the frame register to unwind the stack, we
 115          * need to setup r14 with the value of the stack pointer as
 116          * the return address is usually on the stack somewhere.
 117          */
 118         .macro  setup_frame_reg
 119 #ifdef CONFIG_DWARF_UNWINDER
 120         mov     r15, r14
 121 #endif
 122         .endm