arch/sh/kernel/cpu/irq/ipr.c

   1 /*
   2  * Interrupt handling for IPR-based IRQ.
   3  *
   4  * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi
   5  * Copyright (C) 2000  Kazumoto Kojima
   6  * Copyright (C) 2003  Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
   7  * Copyright (C) 2006  Paul Mundt
   8  *
   9  * Supported system:
  10  *      On-chip supporting modules (TMU, RTC, etc.).
  11  *      On-chip supporting modules for SH7709/SH7709A/SH7729/SH7300.
  12  *      Hitachi SolutionEngine external I/O:
  13  *              MS7709SE01, MS7709ASE01, and MS7750SE01
  14  *
  15  * This file is subject to the terms and conditions of the GNU General Public
  16  * License.  See the file "COPYING" in the main directory of this archive
  17  * for more details.
  18  */
  19 #include <linux/init.h>
  20 #include <linux/irq.h>
  21 #include <linux/module.h>
  22 #include <linux/io.h>
  23 #include <linux/interrupt.h>
  24
  25 static void disable_ipr_irq(unsigned int irq)
  26 {
  27         struct ipr_data *p = get_irq_chip_data(irq);
  28         int shift = p->shift*4;
  29         /* Set the priority in IPR to 0 */
  30         ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << shift)), p->addr);
  31 }
  32
  33 static void enable_ipr_irq(unsigned int irq)
  34 {
  35         struct ipr_data *p = get_irq_chip_data(irq);
  36         int shift = p->shift*4;
  37         /* Set priority in IPR back to original value */
  38         ctrl_outw(ctrl_inw(p->addr) | (p->priority << shift), p->addr);
  39 }
  40
  41 static struct irq_chip ipr_irq_chip = {
  42         .name           = "IPR",
  43         .mask           = disable_ipr_irq,
  44         .unmask         = enable_ipr_irq,
  45         .mask_ack       = disable_ipr_irq,
  46 };
  47
  48 void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs)
  49 {
  50         int i;
  51
  52         for (i = 0; i < nr_irqs; i++) {
  53                 unsigned int irq = table[i].irq;
  54                 disable_irq_nosync(irq);
  55                 set_irq_chip_and_handler_name(irq, &ipr_irq_chip,
  56                                       handle_level_irq, "level");
  57                 set_irq_chip_data(irq, &table[i]);
  58                 enable_ipr_irq(irq);
  59         }
  60 }
  61 EXPORT_SYMBOL(make_ipr_irq);
  62
  63 /*
  64  * XXX: Move this garbage in to the drivers, and kill off the ridiculous CPU
  65  * subtype checks.
  66  */
  67 static struct ipr_data sys_ipr_map[] = {
  68 #ifndef CONFIG_CPU_SUBTYPE_SH7780
  69         { TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY },
  70         { TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY },
  71 #ifdef RTC_IRQ
  72         { RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY },
  73 #endif
  74 #ifdef SCI_ERI_IRQ
  75         { SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
  76         { SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
  77         { SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
  78 #endif
  79 #ifdef SCIF1_ERI_IRQ
  80         { SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
  81         { SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
  82         { SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
  83         { SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
  84 #endif
  85 #ifdef SCIF2_ERI_IRQ
  86         { SCIF2_ERI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY },
  87         { SCIF2_RXI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY },
  88         { SCIF2_BRI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY },
  89         { SCIF2_TXI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY },
  90 #endif
  91 #ifdef SCIF3_ERI_IRQ
  92         { SCIF3_ERI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY },
  93         { SCIF3_RXI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY },
  94         { SCIF3_BRI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY },
  95         { SCIF3_TXI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY },
  96 #endif
  97 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
  98         { SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY },
  99         { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
 100         { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
 101         { VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
 102 #endif
 103 #ifdef SCIF_ERI_IRQ
 104         { SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
 105         { SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
 106         { SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
 107         { SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
 108 #endif
 109 #ifdef IRDA_ERI_IRQ
 110         { IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
 111         { IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
 112         { IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
 113         { IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
 114 #endif
 115 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
 116     defined(CONFIG_CPU_SUBTYPE_SH7706) || \
 117     defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
 118         /*
 119          * Initialize the Interrupt Controller (INTC)
 120          * registers to their power on values
 121          */
 122
 123         /*
 124          * Enable external irq (INTC IRQ mode).
 125          * You should set corresponding bits of PFC to "00"
 126          * to enable these interrupts.
 127          */
 128         { IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY },
 129         { IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY },
 130         { IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY },
 131         { IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY },
 132         { IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY },
 133         { IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY },
 134 #endif
 135 #endif
 136 };
 137
 138 void __init init_IRQ(void)
 139 {
 140         make_ipr_irq(sys_ipr_map, ARRAY_SIZE(sys_ipr_map));
 141
 142 #ifdef CONFIG_CPU_HAS_PINT_IRQ
 143         init_IRQ_pint();
 144 #endif
 145
 146 #ifdef CONFIG_CPU_HAS_INTC2_IRQ
 147         init_IRQ_intc2();
 148 #endif
 149         /* Perform the machine specific initialisation */
 150         if (sh_mv.mv_init_irq != NULL)
 151                 sh_mv.mv_init_irq();
 152
 153         irq_ctx_init(smp_processor_id());
 154 }
 155
 156 #if !defined(CONFIG_CPU_HAS_PINT_IRQ)
 157 int ipr_irq_demux(int irq)
 158 {
 159         return irq;
 160 }
 161 #endif