4 * Copyright (C) 2008 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
14 #include <linux/serial_sci.h>
15 #include <linux/uio_driver.h>
16 #include <asm/clock.h>
17 #include <asm/mmzone.h>
19 static struct uio_info vpu_platform_data
= {
25 static struct resource vpu_resources
[] = {
30 .flags
= IORESOURCE_MEM
,
33 /* place holder for contiguous memory */
37 static struct platform_device vpu_device
= {
38 .name
= "uio_pdrv_genirq",
41 .platform_data
= &vpu_platform_data
,
43 .resource
= vpu_resources
,
44 .num_resources
= ARRAY_SIZE(vpu_resources
),
47 static struct uio_info veu0_platform_data
= {
53 static struct resource veu0_resources
[] = {
58 .flags
= IORESOURCE_MEM
,
61 /* place holder for contiguous memory */
65 static struct platform_device veu0_device
= {
66 .name
= "uio_pdrv_genirq",
69 .platform_data
= &veu0_platform_data
,
71 .resource
= veu0_resources
,
72 .num_resources
= ARRAY_SIZE(veu0_resources
),
75 static struct uio_info veu1_platform_data
= {
81 static struct resource veu1_resources
[] = {
86 .flags
= IORESOURCE_MEM
,
89 /* place holder for contiguous memory */
93 static struct platform_device veu1_device
= {
94 .name
= "uio_pdrv_genirq",
97 .platform_data
= &veu1_platform_data
,
99 .resource
= veu1_resources
,
100 .num_resources
= ARRAY_SIZE(veu1_resources
),
103 static struct plat_sci_port sci_platform_data
[] = {
105 .mapbase
= 0xffe00000,
106 .flags
= UPF_BOOT_AUTOCONF
,
108 .irqs
= { 80, 80, 80, 80 },
110 .mapbase
= 0xffe10000,
111 .flags
= UPF_BOOT_AUTOCONF
,
113 .irqs
= { 81, 81, 81, 81 },
115 .mapbase
= 0xffe20000,
116 .flags
= UPF_BOOT_AUTOCONF
,
118 .irqs
= { 82, 82, 82, 82 },
120 .mapbase
= 0xa4e30000,
121 .flags
= UPF_BOOT_AUTOCONF
,
123 .irqs
= { 56, 56, 56, 56 },
125 .mapbase
= 0xa4e40000,
126 .flags
= UPF_BOOT_AUTOCONF
,
128 .irqs
= { 88, 88, 88, 88 },
130 .mapbase
= 0xa4e50000,
131 .flags
= UPF_BOOT_AUTOCONF
,
133 .irqs
= { 109, 109, 109, 109 },
139 static struct platform_device sci_device
= {
143 .platform_data
= sci_platform_data
,
147 static struct resource rtc_resources
[] = {
150 .end
= 0xa465fec0 + 0x58 - 1,
151 .flags
= IORESOURCE_IO
,
156 .flags
= IORESOURCE_IRQ
,
161 .flags
= IORESOURCE_IRQ
,
166 .flags
= IORESOURCE_IRQ
,
170 static struct platform_device rtc_device
= {
173 .num_resources
= ARRAY_SIZE(rtc_resources
),
174 .resource
= rtc_resources
,
177 static struct resource sh7723_usb_host_resources
[] = {
179 .name
= "r8a66597_hcd",
182 .flags
= IORESOURCE_MEM
,
187 .flags
= IORESOURCE_IRQ
,
191 static struct platform_device sh7723_usb_host_device
= {
192 .name
= "r8a66597_hcd",
195 .dma_mask
= NULL
, /* not use dma */
196 .coherent_dma_mask
= 0xffffffff,
198 .num_resources
= ARRAY_SIZE(sh7723_usb_host_resources
),
199 .resource
= sh7723_usb_host_resources
,
202 static struct resource iic_resources
[] = {
207 .flags
= IORESOURCE_MEM
,
212 .flags
= IORESOURCE_IRQ
,
216 static struct platform_device iic_device
= {
217 .name
= "i2c-sh_mobile",
218 .num_resources
= ARRAY_SIZE(iic_resources
),
219 .resource
= iic_resources
,
222 static struct platform_device
*sh7723_devices
[] __initdata
= {
226 &sh7723_usb_host_device
,
232 static int __init
sh7723_devices_setup(void)
234 clk_always_enable("mstp031"); /* TLB */
235 clk_always_enable("mstp030"); /* IC */
236 clk_always_enable("mstp029"); /* OC */
237 clk_always_enable("mstp024"); /* FPU */
238 clk_always_enable("mstp022"); /* INTC */
239 clk_always_enable("mstp020"); /* SuperHyway */
240 clk_always_enable("mstp000"); /* MERAM */
241 clk_always_enable("mstp109"); /* I2C */
242 clk_always_enable("mstp108"); /* RTC */
243 clk_always_enable("mstp211"); /* USB */
244 clk_always_enable("mstp206"); /* VEU2H1 */
245 clk_always_enable("mstp202"); /* VEU2H0 */
246 clk_always_enable("mstp201"); /* VPU */
248 platform_resource_setup_memory(&vpu_device
, "vpu", 2 << 20);
249 platform_resource_setup_memory(&veu0_device
, "veu0", 2 << 20);
250 platform_resource_setup_memory(&veu1_device
, "veu1", 2 << 20);
252 return platform_add_devices(sh7723_devices
,
253 ARRAY_SIZE(sh7723_devices
));
255 __initcall(sh7723_devices_setup
);
260 /* interrupt sources */
261 IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
,
263 DMAC1A_DEI0
,DMAC1A_DEI1
,DMAC1A_DEI2
,DMAC1A_DEI3
,
264 _2DG_TRI
,_2DG_INI
,_2DG_CEI
,
265 DMAC0A_DEI0
,DMAC0A_DEI1
,DMAC0A_DEI2
,DMAC0A_DEI3
,
266 VIO_CEUI
,VIO_BEUI
,VIO_VEU2HI
,VIO_VOUI
,
272 RTC_ATI
,RTC_PRI
,RTC_CUI
,
273 DMAC1B_DEI4
,DMAC1B_DEI5
,DMAC1B_DADERR
,
274 DMAC0B_DEI4
,DMAC0B_DEI5
,DMAC0B_DADERR
,
276 SCIF_SCIF0
,SCIF_SCIF1
,SCIF_SCIF2
,
277 MSIOF_MSIOFI0
,MSIOF_MSIOFI1
,
279 FLCTL_FLSTEI
,FLCTL_FLTENDI
,FLCTL_FLTREQ0I
,FLCTL_FLTREQ1I
,
280 I2C_ALI
,I2C_TACKI
,I2C_WAITI
,I2C_DTEI
,
281 SDHI0_SDHII0
,SDHI0_SDHII1
,SDHI0_SDHII2
,
286 TMU0_TUNI0
, TMU0_TUNI1
, TMU0_TUNI2
,
289 SDHI1_SDHII0
,SDHI1_SDHII1
,SDHI1_SDHII2
,
292 TMU1_TUNI0
,TMU1_TUNI1
,TMU1_TUNI2
,
294 /* interrupt groups */
295 DMAC1A
, DMAC0A
, VIO
, DMAC0B
, FLCTL
, I2C
, _2DG
,
296 SDHI1
, RTC
, DMAC1B
, SDHI0
,
299 static struct intc_vect vectors
[] __initdata
= {
300 INTC_VECT(IRQ0
, 0x600), INTC_VECT(IRQ1
, 0x620),
301 INTC_VECT(IRQ2
, 0x640), INTC_VECT(IRQ3
, 0x660),
302 INTC_VECT(IRQ4
, 0x680), INTC_VECT(IRQ5
, 0x6a0),
303 INTC_VECT(IRQ6
, 0x6c0), INTC_VECT(IRQ7
, 0x6e0),
305 INTC_VECT(DMAC1A_DEI0
,0x700),
306 INTC_VECT(DMAC1A_DEI1
,0x720),
307 INTC_VECT(DMAC1A_DEI2
,0x740),
308 INTC_VECT(DMAC1A_DEI3
,0x760),
310 INTC_VECT(_2DG_TRI
, 0x780),
311 INTC_VECT(_2DG_INI
, 0x7A0),
312 INTC_VECT(_2DG_CEI
, 0x7C0),
314 INTC_VECT(DMAC0A_DEI0
,0x800),
315 INTC_VECT(DMAC0A_DEI1
,0x820),
316 INTC_VECT(DMAC0A_DEI2
,0x840),
317 INTC_VECT(DMAC0A_DEI3
,0x860),
319 INTC_VECT(VIO_CEUI
,0x880),
320 INTC_VECT(VIO_BEUI
,0x8A0),
321 INTC_VECT(VIO_VEU2HI
,0x8C0),
322 INTC_VECT(VIO_VOUI
,0x8E0),
324 INTC_VECT(SCIFA_SCIFA0
,0x900),
325 INTC_VECT(VPU_VPUI
,0x980),
326 INTC_VECT(TPU_TPUI
,0x9A0),
327 INTC_VECT(ADC_ADI
,0x9E0),
328 INTC_VECT(USB_USI0
,0xA20),
330 INTC_VECT(RTC_ATI
,0xA80),
331 INTC_VECT(RTC_PRI
,0xAA0),
332 INTC_VECT(RTC_CUI
,0xAC0),
334 INTC_VECT(DMAC1B_DEI4
,0xB00),
335 INTC_VECT(DMAC1B_DEI5
,0xB20),
336 INTC_VECT(DMAC1B_DADERR
,0xB40),
338 INTC_VECT(DMAC0B_DEI4
,0xB80),
339 INTC_VECT(DMAC0B_DEI5
,0xBA0),
340 INTC_VECT(DMAC0B_DADERR
,0xBC0),
342 INTC_VECT(KEYSC_KEYI
,0xBE0),
343 INTC_VECT(SCIF_SCIF0
,0xC00),
344 INTC_VECT(SCIF_SCIF1
,0xC20),
345 INTC_VECT(SCIF_SCIF2
,0xC40),
346 INTC_VECT(MSIOF_MSIOFI0
,0xC80),
347 INTC_VECT(MSIOF_MSIOFI1
,0xCA0),
348 INTC_VECT(SCIFA_SCIFA1
,0xD00),
350 INTC_VECT(FLCTL_FLSTEI
,0xD80),
351 INTC_VECT(FLCTL_FLTENDI
,0xDA0),
352 INTC_VECT(FLCTL_FLTREQ0I
,0xDC0),
353 INTC_VECT(FLCTL_FLTREQ1I
,0xDE0),
355 INTC_VECT(I2C_ALI
,0xE00),
356 INTC_VECT(I2C_TACKI
,0xE20),
357 INTC_VECT(I2C_WAITI
,0xE40),
358 INTC_VECT(I2C_DTEI
,0xE60),
360 INTC_VECT(SDHI0_SDHII0
,0xE80),
361 INTC_VECT(SDHI0_SDHII1
,0xEA0),
362 INTC_VECT(SDHI0_SDHII2
,0xEC0),
364 INTC_VECT(CMT_CMTI
,0xF00),
365 INTC_VECT(TSIF_TSIFI
,0xF20),
366 INTC_VECT(SIU_SIUI
,0xF80),
367 INTC_VECT(SCIFA_SCIFA2
,0xFA0),
369 INTC_VECT(TMU0_TUNI0
,0x400),
370 INTC_VECT(TMU0_TUNI1
,0x420),
371 INTC_VECT(TMU0_TUNI2
,0x440),
373 INTC_VECT(IRDA_IRDAI
,0x480),
374 INTC_VECT(ATAPI_ATAPII
,0x4A0),
376 INTC_VECT(SDHI1_SDHII0
,0x4E0),
377 INTC_VECT(SDHI1_SDHII1
,0x500),
378 INTC_VECT(SDHI1_SDHII2
,0x520),
380 INTC_VECT(VEU2H1_VEU2HI
,0x560),
381 INTC_VECT(LCDC_LCDCI
,0x580),
383 INTC_VECT(TMU1_TUNI0
,0x920),
384 INTC_VECT(TMU1_TUNI1
,0x940),
385 INTC_VECT(TMU1_TUNI2
,0x960),
389 static struct intc_group groups
[] __initdata
= {
390 INTC_GROUP(DMAC1A
,DMAC1A_DEI0
,DMAC1A_DEI1
,DMAC1A_DEI2
,DMAC1A_DEI3
),
391 INTC_GROUP(DMAC0A
,DMAC0A_DEI0
,DMAC0A_DEI1
,DMAC0A_DEI2
,DMAC0A_DEI3
),
392 INTC_GROUP(VIO
, VIO_CEUI
,VIO_BEUI
,VIO_VEU2HI
,VIO_VOUI
),
393 INTC_GROUP(DMAC0B
, DMAC0B_DEI4
,DMAC0B_DEI5
,DMAC0B_DADERR
),
394 INTC_GROUP(FLCTL
,FLCTL_FLSTEI
,FLCTL_FLTENDI
,FLCTL_FLTREQ0I
,FLCTL_FLTREQ1I
),
395 INTC_GROUP(I2C
,I2C_ALI
,I2C_TACKI
,I2C_WAITI
,I2C_DTEI
),
396 INTC_GROUP(_2DG
, _2DG_TRI
,_2DG_INI
,_2DG_CEI
),
397 INTC_GROUP(SDHI1
, SDHI1_SDHII0
,SDHI1_SDHII1
,SDHI1_SDHII2
),
398 INTC_GROUP(RTC
, RTC_ATI
,RTC_PRI
,RTC_CUI
),
399 INTC_GROUP(DMAC1B
, DMAC1B_DEI4
,DMAC1B_DEI5
,DMAC1B_DADERR
),
400 INTC_GROUP(SDHI0
,SDHI0_SDHII0
,SDHI0_SDHII1
,SDHI0_SDHII2
),
403 static struct intc_mask_reg mask_registers
[] __initdata
= {
404 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
405 { 0, TMU1_TUNI2
,TMU1_TUNI1
,TMU1_TUNI0
,0,SDHI1_SDHII2
,SDHI1_SDHII1
,SDHI1_SDHII0
} },
406 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
407 { VIO_VOUI
, VIO_VEU2HI
,VIO_BEUI
,VIO_CEUI
,DMAC0A_DEI3
,DMAC0A_DEI2
,DMAC0A_DEI1
,DMAC0A_DEI0
} },
408 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
409 { 0, 0, 0, VPU_VPUI
,0,0,0,SCIFA_SCIFA0
} },
410 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
411 { DMAC1A_DEI3
,DMAC1A_DEI2
,DMAC1A_DEI1
,DMAC1A_DEI0
,0,0,0,IRDA_IRDAI
} },
412 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
413 { 0,TMU0_TUNI2
,TMU0_TUNI1
,TMU0_TUNI0
,VEU2H1_VEU2HI
,0,0,LCDC_LCDCI
} },
414 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
415 { KEYSC_KEYI
,DMAC0B_DADERR
,DMAC0B_DEI5
,DMAC0B_DEI4
,0,SCIF_SCIF2
,SCIF_SCIF1
,SCIF_SCIF0
} },
416 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
417 { 0,0,0,SCIFA_SCIFA1
,ADC_ADI
,0,MSIOF_MSIOFI1
,MSIOF_MSIOFI0
} },
418 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
419 { I2C_DTEI
, I2C_WAITI
, I2C_TACKI
, I2C_ALI
,
420 FLCTL_FLTREQ1I
, FLCTL_FLTREQ0I
, FLCTL_FLTENDI
, FLCTL_FLSTEI
} },
421 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
422 { 0,SDHI0_SDHII2
,SDHI0_SDHII1
,SDHI0_SDHII0
,0,0,SCIFA_SCIFA2
,SIU_SIUI
} },
423 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
424 { 0, 0, 0, CMT_CMTI
, 0, 0, USB_USI0
,0 } },
425 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
426 { 0, DMAC1B_DADERR
,DMAC1B_DEI5
,DMAC1B_DEI4
,0,RTC_ATI
,RTC_PRI
,RTC_CUI
} },
427 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
428 { 0,_2DG_CEI
,_2DG_INI
,_2DG_TRI
,0,TPU_TPUI
,0,TSIF_TSIFI
} },
429 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
430 { 0,0,0,0,0,0,0,ATAPI_ATAPII
} },
431 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
432 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
435 static struct intc_prio_reg prio_registers
[] __initdata
= {
436 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0
, TMU0_TUNI1
, TMU0_TUNI2
, IRDA_IRDAI
} },
437 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI
, LCDC_LCDCI
, DMAC1A
, 0} },
438 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0
, TMU1_TUNI1
, TMU1_TUNI2
, 0} },
439 { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
440 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A
, VIO
, SCIFA_SCIFA0
, VPU_VPUI
} },
441 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI
, DMAC0B
, USB_USI0
, CMT_CMTI
} },
442 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0
, SCIF_SCIF1
, SCIF_SCIF2
,0 } },
443 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0
,MSIOF_MSIOFI1
, FLCTL
, I2C
} },
444 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1
,0,TSIF_TSIFI
,_2DG
} },
445 { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI
,0,SIU_SIUI
,SDHI1
} },
446 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC
,DMAC1B
,0,SDHI0
} },
447 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2
,0,TPU_TPUI
,ATAPI_ATAPII
} },
448 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
449 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
452 static struct intc_sense_reg sense_registers
[] __initdata
= {
453 { 0xa414001c, 16, 2, /* ICR1 */
454 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
457 static struct intc_mask_reg ack_registers
[] __initdata
= {
458 { 0xa4140024, 0, 8, /* INTREQ00 */
459 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
462 static DECLARE_INTC_DESC_ACK(intc_desc
, "sh7723", vectors
, groups
,
463 mask_registers
, prio_registers
, sense_registers
,
466 void __init
plat_irq_setup(void)
468 register_intc_controller(&intc_desc
);