arch/sparc/kernel/head_32.S

   1 /*
   2  * head.S: The initial boot code for the Sparc port of Linux.
   3  *
   4  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   5  * Copyright (C) 1995,1999 Pete Zaitcev   (zaitcev@yahoo.com)
   6  * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
   7  * Copyright (C) 1997 Jakub Jelinek   (jj@sunsite.mff.cuni.cz)
   8  * Copyright (C) 1997 Michael A. Griffith (grif@acm.org)
   9  *
  10  * CompactPCI platform by Eric Brower, 1999.
  11  */
  12
  13 #include <linux/version.h>
  14 #include <linux/init.h>
  15
  16 #include <asm/head.h>
  17 #include <asm/asi.h>
  18 #include <asm/contregs.h>
  19 #include <asm/ptrace.h>
  20 #include <asm/psr.h>
  21 #include <asm/page.h>
  22 #include <asm/kdebug.h>
  23 #include <asm/winmacro.h>
  24 #include <asm/thread_info.h>    /* TI_UWINMASK */
  25 #include <asm/errno.h>
  26 #include <asm/pgtsrmmu.h>       /* SRMMU_PGDIR_SHIFT */
  27
  28         .data
  29 /* The following are used with the prom_vector node-ops to figure out
  30  * the cpu-type
  31  */
  32         .align 4
  33         .globl cputypval
  34 cputypval:
  35         .asciz "sun4m"
  36         .ascii "     "
  37
  38 /* Tested on SS-5, SS-10 */
  39         .align 4
  40 cputypvar:
  41         .asciz "compatible"
  42
  43         .align 4
  44
  45 notsup:
  46         .asciz  "Sparc-Linux sun4/sun4c or MMU-less not supported\n\n"
  47         .align 4
  48
  49 sun4e_notsup:
  50         .asciz  "Sparc-Linux sun4e support does not exist\n\n"
  51         .align 4
  52
  53 /* The trap-table - located in the __HEAD section */
  54 #include "ttable_32.S"
  55
  56         .align PAGE_SIZE
  57
  58 /* This was the only reasonable way I could think of to properly align
  59  * these page-table data structures.
  60  */
  61         .globl empty_zero_page
  62 empty_zero_page:        .skip PAGE_SIZE
  63
  64         .global root_flags
  65         .global ram_flags
  66         .global root_dev
  67         .global sparc_ramdisk_image
  68         .global sparc_ramdisk_size
  69
  70 /* This stuff has to be in sync with SILO and other potential boot loaders
  71  * Fields should be kept upward compatible and whenever any change is made,
  72  * HdrS version should be incremented.
  73  */
  74         .ascii  "HdrS"
  75         .word   LINUX_VERSION_CODE
  76         .half   0x0203          /* HdrS version */
  77 root_flags:
  78         .half   1
  79 root_dev:
  80         .half   0
  81 ram_flags:
  82         .half   0
  83 sparc_ramdisk_image:
  84         .word   0
  85 sparc_ramdisk_size:
  86         .word   0
  87         .word   reboot_command
  88         .word   0, 0, 0
  89         .word   _end
  90
  91 /* Cool, here we go. Pick up the romvec pointer in %o0 and stash it in
  92  * %g7 and at prom_vector_p. And also quickly check whether we are on
  93  * a v0, v2, or v3 prom.
  94  */
  95 gokernel:
  96                 /* Ok, it's nice to know, as early as possible, if we
  97                  * are already mapped where we expect to be in virtual
  98                  * memory.  The Solaris /boot elf format bootloader
  99                  * will peek into our elf header and load us where
 100                  * we want to be, otherwise we have to re-map.
 101                  *
 102                  * Some boot loaders don't place the jmp'rs address
 103                  * in %o7, so we do a pc-relative call to a local
 104                  * label, then see what %o7 has.
 105                  */
 106
 107                 mov     %o7, %g4                ! Save %o7
 108
 109                 /* Jump to it, and pray... */
 110 current_pc:
 111                 call    1f
 112                  nop
 113
 114 1:
 115                 mov     %o7, %g3
 116
 117                 tst     %o0
 118                 be      no_sun4u_here
 119                  mov    %g4, %o7                /* Previous %o7. */
 120
 121                 mov     %o0, %l0                ! stash away romvec
 122                 mov     %o0, %g7                ! put it here too
 123                 mov     %o1, %l1                ! stash away debug_vec too
 124
 125                 /* Ok, let's check out our run time program counter. */
 126                 set     current_pc, %g5
 127                 cmp     %g3, %g5
 128                 be      already_mapped
 129                  nop
 130
 131                 /* %l6 will hold the offset we have to subtract
 132                  * from absolute symbols in order to access areas
 133                  * in our own image.  If already mapped this is
 134                  * just plain zero, else it is KERNBASE.
 135                  */
 136                 set     KERNBASE, %l6
 137                 b       copy_prom_lvl14
 138                  nop
 139
 140 already_mapped:
 141                 mov     0, %l6
 142
 143                 /* Copy over the Prom's level 14 clock handler. */
 144 copy_prom_lvl14:
 145 #if 1
 146                 /* DJHR
 147                  * preserve our linked/calculated instructions
 148                  */
 149                 set     lvl14_save, %g1
 150                 set     t_irq14, %g3
 151                 sub     %g1, %l6, %g1           ! translate to physical
 152                 sub     %g3, %l6, %g3           ! translate to physical
 153                 ldd     [%g3], %g4
 154                 std     %g4, [%g1]
 155                 ldd     [%g3+8], %g4
 156                 std     %g4, [%g1+8]
 157 #endif
 158                 rd      %tbr, %g1
 159                 andn    %g1, 0xfff, %g1         ! proms trap table base
 160                 or      %g0, (0x1e<<4), %g2     ! offset to lvl14 intr
 161                 or      %g1, %g2, %g2
 162                 set     t_irq14, %g3
 163                 sub     %g3, %l6, %g3
 164                 ldd     [%g2], %g4
 165                 std     %g4, [%g3]
 166                 ldd     [%g2 + 0x8], %g4
 167                 std     %g4, [%g3 + 0x8]        ! Copy proms handler
 168
 169 /* DON'T TOUCH %l0 thru %l5 in these remapping routines,
 170  * we need their values afterwards!
 171  */
 172
 173                 /* Now check whether we are already mapped, if we
 174                  * are we can skip all this garbage coming up.
 175                  */
 176 copy_prom_done:
 177                 cmp     %l6, 0
 178                 be      go_to_highmem           ! this will be a nop then
 179                  nop
 180
 181                 /* Validate that we are in fact running on an
 182                  * SRMMU based cpu.
 183                  */
 184                 set     0x4000, %g6
 185                 cmp     %g7, %g6
 186                 bne     not_a_sun4
 187                  nop
 188
 189 halt_notsup:
 190                 ld      [%g7 + 0x68], %o1
 191                 set     notsup, %o0
 192                 sub     %o0, %l6, %o0
 193                 call    %o1
 194                  nop
 195                 ba      halt_me
 196                  nop
 197
 198 not_a_sun4:
 199                 /* It looks like this is a machine we support.
 200                  * Now find out what MMU we are dealing with
 201                  * LEON - identified by the psr.impl field
 202                  * Viking - identified by the psr.impl field
 203                  * In all other cases a sun4m srmmu.
 204                  * We check that the MMU is enabled in all cases.
 205                  */
 206
 207                 /* Check if this is a LEON CPU */
 208                 rd      %psr, %g3
 209                 srl     %g3, PSR_IMPL_SHIFT, %g3
 210                 and     %g3, PSR_IMPL_SHIFTED_MASK, %g3
 211                 cmp     %g3, PSR_IMPL_LEON
 212                 be      leon_remap              /* It is a LEON - jump */
 213                  nop
 214
 215                 /* Sanity-check, is MMU enabled */
 216                 lda     [%g0] ASI_M_MMUREGS, %g1
 217                 andcc   %g1, 1, %g0
 218                 be      halt_notsup
 219                  nop
 220
 221                 /* Check for a viking (TI) module. */
 222                 cmp     %g3, PSR_IMPL_TI
 223                 bne     srmmu_not_viking
 224                  nop
 225
 226                 /* Figure out what kind of viking we are on.
 227                  * We need to know if we have to play with the
 228                  * AC bit and disable traps or not.
 229                  */
 230
 231                 /* I've only seen MicroSparc's on SparcClassics with this
 232                  * bit set.
 233                  */
 234                 set     0x800, %g2
 235                 lda     [%g0] ASI_M_MMUREGS, %g3        ! peek in the control reg
 236                 and     %g2, %g3, %g3
 237                 subcc   %g3, 0x0, %g0
 238                 bnz     srmmu_not_viking                        ! is in mbus mode
 239                  nop
 240
 241                 rd      %psr, %g3                       ! DO NOT TOUCH %g3
 242                 andn    %g3, PSR_ET, %g2
 243                 wr      %g2, 0x0, %psr
 244                 WRITE_PAUSE
 245
 246                 /* Get context table pointer, then convert to
 247                  * a physical address, which is 36 bits.
 248                  */
 249                 set     AC_M_CTPR, %g4
 250                 lda     [%g4] ASI_M_MMUREGS, %g4
 251                 sll     %g4, 0x4, %g4                   ! We use this below
 252                                                         ! DO NOT TOUCH %g4
 253
 254                 /* Set the AC bit in the Viking's MMU control reg. */
 255                 lda     [%g0] ASI_M_MMUREGS, %g5        ! DO NOT TOUCH %g5
 256                 set     0x8000, %g6                     ! AC bit mask
 257                 or      %g5, %g6, %g6                   ! Or it in...
 258                 sta     %g6, [%g0] ASI_M_MMUREGS        ! Close your eyes...
 259
 260                 /* Grrr, why does it seem like every other load/store
 261                  * on the sun4m is in some ASI space...
 262                  * Fine with me, let's get the pointer to the level 1
 263                  * page table directory and fetch its entry.
 264                  */
 265                 lda     [%g4] ASI_M_BYPASS, %o1         ! This is a level 1 ptr
 266                 srl     %o1, 0x4, %o1                   ! Clear low 4 bits
 267                 sll     %o1, 0x8, %o1                   ! Make physical
 268
 269                 /* Ok, pull in the PTD. */
 270                 lda     [%o1] ASI_M_BYPASS, %o2         ! This is the 0x0 16MB pgd
 271
 272                 /* Calculate to KERNBASE entry. */
 273                 add     %o1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %o3
 274
 275                 /* Poke the entry into the calculated address. */
 276                 sta     %o2, [%o3] ASI_M_BYPASS
 277
 278                 /* I don't get it Sun, if you engineered all these
 279                  * boot loaders and the PROM (thank you for the debugging
 280                  * features btw) why did you not have them load kernel
 281                  * images up in high address space, since this is necessary
 282                  * for ABI compliance anyways?  Does this low-mapping provide
 283                  * enhanced interoperability?
 284                  *
 285                  * "The PROM is the computer."
 286                  */
 287
 288                 /* Ok, restore the MMU control register we saved in %g5 */
 289                 sta     %g5, [%g0] ASI_M_MMUREGS        ! POW... ouch
 290
 291                 /* Turn traps back on.  We saved it in %g3 earlier. */
 292                 wr      %g3, 0x0, %psr                  ! tick tock, tick tock
 293
 294                 /* Now we burn precious CPU cycles due to bad engineering. */
 295                 WRITE_PAUSE
 296
 297                 /* Wow, all that just to move a 32-bit value from one
 298                  * place to another...  Jump to high memory.
 299                  */
 300                 b       go_to_highmem
 301                  nop
 302
 303 srmmu_not_viking:
 304                 /* This works on viking's in Mbus mode and all
 305                  * other MBUS modules.  It is virtually the same as
 306                  * the above madness sans turning traps off and flipping
 307                  * the AC bit.
 308                  */
 309                 set     AC_M_CTPR, %g1
 310                 lda     [%g1] ASI_M_MMUREGS, %g1        ! get ctx table ptr
 311                 sll     %g1, 0x4, %g1                   ! make physical addr
 312                 lda     [%g1] ASI_M_BYPASS, %g1         ! ptr to level 1 pg_table
 313                 srl     %g1, 0x4, %g1
 314                 sll     %g1, 0x8, %g1                   ! make phys addr for l1 tbl
 315
 316                 lda     [%g1] ASI_M_BYPASS, %g2         ! get level1 entry for 0x0
 317                 add     %g1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %g3
 318                 sta     %g2, [%g3] ASI_M_BYPASS         ! place at KERNBASE entry
 319                 b       go_to_highmem
 320                  nop                                    ! wheee....
 321
 322
 323 leon_remap:
 324                 /* Sanity-check, is MMU enabled */
 325                 lda     [%g0] ASI_LEON_MMUREGS, %g1
 326                 andcc   %g1, 1, %g0
 327                 be      halt_notsup
 328                  nop
 329
 330                 /* Same code as in the srmmu_not_viking case,
 331                  * with the LEON ASI for mmuregs
 332                  */
 333                 set     AC_M_CTPR, %g1
 334                 lda     [%g1] ASI_LEON_MMUREGS, %g1     ! get ctx table ptr
 335                 sll     %g1, 0x4, %g1                   ! make physical addr
 336                 lda     [%g1] ASI_M_BYPASS, %g1         ! ptr to level 1 pg_table
 337                 srl     %g1, 0x4, %g1
 338                 sll     %g1, 0x8, %g1                   ! make phys addr for l1 tbl
 339
 340                 lda     [%g1] ASI_M_BYPASS, %g2         ! get level1 entry for 0x0
 341                 add     %g1, KERNBASE >> (SRMMU_PGDIR_SHIFT - 2), %g3
 342                 sta     %g2, [%g3] ASI_M_BYPASS         ! place at KERNBASE entry
 343                 b       go_to_highmem
 344                  nop                                    ! wheee....
 345
 346 /* Now do a non-relative jump so that PC is in high-memory */
 347 go_to_highmem:
 348                 set     execute_in_high_mem, %g1
 349                 jmpl    %g1, %g0
 350                  nop
 351
 352 /* The code above should be at beginning and we have to take care about
 353  * short jumps, as branching to .init.text section from .text is usually
 354  * impossible */
 355                 __INIT
 356 /* Acquire boot time privileged register values, this will help debugging.
 357  * I figure out and store nwindows and nwindowsm1 later on.
 358  */
 359 execute_in_high_mem:
 360                 mov     %l0, %o0                ! put back romvec
 361                 mov     %l1, %o1                ! and debug_vec
 362
 363                 sethi   %hi(prom_vector_p), %g1
 364                 st      %o0, [%g1 + %lo(prom_vector_p)]
 365
 366                 sethi   %hi(linux_dbvec), %g1
 367                 st      %o1, [%g1 + %lo(linux_dbvec)]
 368
 369                 /* Get the machine type via the romvec
 370                  * getprops node operation
 371                  */
 372                 add     %g7, 0x1c, %l1
 373                 ld      [%l1], %l0
 374                 ld      [%l0], %l0
 375                 call    %l0
 376                  or     %g0, %g0, %o0           ! next_node(0) = first_node
 377                 or      %o0, %g0, %g6
 378
 379                 sethi   %hi(cputypvar), %o1     ! First node has cpu-arch
 380                 or      %o1, %lo(cputypvar), %o1
 381                 sethi   %hi(cputypval), %o2     ! information, the string
 382                 or      %o2, %lo(cputypval), %o2
 383                 ld      [%l1], %l0              ! 'compatible' tells
 384                 ld      [%l0 + 0xc], %l0        ! that we want 'sun4x' where
 385                 call    %l0                     ! x is one of 'm', 'd' or 'e'.
 386                  nop                            ! %o2 holds pointer
 387                                                 ! to a buf where above string
 388                                                 ! will get stored by the prom.
 389
 390
 391                 /* Check value of "compatible" property.
 392                  * "value" => "model"
 393                  * leon => sparc_leon
 394                  * sun4m => sun4m
 395                  * sun4s => sun4m
 396                  * sun4d => sun4d
 397                  * sun4e => "no_sun4e_here"
 398                  * '*'   => "no_sun4u_here"
 399                  * Check single letters only
 400                  */
 401
 402                 set     cputypval, %o2
 403                 /* If cputypval[0] == 'l' (lower case letter L) this is leon */
 404                 ldub    [%o2], %l1
 405                 cmp     %l1, 'l'
 406                 be      leon_init
 407                  nop
 408
 409                 /* Check cputypval[4] to find the sun model */
 410                 ldub    [%o2 + 0x4], %l1
 411
 412                 cmp     %l1, 'm'
 413                 be      sun4m_init
 414                  cmp    %l1, 's'
 415                 be      sun4m_init
 416                  cmp    %l1, 'd'
 417                 be      sun4d_init
 418                  cmp    %l1, 'e'
 419                 be      no_sun4e_here           ! Could be a sun4e.
 420                  nop
 421                 b       no_sun4u_here           ! AIEEE, a V9 sun4u... Get our BIG BROTHER kernel :))
 422                  nop
 423
 424 leon_init:
 425                 /* LEON CPU - set boot_cpu_id */
 426                 sethi   %hi(boot_cpu_id), %g2   ! boot-cpu index
 427
 428 #ifdef CONFIG_SMP
 429                 ldub    [%g2 + %lo(boot_cpu_id)], %g1
 430                 cmp     %g1, 0xff               ! unset means first CPU
 431                 bne     leon_smp_cpu_startup    ! continue only with master
 432                  nop
 433 #endif
 434                 /* Get CPU-ID from most significant 4-bit of ASR17 */
 435                 rd     %asr17, %g1
 436                 srl    %g1, 28, %g1
 437
 438                 /* Update boot_cpu_id only on boot cpu */
 439                 stub    %g1, [%g2 + %lo(boot_cpu_id)]
 440
 441                 ba continue_boot
 442                  nop
 443
 444 /* CPUID in bootbus can be found at PA 0xff0140000 */
 445 #define SUN4D_BOOTBUS_CPUID     0xf0140000
 446
 447 sun4d_init:
 448         /* Need to patch call to handler_irq */
 449         set     patch_handler_irq, %g4
 450         set     sun4d_handler_irq, %g5
 451         sethi   %hi(0x40000000), %g3            ! call
 452         sub     %g5, %g4, %g5
 453         srl     %g5, 2, %g5
 454         or      %g5, %g3, %g5
 455         st      %g5, [%g4]
 456
 457 #ifdef CONFIG_SMP
 458         /* Get our CPU id out of bootbus */
 459         set     SUN4D_BOOTBUS_CPUID, %g3
 460         lduba   [%g3] ASI_M_CTL, %g3
 461         and     %g3, 0xf8, %g3
 462         srl     %g3, 3, %g4
 463         sta     %g4, [%g0] ASI_M_VIKING_TMP1
 464         sethi   %hi(boot_cpu_id), %g5
 465         stb     %g4, [%g5 + %lo(boot_cpu_id)]
 466 #endif
 467
 468         /* Fall through to sun4m_init */
 469
 470 sun4m_init:
 471 /* Ok, the PROM could have done funny things and apple cider could still
 472  * be sitting in the fault status/address registers.  Read them all to
 473  * clear them so we don't get magic faults later on.
 474  */
 475 /* This sucks, apparently this makes Vikings call prom panic, will fix later */
 476 2:
 477                 rd      %psr, %o1
 478                 srl     %o1, PSR_IMPL_SHIFT, %o1        ! Get a type of the CPU
 479
 480                 subcc   %o1, PSR_IMPL_TI, %g0           ! TI: Viking or MicroSPARC
 481                 be      continue_boot
 482                  nop
 483
 484                 set     AC_M_SFSR, %o0
 485                 lda     [%o0] ASI_M_MMUREGS, %g0
 486                 set     AC_M_SFAR, %o0
 487                 lda     [%o0] ASI_M_MMUREGS, %g0
 488
 489                 /* Fujitsu MicroSPARC-II has no asynchronous flavors of FARs */
 490                 subcc   %o1, 0, %g0
 491                 be      continue_boot
 492                  nop
 493
 494                 set     AC_M_AFSR, %o0
 495                 lda     [%o0] ASI_M_MMUREGS, %g0
 496                 set     AC_M_AFAR, %o0
 497                 lda     [%o0] ASI_M_MMUREGS, %g0
 498                  nop
 499
 500
 501 continue_boot:
 502
 503 /* Aieee, now set PC and nPC, enable traps, give ourselves a stack and it's
 504  * show-time!
 505  */
 506                 /* Turn on Supervisor, EnableFloating, and all the PIL bits.
 507                  * Also puts us in register window zero with traps off.
 508                  */
 509                 set     (PSR_PS | PSR_S | PSR_PIL | PSR_EF), %g2
 510                 wr      %g2, 0x0, %psr
 511                 WRITE_PAUSE
 512
 513                 /* I want a kernel stack NOW! */
 514                 set     init_thread_union, %g1
 515                 set     (THREAD_SIZE - STACKFRAME_SZ), %g2
 516                 add     %g1, %g2, %sp
 517                 mov     0, %fp                  /* And for good luck */
 518
 519                 /* Zero out our BSS section. */
 520                 set     __bss_start , %o0       ! First address of BSS
 521                 set     _end , %o1              ! Last address of BSS
 522                 add     %o0, 0x1, %o0
 523 1:
 524                 stb     %g0, [%o0]
 525                 subcc   %o0, %o1, %g0
 526                 bl      1b
 527                  add    %o0, 0x1, %o0
 528
 529                 /* If boot_cpu_id has not been setup by machine specific
 530                  * init-code above we default it to zero.
 531                  */
 532                 sethi   %hi(boot_cpu_id), %g2
 533                 ldub    [%g2 + %lo(boot_cpu_id)], %g3
 534                 cmp     %g3, 0xff
 535                 bne     1f
 536                  nop
 537                 mov     %g0, %g3
 538                 stub    %g3, [%g2 + %lo(boot_cpu_id)]
 539
 540 1:              sll     %g3, 2, %g3
 541
 542                 /* Initialize the uwinmask value for init task just in case.
 543                  * But first make current_set[boot_cpu_id] point to something useful.
 544                  */
 545                 set     init_thread_union, %g6
 546                 set     current_set, %g2
 547 #ifdef CONFIG_SMP
 548                 st      %g6, [%g2]
 549                 add     %g2, %g3, %g2
 550 #endif
 551                 st      %g6, [%g2]
 552
 553                 st      %g0, [%g6 + TI_UWINMASK]
 554
 555 /* Compute NWINDOWS and stash it away. Now uses %wim trick explained
 556  * in the V8 manual. Ok, this method seems to work, Sparc is cool...
 557  * No, it doesn't work, have to play the save/readCWP/restore trick.
 558  */
 559
 560                 wr      %g0, 0x0, %wim                  ! so we do not get a trap
 561                 WRITE_PAUSE
 562
 563                 save
 564
 565                 rd      %psr, %g3
 566
 567                 restore
 568
 569                 and     %g3, 0x1f, %g3
 570                 add     %g3, 0x1, %g3
 571
 572                 mov     2, %g1
 573                 wr      %g1, 0x0, %wim                  ! make window 1 invalid
 574                 WRITE_PAUSE
 575
 576                 cmp     %g3, 0x7
 577                 bne     2f
 578                  nop
 579
 580                 /* Adjust our window handling routines to
 581                  * do things correctly on 7 window Sparcs.
 582                  */
 583
 584 #define         PATCH_INSN(src, dest) \
 585                 set     src, %g5; \
 586                 set     dest, %g2; \
 587                 ld      [%g5], %g4; \
 588                 st      %g4, [%g2];
 589
 590                 /* Patch for window spills... */
 591                 PATCH_INSN(spnwin_patch1_7win, spnwin_patch1)
 592                 PATCH_INSN(spnwin_patch2_7win, spnwin_patch2)
 593                 PATCH_INSN(spnwin_patch3_7win, spnwin_patch3)
 594
 595                 /* Patch for window fills... */
 596                 PATCH_INSN(fnwin_patch1_7win, fnwin_patch1)
 597                 PATCH_INSN(fnwin_patch2_7win, fnwin_patch2)
 598
 599                 /* Patch for trap entry setup... */
 600                 PATCH_INSN(tsetup_7win_patch1, tsetup_patch1)
 601                 PATCH_INSN(tsetup_7win_patch2, tsetup_patch2)
 602                 PATCH_INSN(tsetup_7win_patch3, tsetup_patch3)
 603                 PATCH_INSN(tsetup_7win_patch4, tsetup_patch4)
 604                 PATCH_INSN(tsetup_7win_patch5, tsetup_patch5)
 605                 PATCH_INSN(tsetup_7win_patch6, tsetup_patch6)
 606
 607                 /* Patch for returning from traps... */
 608                 PATCH_INSN(rtrap_7win_patch1, rtrap_patch1)
 609                 PATCH_INSN(rtrap_7win_patch2, rtrap_patch2)
 610                 PATCH_INSN(rtrap_7win_patch3, rtrap_patch3)
 611                 PATCH_INSN(rtrap_7win_patch4, rtrap_patch4)
 612                 PATCH_INSN(rtrap_7win_patch5, rtrap_patch5)
 613
 614                 /* Patch for killing user windows from the register file. */
 615                 PATCH_INSN(kuw_patch1_7win, kuw_patch1)
 616
 617                 /* Now patch the kernel window flush sequences.
 618                  * This saves 2 traps on every switch and fork.
 619                  */
 620                 set     0x01000000, %g4
 621                 set     flush_patch_one, %g5
 622                 st      %g4, [%g5 + 0x18]
 623                 st      %g4, [%g5 + 0x1c]
 624                 set     flush_patch_two, %g5
 625                 st      %g4, [%g5 + 0x18]
 626                 st      %g4, [%g5 + 0x1c]
 627                 set     flush_patch_three, %g5
 628                 st      %g4, [%g5 + 0x18]
 629                 st      %g4, [%g5 + 0x1c]
 630                 set     flush_patch_four, %g5
 631                 st      %g4, [%g5 + 0x18]
 632                 st      %g4, [%g5 + 0x1c]
 633                 set     flush_patch_exception, %g5
 634                 st      %g4, [%g5 + 0x18]
 635                 st      %g4, [%g5 + 0x1c]
 636                 set     flush_patch_switch, %g5
 637                 st      %g4, [%g5 + 0x18]
 638                 st      %g4, [%g5 + 0x1c]
 639
 640 2:
 641                 sethi   %hi(nwindows), %g4
 642                 st      %g3, [%g4 + %lo(nwindows)]      ! store final value
 643                 sub     %g3, 0x1, %g3
 644                 sethi   %hi(nwindowsm1), %g4
 645                 st      %g3, [%g4 + %lo(nwindowsm1)]
 646
 647                 /* Here we go, start using Linux's trap table... */
 648                 set     trapbase, %g3
 649                 wr      %g3, 0x0, %tbr
 650                 WRITE_PAUSE
 651
 652                 /* Finally, turn on traps so that we can call c-code. */
 653                 rd      %psr, %g3
 654                 wr      %g3, 0x0, %psr
 655                 WRITE_PAUSE
 656
 657                 wr      %g3, PSR_ET, %psr
 658                 WRITE_PAUSE
 659
 660                 /* Call sparc32_start_kernel(struct linux_romvec *rp) */
 661                 sethi   %hi(prom_vector_p), %g5
 662                 ld      [%g5 + %lo(prom_vector_p)], %o0
 663                 call    sparc32_start_kernel
 664                  nop
 665
 666                 /* We should not get here. */
 667                 call    halt_me
 668                  nop
 669
 670 no_sun4e_here:
 671                 ld      [%g7 + 0x68], %o1
 672                 set     sun4e_notsup, %o0
 673                 call    %o1
 674                  nop
 675                 b       halt_me
 676                  nop
 677
 678                 __INITDATA
 679
 680 sun4u_1:
 681                 .asciz "finddevice"
 682                 .align  4
 683 sun4u_2:
 684                 .asciz "/chosen"
 685                 .align  4
 686 sun4u_3:
 687                 .asciz "getprop"
 688                 .align  4
 689 sun4u_4:
 690                 .asciz "stdout"
 691                 .align  4
 692 sun4u_5:
 693                 .asciz "write"
 694                 .align  4
 695 sun4u_6:
 696                 .asciz  "\n\rOn sun4u you have to use sparc64 kernel\n\rand not a sparc32 version\n\r\n\r"
 697 sun4u_6e:
 698                 .align  4
 699 sun4u_7:
 700                 .asciz "exit"
 701                 .align  8
 702 sun4u_a1:
 703                 .word   0, sun4u_1, 0, 1, 0, 1, 0, sun4u_2, 0
 704 sun4u_r1:
 705                 .word   0
 706 sun4u_a2:
 707                 .word   0, sun4u_3, 0, 4, 0, 1, 0
 708 sun4u_i2:
 709                 .word   0, 0, sun4u_4, 0, sun4u_1, 0, 8, 0
 710 sun4u_r2:
 711                 .word   0
 712 sun4u_a3:
 713                 .word   0, sun4u_5, 0, 3, 0, 1, 0
 714 sun4u_i3:
 715                 .word   0, 0, sun4u_6, 0, sun4u_6e - sun4u_6 - 1, 0
 716 sun4u_r3:
 717                 .word   0
 718 sun4u_a4:
 719                 .word   0, sun4u_7, 0, 0, 0, 0
 720 sun4u_r4:
 721
 722                 __INIT
 723 no_sun4u_here:
 724                 set     sun4u_a1, %o0
 725                 set     current_pc, %l2
 726                 cmp     %l2, %g3
 727                 be      1f
 728                  mov    %o4, %l0
 729                 sub     %g3, %l2, %l6
 730                 add     %o0, %l6, %o0
 731                 mov     %o0, %l4
 732                 mov     sun4u_r4 - sun4u_a1, %l3
 733                 ld      [%l4], %l5
 734 2:
 735                 add     %l4, 4, %l4
 736                 cmp     %l5, %l2
 737                 add     %l5, %l6, %l5
 738                 bgeu,a  3f
 739                  st     %l5, [%l4 - 4]
 740 3:
 741                 subcc   %l3, 4, %l3
 742                 bne     2b
 743                  ld     [%l4], %l5
 744 1:
 745                 call    %l0
 746                  mov    %o0, %l1
 747
 748                 ld      [%l1 + (sun4u_r1 - sun4u_a1)], %o1
 749                 add     %l1, (sun4u_a2 - sun4u_a1), %o0
 750                 call    %l0
 751                  st     %o1, [%o0 + (sun4u_i2 - sun4u_a2)]
 752
 753                 ld      [%l1 + (sun4u_1 - sun4u_a1)], %o1
 754                 add     %l1, (sun4u_a3 - sun4u_a1), %o0
 755                 call    %l0
 756                 st      %o1, [%o0 + (sun4u_i3 - sun4u_a3)]
 757
 758                 call    %l0
 759                  add    %l1, (sun4u_a4 - sun4u_a1), %o0
 760
 761                 /* Not reached */
 762 halt_me:
 763                 ld      [%g7 + 0x74], %o0
 764                 call    %o0                     ! Get us out of here...
 765                  nop                            ! Apparently Solaris is better.
 766
 767 /* Ok, now we continue in the .data/.text sections */
 768
 769         .data
 770         .align 4
 771
 772 /*
 773  * Fill up the prom vector, note in particular the kind first element,
 774  * no joke. I don't need all of them in here as the entire prom vector
 775  * gets initialized in c-code so all routines can use it.
 776  */
 777
 778 prom_vector_p:
 779                 .word 0
 780
 781 /* We calculate the following at boot time, window fills/spills and trap entry
 782  * code uses these to keep track of the register windows.
 783  */
 784
 785         .align 4
 786         .globl  nwindows
 787         .globl  nwindowsm1
 788 nwindows:
 789         .word   8
 790 nwindowsm1:
 791         .word   7
 792
 793 /* Boot time debugger vector value.  We need this later on. */
 794
 795         .align 4
 796         .globl  linux_dbvec
 797 linux_dbvec:
 798         .word   0
 799         .word   0
 800
 801         .align 8
 802
 803         .globl  lvl14_save
 804 lvl14_save:
 805         .word   0
 806         .word   0
 807         .word   0
 808         .word   0
 809         .word   t_irq14
 810
 811         .section        ".fixup",#alloc,#execinstr
 812         .globl  __ret_efault
 813 __ret_efault:
 814         ret
 815          restore %g0, -EFAULT, %o0