arch/sparc64/kernel/head.S

   1 /* head.S: Initial boot code for the Sparc64 port of Linux.
   2  *
   3  * Copyright (C) 1996, 1997, 2007 David S. Miller (davem@davemloft.net)
   4  * Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
   5  * Copyright (C) 1997, 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  * Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
   7  */
   8
   9 #include <linux/version.h>
  10 #include <linux/errno.h>
  11 #include <linux/threads.h>
  12 #include <linux/init.h>
  13 #include <asm/thread_info.h>
  14 #include <asm/asi.h>
  15 #include <asm/pstate.h>
  16 #include <asm/ptrace.h>
  17 #include <asm/spitfire.h>
  18 #include <asm/page.h>
  19 #include <asm/pgtable.h>
  20 #include <asm/errno.h>
  21 #include <asm/signal.h>
  22 #include <asm/processor.h>
  23 #include <asm/lsu.h>
  24 #include <asm/dcr.h>
  25 #include <asm/dcu.h>
  26 #include <asm/head.h>
  27 #include <asm/ttable.h>
  28 #include <asm/mmu.h>
  29 #include <asm/cpudata.h>
  30 #include <asm/pil.h>
  31 #include <asm/estate.h>
  32 #include <asm/sfafsr.h>
  33 #include <asm/unistd.h>
  34
  35 /* This section from from _start to sparc64_boot_end should fit into
  36  * 0x0000000000404000 to 0x0000000000408000.
  37  */
  38         .text
  39         .globl  start, _start, stext, _stext
  40 _start:
  41 start:
  42 _stext:
  43 stext:
  44 ! 0x0000000000404000
  45         b       sparc64_boot
  46          flushw                                 /* Flush register file.      */
  47
  48 /* This stuff has to be in sync with SILO and other potential boot loaders
  49  * Fields should be kept upward compatible and whenever any change is made,
  50  * HdrS version should be incremented.
  51  */
  52         .global root_flags, ram_flags, root_dev
  53         .global sparc_ramdisk_image, sparc_ramdisk_size
  54         .global sparc_ramdisk_image64
  55
  56         .ascii  "HdrS"
  57         .word   LINUX_VERSION_CODE
  58
  59         /* History:
  60          *
  61          * 0x0300 : Supports being located at other than 0x4000
  62          * 0x0202 : Supports kernel params string
  63          * 0x0201 : Supports reboot_command
  64          */
  65         .half   0x0301          /* HdrS version */
  66
  67 root_flags:
  68         .half   1
  69 root_dev:
  70         .half   0
  71 ram_flags:
  72         .half   0
  73 sparc_ramdisk_image:
  74         .word   0
  75 sparc_ramdisk_size:
  76         .word   0
  77         .xword  reboot_command
  78         .xword  bootstr_info
  79 sparc_ramdisk_image64:
  80         .xword  0
  81         .word   _end
  82
  83         /* PROM cif handler code address is in %o4.  */
  84 sparc64_boot:
  85         mov     %o4, %l7
  86
  87         /* We need to remap the kernel.  Use position independant
  88          * code to remap us to KERNBASE.
  89          *
  90          * SILO can invoke us with 32-bit address masking enabled,
  91          * so make sure that's clear.
  92          */
  93         rdpr    %pstate, %g1
  94         andn    %g1, PSTATE_AM, %g1
  95         wrpr    %g1, 0x0, %pstate
  96         ba,a,pt %xcc, 1f
  97
  98         .globl  prom_finddev_name, prom_chosen_path, prom_root_node
  99         .globl  prom_getprop_name, prom_mmu_name, prom_peer_name
 100         .globl  prom_callmethod_name, prom_translate_name, prom_root_compatible
 101         .globl  prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
 102         .globl  prom_boot_mapped_pc, prom_boot_mapping_mode
 103         .globl  prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
 104         .globl  prom_compatible_name, prom_cpu_path, prom_cpu_compatible
 105         .globl  is_sun4v, sun4v_chip_type, prom_set_trap_table_name
 106 prom_peer_name:
 107         .asciz  "peer"
 108 prom_compatible_name:
 109         .asciz  "compatible"
 110 prom_finddev_name:
 111         .asciz  "finddevice"
 112 prom_chosen_path:
 113         .asciz  "/chosen"
 114 prom_cpu_path:
 115         .asciz  "/cpu"
 116 prom_getprop_name:
 117         .asciz  "getprop"
 118 prom_mmu_name:
 119         .asciz  "mmu"
 120 prom_callmethod_name:
 121         .asciz  "call-method"
 122 prom_translate_name:
 123         .asciz  "translate"
 124 prom_map_name:
 125         .asciz  "map"
 126 prom_unmap_name:
 127         .asciz  "unmap"
 128 prom_set_trap_table_name:
 129         .asciz  "SUNW,set-trap-table"
 130 prom_sun4v_name:
 131         .asciz  "sun4v"
 132 prom_niagara_prefix:
 133         .asciz  "SUNW,UltraSPARC-T"
 134         .align  4
 135 prom_root_compatible:
 136         .skip   64
 137 prom_cpu_compatible:
 138         .skip   64
 139 prom_root_node:
 140         .word   0
 141 prom_mmu_ihandle_cache:
 142         .word   0
 143 prom_boot_mapped_pc:
 144         .word   0
 145 prom_boot_mapping_mode:
 146         .word   0
 147         .align  8
 148 prom_boot_mapping_phys_high:
 149         .xword  0
 150 prom_boot_mapping_phys_low:
 151         .xword  0
 152 is_sun4v:
 153         .word   0
 154 sun4v_chip_type:
 155         .word   SUN4V_CHIP_INVALID
 156 1:
 157         rd      %pc, %l0
 158
 159         mov     (1b - prom_peer_name), %l1
 160         sub     %l0, %l1, %l1
 161         mov     0, %l2
 162
 163         /* prom_root_node = prom_peer(0) */
 164         stx     %l1, [%sp + 2047 + 128 + 0x00]  ! service, "peer"
 165         mov     1, %l3
 166         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 1
 167         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 1
 168         stx     %l2, [%sp + 2047 + 128 + 0x18]  ! arg1, 0
 169         stx     %g0, [%sp + 2047 + 128 + 0x20]  ! ret1
 170         call    %l7
 171          add    %sp, (2047 + 128), %o0          ! argument array
 172
 173         ldx     [%sp + 2047 + 128 + 0x20], %l4  ! prom root node
 174         mov     (1b - prom_root_node), %l1
 175         sub     %l0, %l1, %l1
 176         stw     %l4, [%l1]
 177
 178         mov     (1b - prom_getprop_name), %l1
 179         mov     (1b - prom_compatible_name), %l2
 180         mov     (1b - prom_root_compatible), %l5
 181         sub     %l0, %l1, %l1
 182         sub     %l0, %l2, %l2
 183         sub     %l0, %l5, %l5
 184
 185         /* prom_getproperty(prom_root_node, "compatible",
 186          *                  &prom_root_compatible, 64)
 187          */
 188         stx     %l1, [%sp + 2047 + 128 + 0x00]  ! service, "getprop"
 189         mov     4, %l3
 190         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 4
 191         mov     1, %l3
 192         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 1
 193         stx     %l4, [%sp + 2047 + 128 + 0x18]  ! arg1, prom_root_node
 194         stx     %l2, [%sp + 2047 + 128 + 0x20]  ! arg2, "compatible"
 195         stx     %l5, [%sp + 2047 + 128 + 0x28]  ! arg3, &prom_root_compatible
 196         mov     64, %l3
 197         stx     %l3, [%sp + 2047 + 128 + 0x30]  ! arg4, size
 198         stx     %g0, [%sp + 2047 + 128 + 0x38]  ! ret1
 199         call    %l7
 200          add    %sp, (2047 + 128), %o0          ! argument array
 201
 202         mov     (1b - prom_finddev_name), %l1
 203         mov     (1b - prom_chosen_path), %l2
 204         mov     (1b - prom_boot_mapped_pc), %l3
 205         sub     %l0, %l1, %l1
 206         sub     %l0, %l2, %l2
 207         sub     %l0, %l3, %l3
 208         stw     %l0, [%l3]
 209         sub     %sp, (192 + 128), %sp
 210
 211         /* chosen_node = prom_finddevice("/chosen") */
 212         stx     %l1, [%sp + 2047 + 128 + 0x00]  ! service, "finddevice"
 213         mov     1, %l3
 214         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 1
 215         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 1
 216         stx     %l2, [%sp + 2047 + 128 + 0x18]  ! arg1, "/chosen"
 217         stx     %g0, [%sp + 2047 + 128 + 0x20]  ! ret1
 218         call    %l7
 219          add    %sp, (2047 + 128), %o0          ! argument array
 220
 221         ldx     [%sp + 2047 + 128 + 0x20], %l4  ! chosen device node
 222
 223         mov     (1b - prom_getprop_name), %l1
 224         mov     (1b - prom_mmu_name), %l2
 225         mov     (1b - prom_mmu_ihandle_cache), %l5
 226         sub     %l0, %l1, %l1
 227         sub     %l0, %l2, %l2
 228         sub     %l0, %l5, %l5
 229
 230         /* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
 231         stx     %l1, [%sp + 2047 + 128 + 0x00]  ! service, "getprop"
 232         mov     4, %l3
 233         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 4
 234         mov     1, %l3
 235         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 1
 236         stx     %l4, [%sp + 2047 + 128 + 0x18]  ! arg1, chosen_node
 237         stx     %l2, [%sp + 2047 + 128 + 0x20]  ! arg2, "mmu"
 238         stx     %l5, [%sp + 2047 + 128 + 0x28]  ! arg3, &prom_mmu_ihandle_cache
 239         mov     4, %l3
 240         stx     %l3, [%sp + 2047 + 128 + 0x30]  ! arg4, sizeof(arg3)
 241         stx     %g0, [%sp + 2047 + 128 + 0x38]  ! ret1
 242         call    %l7
 243          add    %sp, (2047 + 128), %o0          ! argument array
 244
 245         mov     (1b - prom_callmethod_name), %l1
 246         mov     (1b - prom_translate_name), %l2
 247         sub     %l0, %l1, %l1
 248         sub     %l0, %l2, %l2
 249         lduw    [%l5], %l5                      ! prom_mmu_ihandle_cache
 250
 251         stx     %l1, [%sp + 2047 + 128 + 0x00]  ! service, "call-method"
 252         mov     3, %l3
 253         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 3
 254         mov     5, %l3
 255         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 5
 256         stx     %l2, [%sp + 2047 + 128 + 0x18]  ! arg1: "translate"
 257         stx     %l5, [%sp + 2047 + 128 + 0x20]  ! arg2: prom_mmu_ihandle_cache
 258         /* PAGE align */
 259         srlx    %l0, 13, %l3
 260         sllx    %l3, 13, %l3
 261         stx     %l3, [%sp + 2047 + 128 + 0x28]  ! arg3: vaddr, our PC
 262         stx     %g0, [%sp + 2047 + 128 + 0x30]  ! res1
 263         stx     %g0, [%sp + 2047 + 128 + 0x38]  ! res2
 264         stx     %g0, [%sp + 2047 + 128 + 0x40]  ! res3
 265         stx     %g0, [%sp + 2047 + 128 + 0x48]  ! res4
 266         stx     %g0, [%sp + 2047 + 128 + 0x50]  ! res5
 267         call    %l7
 268          add    %sp, (2047 + 128), %o0          ! argument array
 269
 270         ldx     [%sp + 2047 + 128 + 0x40], %l1  ! translation mode
 271         mov     (1b - prom_boot_mapping_mode), %l4
 272         sub     %l0, %l4, %l4
 273         stw     %l1, [%l4]
 274         mov     (1b - prom_boot_mapping_phys_high), %l4
 275         sub     %l0, %l4, %l4
 276         ldx     [%sp + 2047 + 128 + 0x48], %l2  ! physaddr high
 277         stx     %l2, [%l4 + 0x0]
 278         ldx     [%sp + 2047 + 128 + 0x50], %l3  ! physaddr low
 279         /* 4MB align */
 280         srlx    %l3, 22, %l3
 281         sllx    %l3, 22, %l3
 282         stx     %l3, [%l4 + 0x8]
 283
 284         /* Leave service as-is, "call-method" */
 285         mov     7, %l3
 286         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 7
 287         mov     1, %l3
 288         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 1
 289         mov     (1b - prom_map_name), %l3
 290         sub     %l0, %l3, %l3
 291         stx     %l3, [%sp + 2047 + 128 + 0x18]  ! arg1: "map"
 292         /* Leave arg2 as-is, prom_mmu_ihandle_cache */
 293         mov     -1, %l3
 294         stx     %l3, [%sp + 2047 + 128 + 0x28]  ! arg3: mode (-1 default)
 295         /* 4MB align the kernel image size. */
 296         set     (_end - KERNBASE), %l3
 297         set     ((4 * 1024 * 1024) - 1), %l4
 298         add     %l3, %l4, %l3
 299         andn    %l3, %l4, %l3
 300         stx     %l3, [%sp + 2047 + 128 + 0x30]  ! arg4: roundup(ksize, 4MB)
 301         sethi   %hi(KERNBASE), %l3
 302         stx     %l3, [%sp + 2047 + 128 + 0x38]  ! arg5: vaddr (KERNBASE)
 303         stx     %g0, [%sp + 2047 + 128 + 0x40]  ! arg6: empty
 304         mov     (1b - prom_boot_mapping_phys_low), %l3
 305         sub     %l0, %l3, %l3
 306         ldx     [%l3], %l3
 307         stx     %l3, [%sp + 2047 + 128 + 0x48]  ! arg7: phys addr
 308         call    %l7
 309          add    %sp, (2047 + 128), %o0          ! argument array
 310
 311         add     %sp, (192 + 128), %sp
 312
 313         sethi   %hi(prom_root_compatible), %g1
 314         or      %g1, %lo(prom_root_compatible), %g1
 315         sethi   %hi(prom_sun4v_name), %g7
 316         or      %g7, %lo(prom_sun4v_name), %g7
 317         mov     5, %g3
 318 90:     ldub    [%g7], %g2
 319         ldub    [%g1], %g4
 320         cmp     %g2, %g4
 321         bne,pn  %icc, 80f
 322          add    %g7, 1, %g7
 323         subcc   %g3, 1, %g3
 324         bne,pt  %xcc, 90b
 325          add    %g1, 1, %g1
 326
 327         sethi   %hi(is_sun4v), %g1
 328         or      %g1, %lo(is_sun4v), %g1
 329         mov     1, %g7
 330         stw     %g7, [%g1]
 331
 332         /* cpu_node = prom_finddevice("/cpu") */
 333         mov     (1b - prom_finddev_name), %l1
 334         mov     (1b - prom_cpu_path), %l2
 335         sub     %l0, %l1, %l1
 336         sub     %l0, %l2, %l2
 337         sub     %sp, (192 + 128), %sp
 338
 339         stx     %l1, [%sp + 2047 + 128 + 0x00]  ! service, "finddevice"
 340         mov     1, %l3
 341         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 1
 342         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 1
 343         stx     %l2, [%sp + 2047 + 128 + 0x18]  ! arg1, "/cpu"
 344         stx     %g0, [%sp + 2047 + 128 + 0x20]  ! ret1
 345         call    %l7
 346          add    %sp, (2047 + 128), %o0          ! argument array
 347
 348         ldx     [%sp + 2047 + 128 + 0x20], %l4  ! cpu device node
 349
 350         mov     (1b - prom_getprop_name), %l1
 351         mov     (1b - prom_compatible_name), %l2
 352         mov     (1b - prom_cpu_compatible), %l5
 353         sub     %l0, %l1, %l1
 354         sub     %l0, %l2, %l2
 355         sub     %l0, %l5, %l5
 356
 357         /* prom_getproperty(cpu_node, "compatible",
 358          *                  &prom_cpu_compatible, 64)
 359          */
 360         stx     %l1, [%sp + 2047 + 128 + 0x00]  ! service, "getprop"
 361         mov     4, %l3
 362         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 4
 363         mov     1, %l3
 364         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 1
 365         stx     %l4, [%sp + 2047 + 128 + 0x18]  ! arg1, cpu_node
 366         stx     %l2, [%sp + 2047 + 128 + 0x20]  ! arg2, "compatible"
 367         stx     %l5, [%sp + 2047 + 128 + 0x28]  ! arg3, &prom_cpu_compatible
 368         mov     64, %l3
 369         stx     %l3, [%sp + 2047 + 128 + 0x30]  ! arg4, size
 370         stx     %g0, [%sp + 2047 + 128 + 0x38]  ! ret1
 371         call    %l7
 372          add    %sp, (2047 + 128), %o0          ! argument array
 373
 374         add     %sp, (192 + 128), %sp
 375
 376         sethi   %hi(prom_cpu_compatible), %g1
 377         or      %g1, %lo(prom_cpu_compatible), %g1
 378         sethi   %hi(prom_niagara_prefix), %g7
 379         or      %g7, %lo(prom_niagara_prefix), %g7
 380         mov     17, %g3
 381 90:     ldub    [%g7], %g2
 382         ldub    [%g1], %g4
 383         cmp     %g2, %g4
 384         bne,pn  %icc, 4f
 385          add    %g7, 1, %g7
 386         subcc   %g3, 1, %g3
 387         bne,pt  %xcc, 90b
 388          add    %g1, 1, %g1
 389
 390         sethi   %hi(prom_cpu_compatible), %g1
 391         or      %g1, %lo(prom_cpu_compatible), %g1
 392         ldub    [%g1 + 17], %g2
 393         cmp     %g2, '1'
 394         be,pt   %xcc, 5f
 395          mov    SUN4V_CHIP_NIAGARA1, %g4
 396         cmp     %g2, '2'
 397         be,pt   %xcc, 5f
 398          mov    SUN4V_CHIP_NIAGARA2, %g4
 399 4:
 400         mov     SUN4V_CHIP_UNKNOWN, %g4
 401 5:      sethi   %hi(sun4v_chip_type), %g2
 402         or      %g2, %lo(sun4v_chip_type), %g2
 403         stw     %g4, [%g2]
 404
 405 80:
 406         BRANCH_IF_SUN4V(g1, jump_to_sun4u_init)
 407         BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
 408         BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
 409         ba,pt   %xcc, spitfire_boot
 410          nop
 411
 412 cheetah_plus_boot:
 413         /* Preserve OBP chosen DCU and DCR register settings.  */
 414         ba,pt   %xcc, cheetah_generic_boot
 415          nop
 416
 417 cheetah_boot:
 418         mov     DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
 419         wr      %g1, %asr18
 420
 421         sethi   %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
 422         or      %g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
 423         sllx    %g7, 32, %g7
 424         or      %g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7
 425         stxa    %g7, [%g0] ASI_DCU_CONTROL_REG
 426         membar  #Sync
 427
 428 cheetah_generic_boot:
 429         mov     TSB_EXTENSION_P, %g3
 430         stxa    %g0, [%g3] ASI_DMMU
 431         stxa    %g0, [%g3] ASI_IMMU
 432         membar  #Sync
 433
 434         mov     TSB_EXTENSION_S, %g3
 435         stxa    %g0, [%g3] ASI_DMMU
 436         membar  #Sync
 437
 438         mov     TSB_EXTENSION_N, %g3
 439         stxa    %g0, [%g3] ASI_DMMU
 440         stxa    %g0, [%g3] ASI_IMMU
 441         membar  #Sync
 442
 443         ba,a,pt %xcc, jump_to_sun4u_init
 444
 445 spitfire_boot:
 446         /* Typically PROM has already enabled both MMU's and both on-chip
 447          * caches, but we do it here anyway just to be paranoid.
 448          */
 449         mov     (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1
 450         stxa    %g1, [%g0] ASI_LSU_CONTROL
 451         membar  #Sync
 452
 453 jump_to_sun4u_init:
 454         /*
 455          * Make sure we are in privileged mode, have address masking,
 456          * using the ordinary globals and have enabled floating
 457          * point.
 458          *
 459          * Again, typically PROM has left %pil at 13 or similar, and
 460          * (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate.
 461          */
 462         wrpr    %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
 463         wr      %g0, 0, %fprs
 464
 465         set     sun4u_init, %g2
 466         jmpl    %g2 + %g0, %g0
 467          nop
 468
 469         .section        .text.init.refok
 470 sun4u_init:
 471         BRANCH_IF_SUN4V(g1, sun4v_init)
 472
 473         /* Set ctx 0 */
 474         mov             PRIMARY_CONTEXT, %g7
 475         stxa            %g0, [%g7] ASI_DMMU
 476         membar          #Sync
 477
 478         mov             SECONDARY_CONTEXT, %g7
 479         stxa            %g0, [%g7] ASI_DMMU
 480         membar  #Sync
 481
 482         ba,pt           %xcc, sun4u_continue
 483          nop
 484
 485 sun4v_init:
 486         /* Set ctx 0 */
 487         mov             PRIMARY_CONTEXT, %g7
 488         stxa            %g0, [%g7] ASI_MMU
 489         membar          #Sync
 490
 491         mov             SECONDARY_CONTEXT, %g7
 492         stxa            %g0, [%g7] ASI_MMU
 493         membar          #Sync
 494         ba,pt           %xcc, niagara_tlb_fixup
 495          nop
 496
 497 sun4u_continue:
 498         BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup)
 499
 500         ba,pt   %xcc, spitfire_tlb_fixup
 501          nop
 502
 503 niagara_tlb_fixup:
 504         mov     3, %g2          /* Set TLB type to hypervisor. */
 505         sethi   %hi(tlb_type), %g1
 506         stw     %g2, [%g1 + %lo(tlb_type)]
 507
 508         /* Patch copy/clear ops.  */
 509         sethi   %hi(sun4v_chip_type), %g1
 510         lduw    [%g1 + %lo(sun4v_chip_type)], %g1
 511         cmp     %g1, SUN4V_CHIP_NIAGARA1
 512         be,pt   %xcc, niagara_patch
 513          cmp    %g1, SUN4V_CHIP_NIAGARA2
 514         be,pt   %xcc, niagara2_patch
 515          nop
 516
 517         call    generic_patch_copyops
 518          nop
 519         call    generic_patch_bzero
 520          nop
 521         call    generic_patch_pageops
 522          nop
 523
 524         ba,a,pt %xcc, 80f
 525 niagara2_patch:
 526         call    niagara2_patch_copyops
 527          nop
 528         call    niagara_patch_bzero
 529          nop
 530         call    niagara2_patch_pageops
 531          nop
 532
 533         ba,a,pt %xcc, 80f
 534
 535 niagara_patch:
 536         call    niagara_patch_copyops
 537          nop
 538         call    niagara_patch_bzero
 539          nop
 540         call    niagara_patch_pageops
 541          nop
 542
 543 80:
 544         /* Patch TLB/cache ops.  */
 545         call    hypervisor_patch_cachetlbops
 546          nop
 547
 548         ba,pt   %xcc, tlb_fixup_done
 549          nop
 550
 551 cheetah_tlb_fixup:
 552         mov     2, %g2          /* Set TLB type to cheetah+. */
 553         BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
 554
 555         mov     1, %g2          /* Set TLB type to cheetah. */
 556
 557 1:      sethi   %hi(tlb_type), %g1
 558         stw     %g2, [%g1 + %lo(tlb_type)]
 559
 560         /* Patch copy/page operations to cheetah optimized versions. */
 561         call    cheetah_patch_copyops
 562          nop
 563         call    cheetah_patch_copy_page
 564          nop
 565         call    cheetah_patch_cachetlbops
 566          nop
 567
 568         ba,pt   %xcc, tlb_fixup_done
 569          nop
 570
 571 spitfire_tlb_fixup:
 572         /* Set TLB type to spitfire. */
 573         mov     0, %g2
 574         sethi   %hi(tlb_type), %g1
 575         stw     %g2, [%g1 + %lo(tlb_type)]
 576
 577 tlb_fixup_done:
 578         sethi   %hi(init_thread_union), %g6
 579         or      %g6, %lo(init_thread_union), %g6
 580         ldx     [%g6 + TI_TASK], %g4
 581         mov     %sp, %l6
 582
 583         wr      %g0, ASI_P, %asi
 584         mov     1, %g1
 585         sllx    %g1, THREAD_SHIFT, %g1
 586         sub     %g1, (STACKFRAME_SZ + STACK_BIAS), %g1
 587         add     %g6, %g1, %sp
 588         mov     0, %fp
 589
 590         /* Set per-cpu pointer initially to zero, this makes
 591          * the boot-cpu use the in-kernel-image per-cpu areas
 592          * before setup_per_cpu_area() is invoked.
 593          */
 594         clr     %g5
 595
 596         wrpr    %g0, 0, %wstate
 597         wrpr    %g0, 0x0, %tl
 598
 599         /* Clear the bss */
 600         sethi   %hi(__bss_start), %o0
 601         or      %o0, %lo(__bss_start), %o0
 602         sethi   %hi(_end), %o1
 603         or      %o1, %lo(_end), %o1
 604         call    __bzero
 605          sub    %o1, %o0, %o1
 606
 607 #ifdef CONFIG_LOCKDEP
 608         /* We have this call this super early, as even prom_init can grab
 609          * spinlocks and thus call into the lockdep code.
 610          */
 611         call    lockdep_init
 612          nop
 613 #endif
 614
 615         mov     %l6, %o1                        ! OpenPROM stack
 616         call    prom_init
 617          mov    %l7, %o0                        ! OpenPROM cif handler
 618
 619         /* Initialize current_thread_info()->cpu as early as possible.
 620          * In order to do that accurately we have to patch up the get_cpuid()
 621          * assembler sequences.  And that, in turn, requires that we know
 622          * if we are on a Starfire box or not.  While we're here, patch up
 623          * the sun4v sequences as well.
 624          */
 625         call    check_if_starfire
 626          nop
 627         call    per_cpu_patch
 628          nop
 629         call    sun4v_patch
 630          nop
 631
 632 #ifdef CONFIG_SMP
 633         call    hard_smp_processor_id
 634          nop
 635         cmp     %o0, NR_CPUS
 636         blu,pt  %xcc, 1f
 637          nop
 638         call    boot_cpu_id_too_large
 639          nop
 640         /* Not reached... */
 641
 642 1:
 643         /* If we boot on a non-zero cpu, all of the per-cpu
 644          * variable references we make before setting up the
 645          * per-cpu areas will use a bogus offset.  Put a
 646          * compensating factor into __per_cpu_base to handle
 647          * this cleanly.
 648          *
 649          * What the per-cpu code calculates is:
 650          *
 651          *      __per_cpu_base + (cpu << __per_cpu_shift)
 652          *
 653          * These two variables are zero initially, so to
 654          * make it all cancel out to zero we need to put
 655          * "0 - (cpu << 0)" into __per_cpu_base so that the
 656          * above formula evaluates to zero.
 657          *
 658          * We cannot even perform a printk() until this stuff
 659          * is setup as that calls cpu_clock() which uses
 660          * per-cpu variables.
 661          */
 662         sub     %g0, %o0, %o1
 663         sethi   %hi(__per_cpu_base), %o2
 664         stx     %o1, [%o2 + %lo(__per_cpu_base)]
 665 #else
 666         mov     0, %o0
 667 #endif
 668         sth     %o0, [%g6 + TI_CPU]
 669
 670         call    prom_init_report
 671          nop
 672
 673         /* Off we go.... */
 674         call    start_kernel
 675          nop
 676         /* Not reached... */
 677
 678         .previous
 679
 680         /* This is meant to allow the sharing of this code between
 681          * boot processor invocation (via setup_tba() below) and
 682          * secondary processor startup (via trampoline.S).  The
 683          * former does use this code, the latter does not yet due
 684          * to some complexities.  That should be fixed up at some
 685          * point.
 686          *
 687          * There used to be enormous complexity wrt. transferring
 688          * over from the firwmare's trap table to the Linux kernel's.
 689          * For example, there was a chicken & egg problem wrt. building
 690          * the OBP page tables, yet needing to be on the Linux kernel
 691          * trap table (to translate PAGE_OFFSET addresses) in order to
 692          * do that.
 693          *
 694          * We now handle OBP tlb misses differently, via linear lookups
 695          * into the prom_trans[] array.  So that specific problem no
 696          * longer exists.  Yet, unfortunately there are still some issues
 697          * preventing trampoline.S from using this code... ho hum.
 698          */
 699         .globl  setup_trap_table
 700 setup_trap_table:
 701         save    %sp, -192, %sp
 702
 703         /* Force interrupts to be disabled. */
 704         rdpr    %pstate, %l0
 705         andn    %l0, PSTATE_IE, %o1
 706         wrpr    %o1, 0x0, %pstate
 707         rdpr    %pil, %l1
 708         wrpr    %g0, 15, %pil
 709
 710         /* Make the firmware call to jump over to the Linux trap table.  */
 711         sethi   %hi(is_sun4v), %o0
 712         lduw    [%o0 + %lo(is_sun4v)], %o0
 713         brz,pt  %o0, 1f
 714          nop
 715
 716         TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
 717         add     %g2, TRAP_PER_CPU_FAULT_INFO, %g2
 718         stxa    %g2, [%g0] ASI_SCRATCHPAD
 719
 720         /* Compute physical address:
 721          *
 722          * paddr = kern_base + (mmfsa_vaddr - KERNBASE)
 723          */
 724         sethi   %hi(KERNBASE), %g3
 725         sub     %g2, %g3, %g2
 726         sethi   %hi(kern_base), %g3
 727         ldx     [%g3 + %lo(kern_base)], %g3
 728         add     %g2, %g3, %o1
 729         sethi   %hi(sparc64_ttable_tl0), %o0
 730
 731         set     prom_set_trap_table_name, %g2
 732         stx     %g2, [%sp + 2047 + 128 + 0x00]
 733         mov     2, %g2
 734         stx     %g2, [%sp + 2047 + 128 + 0x08]
 735         mov     0, %g2
 736         stx     %g2, [%sp + 2047 + 128 + 0x10]
 737         stx     %o0, [%sp + 2047 + 128 + 0x18]
 738         stx     %o1, [%sp + 2047 + 128 + 0x20]
 739         sethi   %hi(p1275buf), %g2
 740         or      %g2, %lo(p1275buf), %g2
 741         ldx     [%g2 + 0x08], %o1
 742         call    %o1
 743          add    %sp, (2047 + 128), %o0
 744
 745         ba,pt   %xcc, 2f
 746          nop
 747
 748 1:      sethi   %hi(sparc64_ttable_tl0), %o0
 749         set     prom_set_trap_table_name, %g2
 750         stx     %g2, [%sp + 2047 + 128 + 0x00]
 751         mov     1, %g2
 752         stx     %g2, [%sp + 2047 + 128 + 0x08]
 753         mov     0, %g2
 754         stx     %g2, [%sp + 2047 + 128 + 0x10]
 755         stx     %o0, [%sp + 2047 + 128 + 0x18]
 756         sethi   %hi(p1275buf), %g2
 757         or      %g2, %lo(p1275buf), %g2
 758         ldx     [%g2 + 0x08], %o1
 759         call    %o1
 760          add    %sp, (2047 + 128), %o0
 761
 762         /* Start using proper page size encodings in ctx register.  */
 763 2:      sethi   %hi(sparc64_kern_pri_context), %g3
 764         ldx     [%g3 + %lo(sparc64_kern_pri_context)], %g2
 765
 766         mov             PRIMARY_CONTEXT, %g1
 767
 768 661:    stxa            %g2, [%g1] ASI_DMMU
 769         .section        .sun4v_1insn_patch, "ax"
 770         .word           661b
 771         stxa            %g2, [%g1] ASI_MMU
 772         .previous
 773
 774         membar  #Sync
 775
 776         BRANCH_IF_SUN4V(o2, 1f)
 777
 778         /* Kill PROM timer */
 779         sethi   %hi(0x80000000), %o2
 780         sllx    %o2, 32, %o2
 781         wr      %o2, 0, %tick_cmpr
 782
 783         BRANCH_IF_ANY_CHEETAH(o2, o3, 1f)
 784
 785         ba,pt   %xcc, 2f
 786          nop
 787
 788         /* Disable STICK_INT interrupts. */
 789 1:
 790         sethi   %hi(0x80000000), %o2
 791         sllx    %o2, 32, %o2
 792         wr      %o2, %asr25
 793
 794 2:
 795         wrpr    %g0, %g0, %wstate
 796
 797         call    init_irqwork_curcpu
 798          nop
 799
 800         /* Now we can restore interrupt state. */
 801         wrpr    %l0, 0, %pstate
 802         wrpr    %l1, 0x0, %pil
 803
 804         ret
 805          restore
 806
 807         .globl  setup_tba
 808 setup_tba:
 809         save    %sp, -192, %sp
 810
 811         /* The boot processor is the only cpu which invokes this
 812          * routine, the other cpus set things up via trampoline.S.
 813          * So save the OBP trap table address here.
 814          */
 815         rdpr    %tba, %g7
 816         sethi   %hi(prom_tba), %o1
 817         or      %o1, %lo(prom_tba), %o1
 818         stx     %g7, [%o1]
 819
 820         call    setup_trap_table
 821          nop
 822
 823         ret
 824          restore
 825 sparc64_boot_end:
 826
 827 #include "etrap.S"
 828 #include "rtrap.S"
 829 #include "winfixup.S"
 830 #include "fpu_traps.S"
 831 #include "ivec.S"
 832 #include "getsetcc.S"
 833 #include "utrap.S"
 834 #include "spiterrs.S"
 835 #include "cherrs.S"
 836 #include "misctrap.S"
 837 #include "syscalls.S"
 838 #include "helpers.S"
 839 #include "hvcalls.S"
 840 #include "sun4v_tlb_miss.S"
 841 #include "sun4v_ivec.S"
 842 #include "ktlb.S"
 843 #include "tsb.S"
 844
 845 /*
 846  * The following skip makes sure the trap table in ttable.S is aligned
 847  * on a 32K boundary as required by the v9 specs for TBA register.
 848  *
 849  * We align to a 32K boundary, then we have the 32K kernel TSB,
 850  * the 64K kernel 4MB TSB, and then the 32K aligned trap table.
 851  */
 852 1:
 853         .skip   0x4000 + _start - 1b
 854
 855 ! 0x0000000000408000
 856
 857         .globl  swapper_tsb
 858 swapper_tsb:
 859         .skip   (32 * 1024)
 860
 861         .globl  swapper_4m_tsb
 862 swapper_4m_tsb:
 863         .skip   (64 * 1024)
 864
 865 ! 0x0000000000420000
 866
 867         /* Some care needs to be exercised if you try to move the
 868          * location of the trap table relative to other things.  For
 869          * one thing there are br* instructions in some of the
 870          * trap table entires which branch back to code in ktlb.S
 871          * Those instructions can only handle a signed 16-bit
 872          * displacement.
 873          *
 874          * There is a binutils bug (bugzilla #4558) which causes
 875          * the relocation overflow checks for such instructions to
 876          * not be done correctly.  So bintuils will not notice the
 877          * error and will instead write junk into the relocation and
 878          * you'll have an unbootable kernel.
 879          */
 880 #include "ttable.S"
 881
 882 ! 0x0000000000428000
 883
 884 #include "systbls.S"
 885
 886         .data
 887         .align  8
 888         .globl  prom_tba, tlb_type
 889 prom_tba:       .xword  0
 890 tlb_type:       .word   0       /* Must NOT end up in BSS */
 891         .section        ".fixup",#alloc,#execinstr
 892
 893         .globl  __ret_efault, __retl_efault
 894 __ret_efault:
 895         ret
 896          restore %g0, -EFAULT, %o0
 897 __retl_efault:
 898         retl
 899          mov    -EFAULT, %o0