arch/sparc64/kernel/head.S

   1 /* head.S: Initial boot code for the Sparc64 port of Linux.
   2  *
   3  * Copyright (C) 1996, 1997, 2007 David S. Miller (davem@davemloft.net)
   4  * Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
   5  * Copyright (C) 1997, 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  * Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
   7  */
   8
   9 #include <linux/version.h>
  10 #include <linux/errno.h>
  11 #include <linux/threads.h>
  12 #include <linux/init.h>
  13 #include <asm/thread_info.h>
  14 #include <asm/asi.h>
  15 #include <asm/pstate.h>
  16 #include <asm/ptrace.h>
  17 #include <asm/spitfire.h>
  18 #include <asm/page.h>
  19 #include <asm/pgtable.h>
  20 #include <asm/errno.h>
  21 #include <asm/signal.h>
  22 #include <asm/processor.h>
  23 #include <asm/lsu.h>
  24 #include <asm/dcr.h>
  25 #include <asm/dcu.h>
  26 #include <asm/head.h>
  27 #include <asm/ttable.h>
  28 #include <asm/mmu.h>
  29 #include <asm/cpudata.h>
  30
  31 /* This section from from _start to sparc64_boot_end should fit into
  32  * 0x0000000000404000 to 0x0000000000408000.
  33  */
  34         .text
  35         .globl  start, _start, stext, _stext
  36 _start:
  37 start:
  38 _stext:
  39 stext:
  40 ! 0x0000000000404000
  41         b       sparc64_boot
  42          flushw                                 /* Flush register file.      */
  43
  44 /* This stuff has to be in sync with SILO and other potential boot loaders
  45  * Fields should be kept upward compatible and whenever any change is made,
  46  * HdrS version should be incremented.
  47  */
  48         .global root_flags, ram_flags, root_dev
  49         .global sparc_ramdisk_image, sparc_ramdisk_size
  50         .global sparc_ramdisk_image64
  51
  52         .ascii  "HdrS"
  53         .word   LINUX_VERSION_CODE
  54
  55         /* History:
  56          *
  57          * 0x0300 : Supports being located at other than 0x4000
  58          * 0x0202 : Supports kernel params string
  59          * 0x0201 : Supports reboot_command
  60          */
  61         .half   0x0301          /* HdrS version */
  62
  63 root_flags:
  64         .half   1
  65 root_dev:
  66         .half   0
  67 ram_flags:
  68         .half   0
  69 sparc_ramdisk_image:
  70         .word   0
  71 sparc_ramdisk_size:
  72         .word   0
  73         .xword  reboot_command
  74         .xword  bootstr_info
  75 sparc_ramdisk_image64:
  76         .xword  0
  77         .word   _end
  78
  79         /* PROM cif handler code address is in %o4.  */
  80 sparc64_boot:
  81         mov     %o4, %l7
  82
  83         /* We need to remap the kernel.  Use position independant
  84          * code to remap us to KERNBASE.
  85          *
  86          * SILO can invoke us with 32-bit address masking enabled,
  87          * so make sure that's clear.
  88          */
  89         rdpr    %pstate, %g1
  90         andn    %g1, PSTATE_AM, %g1
  91         wrpr    %g1, 0x0, %pstate
  92         ba,a,pt %xcc, 1f
  93
  94         .globl  prom_finddev_name, prom_chosen_path, prom_root_node
  95         .globl  prom_getprop_name, prom_mmu_name, prom_peer_name
  96         .globl  prom_callmethod_name, prom_translate_name, prom_root_compatible
  97         .globl  prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
  98         .globl  prom_boot_mapped_pc, prom_boot_mapping_mode
  99         .globl  prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
 100         .globl  prom_compatible_name, prom_cpu_path, prom_cpu_compatible
 101         .globl  is_sun4v, sun4v_chip_type, prom_set_trap_table_name
 102 prom_peer_name:
 103         .asciz  "peer"
 104 prom_compatible_name:
 105         .asciz  "compatible"
 106 prom_finddev_name:
 107         .asciz  "finddevice"
 108 prom_chosen_path:
 109         .asciz  "/chosen"
 110 prom_cpu_path:
 111         .asciz  "/cpu"
 112 prom_getprop_name:
 113         .asciz  "getprop"
 114 prom_mmu_name:
 115         .asciz  "mmu"
 116 prom_callmethod_name:
 117         .asciz  "call-method"
 118 prom_translate_name:
 119         .asciz  "translate"
 120 prom_map_name:
 121         .asciz  "map"
 122 prom_unmap_name:
 123         .asciz  "unmap"
 124 prom_set_trap_table_name:
 125         .asciz  "SUNW,set-trap-table"
 126 prom_sun4v_name:
 127         .asciz  "sun4v"
 128 prom_niagara_prefix:
 129         .asciz  "SUNW,UltraSPARC-T"
 130         .align  4
 131 prom_root_compatible:
 132         .skip   64
 133 prom_cpu_compatible:
 134         .skip   64
 135 prom_root_node:
 136         .word   0
 137 prom_mmu_ihandle_cache:
 138         .word   0
 139 prom_boot_mapped_pc:
 140         .word   0
 141 prom_boot_mapping_mode:
 142         .word   0
 143         .align  8
 144 prom_boot_mapping_phys_high:
 145         .xword  0
 146 prom_boot_mapping_phys_low:
 147         .xword  0
 148 is_sun4v:
 149         .word   0
 150 sun4v_chip_type:
 151         .word   SUN4V_CHIP_INVALID
 152 1:
 153         rd      %pc, %l0
 154
 155         mov     (1b - prom_peer_name), %l1
 156         sub     %l0, %l1, %l1
 157         mov     0, %l2
 158
 159         /* prom_root_node = prom_peer(0) */
 160         stx     %l1, [%sp + 2047 + 128 + 0x00]  ! service, "peer"
 161         mov     1, %l3
 162         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 1
 163         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 1
 164         stx     %l2, [%sp + 2047 + 128 + 0x18]  ! arg1, 0
 165         stx     %g0, [%sp + 2047 + 128 + 0x20]  ! ret1
 166         call    %l7
 167          add    %sp, (2047 + 128), %o0          ! argument array
 168
 169         ldx     [%sp + 2047 + 128 + 0x20], %l4  ! prom root node
 170         mov     (1b - prom_root_node), %l1
 171         sub     %l0, %l1, %l1
 172         stw     %l4, [%l1]
 173
 174         mov     (1b - prom_getprop_name), %l1
 175         mov     (1b - prom_compatible_name), %l2
 176         mov     (1b - prom_root_compatible), %l5
 177         sub     %l0, %l1, %l1
 178         sub     %l0, %l2, %l2
 179         sub     %l0, %l5, %l5
 180
 181         /* prom_getproperty(prom_root_node, "compatible",
 182          *                  &prom_root_compatible, 64)
 183          */
 184         stx     %l1, [%sp + 2047 + 128 + 0x00]  ! service, "getprop"
 185         mov     4, %l3
 186         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 4
 187         mov     1, %l3
 188         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 1
 189         stx     %l4, [%sp + 2047 + 128 + 0x18]  ! arg1, prom_root_node
 190         stx     %l2, [%sp + 2047 + 128 + 0x20]  ! arg2, "compatible"
 191         stx     %l5, [%sp + 2047 + 128 + 0x28]  ! arg3, &prom_root_compatible
 192         mov     64, %l3
 193         stx     %l3, [%sp + 2047 + 128 + 0x30]  ! arg4, size
 194         stx     %g0, [%sp + 2047 + 128 + 0x38]  ! ret1
 195         call    %l7
 196          add    %sp, (2047 + 128), %o0          ! argument array
 197
 198         mov     (1b - prom_finddev_name), %l1
 199         mov     (1b - prom_chosen_path), %l2
 200         mov     (1b - prom_boot_mapped_pc), %l3
 201         sub     %l0, %l1, %l1
 202         sub     %l0, %l2, %l2
 203         sub     %l0, %l3, %l3
 204         stw     %l0, [%l3]
 205         sub     %sp, (192 + 128), %sp
 206
 207         /* chosen_node = prom_finddevice("/chosen") */
 208         stx     %l1, [%sp + 2047 + 128 + 0x00]  ! service, "finddevice"
 209         mov     1, %l3
 210         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 1
 211         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 1
 212         stx     %l2, [%sp + 2047 + 128 + 0x18]  ! arg1, "/chosen"
 213         stx     %g0, [%sp + 2047 + 128 + 0x20]  ! ret1
 214         call    %l7
 215          add    %sp, (2047 + 128), %o0          ! argument array
 216
 217         ldx     [%sp + 2047 + 128 + 0x20], %l4  ! chosen device node
 218
 219         mov     (1b - prom_getprop_name), %l1
 220         mov     (1b - prom_mmu_name), %l2
 221         mov     (1b - prom_mmu_ihandle_cache), %l5
 222         sub     %l0, %l1, %l1
 223         sub     %l0, %l2, %l2
 224         sub     %l0, %l5, %l5
 225
 226         /* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
 227         stx     %l1, [%sp + 2047 + 128 + 0x00]  ! service, "getprop"
 228         mov     4, %l3
 229         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 4
 230         mov     1, %l3
 231         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 1
 232         stx     %l4, [%sp + 2047 + 128 + 0x18]  ! arg1, chosen_node
 233         stx     %l2, [%sp + 2047 + 128 + 0x20]  ! arg2, "mmu"
 234         stx     %l5, [%sp + 2047 + 128 + 0x28]  ! arg3, &prom_mmu_ihandle_cache
 235         mov     4, %l3
 236         stx     %l3, [%sp + 2047 + 128 + 0x30]  ! arg4, sizeof(arg3)
 237         stx     %g0, [%sp + 2047 + 128 + 0x38]  ! ret1
 238         call    %l7
 239          add    %sp, (2047 + 128), %o0          ! argument array
 240
 241         mov     (1b - prom_callmethod_name), %l1
 242         mov     (1b - prom_translate_name), %l2
 243         sub     %l0, %l1, %l1
 244         sub     %l0, %l2, %l2
 245         lduw    [%l5], %l5                      ! prom_mmu_ihandle_cache
 246
 247         stx     %l1, [%sp + 2047 + 128 + 0x00]  ! service, "call-method"
 248         mov     3, %l3
 249         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 3
 250         mov     5, %l3
 251         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 5
 252         stx     %l2, [%sp + 2047 + 128 + 0x18]  ! arg1: "translate"
 253         stx     %l5, [%sp + 2047 + 128 + 0x20]  ! arg2: prom_mmu_ihandle_cache
 254         /* PAGE align */
 255         srlx    %l0, 13, %l3
 256         sllx    %l3, 13, %l3
 257         stx     %l3, [%sp + 2047 + 128 + 0x28]  ! arg3: vaddr, our PC
 258         stx     %g0, [%sp + 2047 + 128 + 0x30]  ! res1
 259         stx     %g0, [%sp + 2047 + 128 + 0x38]  ! res2
 260         stx     %g0, [%sp + 2047 + 128 + 0x40]  ! res3
 261         stx     %g0, [%sp + 2047 + 128 + 0x48]  ! res4
 262         stx     %g0, [%sp + 2047 + 128 + 0x50]  ! res5
 263         call    %l7
 264          add    %sp, (2047 + 128), %o0          ! argument array
 265
 266         ldx     [%sp + 2047 + 128 + 0x40], %l1  ! translation mode
 267         mov     (1b - prom_boot_mapping_mode), %l4
 268         sub     %l0, %l4, %l4
 269         stw     %l1, [%l4]
 270         mov     (1b - prom_boot_mapping_phys_high), %l4
 271         sub     %l0, %l4, %l4
 272         ldx     [%sp + 2047 + 128 + 0x48], %l2  ! physaddr high
 273         stx     %l2, [%l4 + 0x0]
 274         ldx     [%sp + 2047 + 128 + 0x50], %l3  ! physaddr low
 275         /* 4MB align */
 276         srlx    %l3, 22, %l3
 277         sllx    %l3, 22, %l3
 278         stx     %l3, [%l4 + 0x8]
 279
 280         /* Leave service as-is, "call-method" */
 281         mov     7, %l3
 282         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 7
 283         mov     1, %l3
 284         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 1
 285         mov     (1b - prom_map_name), %l3
 286         sub     %l0, %l3, %l3
 287         stx     %l3, [%sp + 2047 + 128 + 0x18]  ! arg1: "map"
 288         /* Leave arg2 as-is, prom_mmu_ihandle_cache */
 289         mov     -1, %l3
 290         stx     %l3, [%sp + 2047 + 128 + 0x28]  ! arg3: mode (-1 default)
 291         sethi   %hi(8 * 1024 * 1024), %l3
 292         stx     %l3, [%sp + 2047 + 128 + 0x30]  ! arg4: size (8MB)
 293         sethi   %hi(KERNBASE), %l3
 294         stx     %l3, [%sp + 2047 + 128 + 0x38]  ! arg5: vaddr (KERNBASE)
 295         stx     %g0, [%sp + 2047 + 128 + 0x40]  ! arg6: empty
 296         mov     (1b - prom_boot_mapping_phys_low), %l3
 297         sub     %l0, %l3, %l3
 298         ldx     [%l3], %l3
 299         stx     %l3, [%sp + 2047 + 128 + 0x48]  ! arg7: phys addr
 300         call    %l7
 301          add    %sp, (2047 + 128), %o0          ! argument array
 302
 303         add     %sp, (192 + 128), %sp
 304
 305         sethi   %hi(prom_root_compatible), %g1
 306         or      %g1, %lo(prom_root_compatible), %g1
 307         sethi   %hi(prom_sun4v_name), %g7
 308         or      %g7, %lo(prom_sun4v_name), %g7
 309         mov     5, %g3
 310 90:     ldub    [%g7], %g2
 311         ldub    [%g1], %g4
 312         cmp     %g2, %g4
 313         bne,pn  %icc, 80f
 314          add    %g7, 1, %g7
 315         subcc   %g3, 1, %g3
 316         bne,pt  %xcc, 90b
 317          add    %g1, 1, %g1
 318
 319         sethi   %hi(is_sun4v), %g1
 320         or      %g1, %lo(is_sun4v), %g1
 321         mov     1, %g7
 322         stw     %g7, [%g1]
 323
 324         /* cpu_node = prom_finddevice("/cpu") */
 325         mov     (1b - prom_finddev_name), %l1
 326         mov     (1b - prom_cpu_path), %l2
 327         sub     %l0, %l1, %l1
 328         sub     %l0, %l2, %l2
 329         sub     %sp, (192 + 128), %sp
 330
 331         stx     %l1, [%sp + 2047 + 128 + 0x00]  ! service, "finddevice"
 332         mov     1, %l3
 333         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 1
 334         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 1
 335         stx     %l2, [%sp + 2047 + 128 + 0x18]  ! arg1, "/cpu"
 336         stx     %g0, [%sp + 2047 + 128 + 0x20]  ! ret1
 337         call    %l7
 338          add    %sp, (2047 + 128), %o0          ! argument array
 339
 340         ldx     [%sp + 2047 + 128 + 0x20], %l4  ! cpu device node
 341
 342         mov     (1b - prom_getprop_name), %l1
 343         mov     (1b - prom_compatible_name), %l2
 344         mov     (1b - prom_cpu_compatible), %l5
 345         sub     %l0, %l1, %l1
 346         sub     %l0, %l2, %l2
 347         sub     %l0, %l5, %l5
 348
 349         /* prom_getproperty(cpu_node, "compatible",
 350          *                  &prom_cpu_compatible, 64)
 351          */
 352         stx     %l1, [%sp + 2047 + 128 + 0x00]  ! service, "getprop"
 353         mov     4, %l3
 354         stx     %l3, [%sp + 2047 + 128 + 0x08]  ! num_args, 4
 355         mov     1, %l3
 356         stx     %l3, [%sp + 2047 + 128 + 0x10]  ! num_rets, 1
 357         stx     %l4, [%sp + 2047 + 128 + 0x18]  ! arg1, cpu_node
 358         stx     %l2, [%sp + 2047 + 128 + 0x20]  ! arg2, "compatible"
 359         stx     %l5, [%sp + 2047 + 128 + 0x28]  ! arg3, &prom_cpu_compatible
 360         mov     64, %l3
 361         stx     %l3, [%sp + 2047 + 128 + 0x30]  ! arg4, size
 362         stx     %g0, [%sp + 2047 + 128 + 0x38]  ! ret1
 363         call    %l7
 364          add    %sp, (2047 + 128), %o0          ! argument array
 365
 366         add     %sp, (192 + 128), %sp
 367
 368         sethi   %hi(prom_cpu_compatible), %g1
 369         or      %g1, %lo(prom_cpu_compatible), %g1
 370         sethi   %hi(prom_niagara_prefix), %g7
 371         or      %g7, %lo(prom_niagara_prefix), %g7
 372         mov     17, %g3
 373 90:     ldub    [%g7], %g2
 374         ldub    [%g1], %g4
 375         cmp     %g2, %g4
 376         bne,pn  %icc, 4f
 377          add    %g7, 1, %g7
 378         subcc   %g3, 1, %g3
 379         bne,pt  %xcc, 90b
 380          add    %g1, 1, %g1
 381
 382         sethi   %hi(prom_cpu_compatible), %g1
 383         or      %g1, %lo(prom_cpu_compatible), %g1
 384         ldub    [%g1 + 17], %g2
 385         cmp     %g2, '1'
 386         be,pt   %xcc, 5f
 387          mov    SUN4V_CHIP_NIAGARA1, %g4
 388         cmp     %g2, '2'
 389         be,pt   %xcc, 5f
 390          mov    SUN4V_CHIP_NIAGARA2, %g4
 391 4:
 392         mov     SUN4V_CHIP_UNKNOWN, %g4
 393 5:      sethi   %hi(sun4v_chip_type), %g2
 394         or      %g2, %lo(sun4v_chip_type), %g2
 395         stw     %g4, [%g2]
 396
 397 80:
 398         BRANCH_IF_SUN4V(g1, jump_to_sun4u_init)
 399         BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
 400         BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
 401         ba,pt   %xcc, spitfire_boot
 402          nop
 403
 404 cheetah_plus_boot:
 405         /* Preserve OBP chosen DCU and DCR register settings.  */
 406         ba,pt   %xcc, cheetah_generic_boot
 407          nop
 408
 409 cheetah_boot:
 410         mov     DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
 411         wr      %g1, %asr18
 412
 413         sethi   %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
 414         or      %g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
 415         sllx    %g7, 32, %g7
 416         or      %g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7
 417         stxa    %g7, [%g0] ASI_DCU_CONTROL_REG
 418         membar  #Sync
 419
 420 cheetah_generic_boot:
 421         mov     TSB_EXTENSION_P, %g3
 422         stxa    %g0, [%g3] ASI_DMMU
 423         stxa    %g0, [%g3] ASI_IMMU
 424         membar  #Sync
 425
 426         mov     TSB_EXTENSION_S, %g3
 427         stxa    %g0, [%g3] ASI_DMMU
 428         membar  #Sync
 429
 430         mov     TSB_EXTENSION_N, %g3
 431         stxa    %g0, [%g3] ASI_DMMU
 432         stxa    %g0, [%g3] ASI_IMMU
 433         membar  #Sync
 434
 435         ba,a,pt %xcc, jump_to_sun4u_init
 436
 437 spitfire_boot:
 438         /* Typically PROM has already enabled both MMU's and both on-chip
 439          * caches, but we do it here anyway just to be paranoid.
 440          */
 441         mov     (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1
 442         stxa    %g1, [%g0] ASI_LSU_CONTROL
 443         membar  #Sync
 444
 445 jump_to_sun4u_init:
 446         /*
 447          * Make sure we are in privileged mode, have address masking,
 448          * using the ordinary globals and have enabled floating
 449          * point.
 450          *
 451          * Again, typically PROM has left %pil at 13 or similar, and
 452          * (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate.
 453          */
 454         wrpr    %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
 455         wr      %g0, 0, %fprs
 456
 457         set     sun4u_init, %g2
 458         jmpl    %g2 + %g0, %g0
 459          nop
 460
 461         .section        .text.init.refok
 462 sun4u_init:
 463         BRANCH_IF_SUN4V(g1, sun4v_init)
 464
 465         /* Set ctx 0 */
 466         mov             PRIMARY_CONTEXT, %g7
 467         stxa            %g0, [%g7] ASI_DMMU
 468         membar          #Sync
 469
 470         mov             SECONDARY_CONTEXT, %g7
 471         stxa            %g0, [%g7] ASI_DMMU
 472         membar  #Sync
 473
 474         ba,pt           %xcc, sun4u_continue
 475          nop
 476
 477 sun4v_init:
 478         /* Set ctx 0 */
 479         mov             PRIMARY_CONTEXT, %g7
 480         stxa            %g0, [%g7] ASI_MMU
 481         membar          #Sync
 482
 483         mov             SECONDARY_CONTEXT, %g7
 484         stxa            %g0, [%g7] ASI_MMU
 485         membar          #Sync
 486         ba,pt           %xcc, niagara_tlb_fixup
 487          nop
 488
 489 sun4u_continue:
 490         BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup)
 491
 492         ba,pt   %xcc, spitfire_tlb_fixup
 493          nop
 494
 495 niagara_tlb_fixup:
 496         mov     3, %g2          /* Set TLB type to hypervisor. */
 497         sethi   %hi(tlb_type), %g1
 498         stw     %g2, [%g1 + %lo(tlb_type)]
 499
 500         /* Patch copy/clear ops.  */
 501         sethi   %hi(sun4v_chip_type), %g1
 502         lduw    [%g1 + %lo(sun4v_chip_type)], %g1
 503         cmp     %g1, SUN4V_CHIP_NIAGARA1
 504         be,pt   %xcc, niagara_patch
 505          cmp    %g1, SUN4V_CHIP_NIAGARA2
 506         be,pt   %xcc, niagara2_patch
 507          nop
 508
 509         call    generic_patch_copyops
 510          nop
 511         call    generic_patch_bzero
 512          nop
 513         call    generic_patch_pageops
 514          nop
 515
 516         ba,a,pt %xcc, 80f
 517 niagara2_patch:
 518         call    niagara2_patch_copyops
 519          nop
 520         call    niagara_patch_bzero
 521          nop
 522         call    niagara2_patch_pageops
 523          nop
 524
 525         ba,a,pt %xcc, 80f
 526
 527 niagara_patch:
 528         call    niagara_patch_copyops
 529          nop
 530         call    niagara_patch_bzero
 531          nop
 532         call    niagara_patch_pageops
 533          nop
 534
 535 80:
 536         /* Patch TLB/cache ops.  */
 537         call    hypervisor_patch_cachetlbops
 538          nop
 539
 540         ba,pt   %xcc, tlb_fixup_done
 541          nop
 542
 543 cheetah_tlb_fixup:
 544         mov     2, %g2          /* Set TLB type to cheetah+. */
 545         BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
 546
 547         mov     1, %g2          /* Set TLB type to cheetah. */
 548
 549 1:      sethi   %hi(tlb_type), %g1
 550         stw     %g2, [%g1 + %lo(tlb_type)]
 551
 552         /* Patch copy/page operations to cheetah optimized versions. */
 553         call    cheetah_patch_copyops
 554          nop
 555         call    cheetah_patch_copy_page
 556          nop
 557         call    cheetah_patch_cachetlbops
 558          nop
 559
 560         ba,pt   %xcc, tlb_fixup_done
 561          nop
 562
 563 spitfire_tlb_fixup:
 564         /* Set TLB type to spitfire. */
 565         mov     0, %g2
 566         sethi   %hi(tlb_type), %g1
 567         stw     %g2, [%g1 + %lo(tlb_type)]
 568
 569 tlb_fixup_done:
 570         sethi   %hi(init_thread_union), %g6
 571         or      %g6, %lo(init_thread_union), %g6
 572         ldx     [%g6 + TI_TASK], %g4
 573         mov     %sp, %l6
 574
 575         wr      %g0, ASI_P, %asi
 576         mov     1, %g1
 577         sllx    %g1, THREAD_SHIFT, %g1
 578         sub     %g1, (STACKFRAME_SZ + STACK_BIAS), %g1
 579         add     %g6, %g1, %sp
 580         mov     0, %fp
 581
 582         /* Set per-cpu pointer initially to zero, this makes
 583          * the boot-cpu use the in-kernel-image per-cpu areas
 584          * before setup_per_cpu_area() is invoked.
 585          */
 586         clr     %g5
 587
 588         wrpr    %g0, 0, %wstate
 589         wrpr    %g0, 0x0, %tl
 590
 591         /* Clear the bss */
 592         sethi   %hi(__bss_start), %o0
 593         or      %o0, %lo(__bss_start), %o0
 594         sethi   %hi(_end), %o1
 595         or      %o1, %lo(_end), %o1
 596         call    __bzero
 597          sub    %o1, %o0, %o1
 598
 599 #ifdef CONFIG_LOCKDEP
 600         /* We have this call this super early, as even prom_init can grab
 601          * spinlocks and thus call into the lockdep code.
 602          */
 603         call    lockdep_init
 604          nop
 605 #endif
 606
 607         mov     %l6, %o1                        ! OpenPROM stack
 608         call    prom_init
 609          mov    %l7, %o0                        ! OpenPROM cif handler
 610
 611         /* Initialize current_thread_info()->cpu as early as possible.
 612          * In order to do that accurately we have to patch up the get_cpuid()
 613          * assembler sequences.  And that, in turn, requires that we know
 614          * if we are on a Starfire box or not.  While we're here, patch up
 615          * the sun4v sequences as well.
 616          */
 617         call    check_if_starfire
 618          nop
 619         call    per_cpu_patch
 620          nop
 621         call    sun4v_patch
 622          nop
 623
 624 #ifdef CONFIG_SMP
 625         call    hard_smp_processor_id
 626          nop
 627         cmp     %o0, NR_CPUS
 628         blu,pt  %xcc, 1f
 629          nop
 630         call    boot_cpu_id_too_large
 631          nop
 632         /* Not reached... */
 633
 634 1:
 635 #else
 636         mov     0, %o0
 637 #endif
 638         sth     %o0, [%g6 + TI_CPU]
 639
 640         /* Off we go.... */
 641         call    start_kernel
 642          nop
 643         /* Not reached... */
 644
 645         .previous
 646
 647         /* This is meant to allow the sharing of this code between
 648          * boot processor invocation (via setup_tba() below) and
 649          * secondary processor startup (via trampoline.S).  The
 650          * former does use this code, the latter does not yet due
 651          * to some complexities.  That should be fixed up at some
 652          * point.
 653          *
 654          * There used to be enormous complexity wrt. transferring
 655          * over from the firwmare's trap table to the Linux kernel's.
 656          * For example, there was a chicken & egg problem wrt. building
 657          * the OBP page tables, yet needing to be on the Linux kernel
 658          * trap table (to translate PAGE_OFFSET addresses) in order to
 659          * do that.
 660          *
 661          * We now handle OBP tlb misses differently, via linear lookups
 662          * into the prom_trans[] array.  So that specific problem no
 663          * longer exists.  Yet, unfortunately there are still some issues
 664          * preventing trampoline.S from using this code... ho hum.
 665          */
 666         .globl  setup_trap_table
 667 setup_trap_table:
 668         save    %sp, -192, %sp
 669
 670         /* Force interrupts to be disabled. */
 671         rdpr    %pstate, %l0
 672         andn    %l0, PSTATE_IE, %o1
 673         wrpr    %o1, 0x0, %pstate
 674         rdpr    %pil, %l1
 675         wrpr    %g0, 15, %pil
 676
 677         /* Make the firmware call to jump over to the Linux trap table.  */
 678         sethi   %hi(is_sun4v), %o0
 679         lduw    [%o0 + %lo(is_sun4v)], %o0
 680         brz,pt  %o0, 1f
 681          nop
 682
 683         TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
 684         add     %g2, TRAP_PER_CPU_FAULT_INFO, %g2
 685         stxa    %g2, [%g0] ASI_SCRATCHPAD
 686
 687         /* Compute physical address:
 688          *
 689          * paddr = kern_base + (mmfsa_vaddr - KERNBASE)
 690          */
 691         sethi   %hi(KERNBASE), %g3
 692         sub     %g2, %g3, %g2
 693         sethi   %hi(kern_base), %g3
 694         ldx     [%g3 + %lo(kern_base)], %g3
 695         add     %g2, %g3, %o1
 696         sethi   %hi(sparc64_ttable_tl0), %o0
 697
 698         set     prom_set_trap_table_name, %g2
 699         stx     %g2, [%sp + 2047 + 128 + 0x00]
 700         mov     2, %g2
 701         stx     %g2, [%sp + 2047 + 128 + 0x08]
 702         mov     0, %g2
 703         stx     %g2, [%sp + 2047 + 128 + 0x10]
 704         stx     %o0, [%sp + 2047 + 128 + 0x18]
 705         stx     %o1, [%sp + 2047 + 128 + 0x20]
 706         sethi   %hi(p1275buf), %g2
 707         or      %g2, %lo(p1275buf), %g2
 708         ldx     [%g2 + 0x08], %o1
 709         call    %o1
 710          add    %sp, (2047 + 128), %o0
 711
 712         ba,pt   %xcc, 2f
 713          nop
 714
 715 1:      sethi   %hi(sparc64_ttable_tl0), %o0
 716         set     prom_set_trap_table_name, %g2
 717         stx     %g2, [%sp + 2047 + 128 + 0x00]
 718         mov     1, %g2
 719         stx     %g2, [%sp + 2047 + 128 + 0x08]
 720         mov     0, %g2
 721         stx     %g2, [%sp + 2047 + 128 + 0x10]
 722         stx     %o0, [%sp + 2047 + 128 + 0x18]
 723         sethi   %hi(p1275buf), %g2
 724         or      %g2, %lo(p1275buf), %g2
 725         ldx     [%g2 + 0x08], %o1
 726         call    %o1
 727          add    %sp, (2047 + 128), %o0
 728
 729         /* Start using proper page size encodings in ctx register.  */
 730 2:      sethi   %hi(sparc64_kern_pri_context), %g3
 731         ldx     [%g3 + %lo(sparc64_kern_pri_context)], %g2
 732
 733         mov             PRIMARY_CONTEXT, %g1
 734
 735 661:    stxa            %g2, [%g1] ASI_DMMU
 736         .section        .sun4v_1insn_patch, "ax"
 737         .word           661b
 738         stxa            %g2, [%g1] ASI_MMU
 739         .previous
 740
 741         membar  #Sync
 742
 743         BRANCH_IF_SUN4V(o2, 1f)
 744
 745         /* Kill PROM timer */
 746         sethi   %hi(0x80000000), %o2
 747         sllx    %o2, 32, %o2
 748         wr      %o2, 0, %tick_cmpr
 749
 750         BRANCH_IF_ANY_CHEETAH(o2, o3, 1f)
 751
 752         ba,pt   %xcc, 2f
 753          nop
 754
 755         /* Disable STICK_INT interrupts. */
 756 1:
 757         sethi   %hi(0x80000000), %o2
 758         sllx    %o2, 32, %o2
 759         wr      %o2, %asr25
 760
 761 2:
 762         wrpr    %g0, %g0, %wstate
 763
 764         call    init_irqwork_curcpu
 765          nop
 766
 767         /* Now we can restore interrupt state. */
 768         wrpr    %l0, 0, %pstate
 769         wrpr    %l1, 0x0, %pil
 770
 771         ret
 772          restore
 773
 774         .globl  setup_tba
 775 setup_tba:
 776         save    %sp, -192, %sp
 777
 778         /* The boot processor is the only cpu which invokes this
 779          * routine, the other cpus set things up via trampoline.S.
 780          * So save the OBP trap table address here.
 781          */
 782         rdpr    %tba, %g7
 783         sethi   %hi(prom_tba), %o1
 784         or      %o1, %lo(prom_tba), %o1
 785         stx     %g7, [%o1]
 786
 787         call    setup_trap_table
 788          nop
 789
 790         ret
 791          restore
 792 sparc64_boot_end:
 793
 794 #include "etrap.S"
 795 #include "rtrap.S"
 796 #include "winfixup.S"
 797 #include "entry.S"
 798 #include "sun4v_tlb_miss.S"
 799 #include "sun4v_ivec.S"
 800 #include "ktlb.S"
 801 #include "tsb.S"
 802
 803 /*
 804  * The following skip makes sure the trap table in ttable.S is aligned
 805  * on a 32K boundary as required by the v9 specs for TBA register.
 806  *
 807  * We align to a 32K boundary, then we have the 32K kernel TSB,
 808  * the 64K kernel 4MB TSB, and then the 32K aligned trap table.
 809  */
 810 1:
 811         .skip   0x4000 + _start - 1b
 812
 813 ! 0x0000000000408000
 814
 815         .globl  swapper_tsb
 816 swapper_tsb:
 817         .skip   (32 * 1024)
 818
 819         .globl  swapper_4m_tsb
 820 swapper_4m_tsb:
 821         .skip   (64 * 1024)
 822
 823 ! 0x0000000000420000
 824
 825         /* Some care needs to be exercised if you try to move the
 826          * location of the trap table relative to other things.  For
 827          * one thing there are br* instructions in some of the
 828          * trap table entires which branch back to code in ktlb.S
 829          * Those instructions can only handle a signed 16-bit
 830          * displacement.
 831          *
 832          * There is a binutils bug (bugzilla #4558) which causes
 833          * the relocation overflow checks for such instructions to
 834          * not be done correctly.  So bintuils will not notice the
 835          * error and will instead write junk into the relocation and
 836          * you'll have an unbootable kernel.
 837          */
 838 #include "ttable.S"
 839
 840 ! 0x0000000000428000
 841
 842 #include "systbls.S"
 843
 844         .data
 845         .align  8
 846         .globl  prom_tba, tlb_type
 847 prom_tba:       .xword  0
 848 tlb_type:       .word   0       /* Must NOT end up in BSS */
 849         .section        ".fixup",#alloc,#execinstr
 850
 851         .globl  __ret_efault, __retl_efault
 852 __ret_efault:
 853         ret
 854          restore %g0, -EFAULT, %o0
 855 __retl_efault:
 856         retl
 857          mov    -EFAULT, %o0