arch/sparc64/kernel/hvtramp.S

   1 /* hvtramp.S: Hypervisor start-cpu trampoline code.
   2  *
   3  * Copyright (C) 2007 David S. Miller <davem@davemloft.net>
   4  */
   5
   6 #include <asm/thread_info.h>
   7 #include <asm/hypervisor.h>
   8 #include <asm/scratchpad.h>
   9 #include <asm/spitfire.h>
  10 #include <asm/hvtramp.h>
  11 #include <asm/pstate.h>
  12 #include <asm/ptrace.h>
  13 #include <asm/head.h>
  14 #include <asm/asi.h>
  15
  16         .text
  17         .align          8
  18         .globl          hv_cpu_startup, hv_cpu_startup_end
  19
  20         /* This code executes directly out of the hypervisor
  21          * with physical addressing (va==pa).  %o0 contains
  22          * our client argument which for Linux points to
  23          * a descriptor data structure which defines the
  24          * MMU entries we need to load up.
  25          *
  26          * After we set things up we enable the MMU and call
  27          * into the kernel.
  28          *
  29          * First setup basic privileged cpu state.
  30          */
  31 hv_cpu_startup:
  32         SET_GL(0)
  33         wrpr            %g0, 15, %pil
  34         wrpr            %g0, 0, %canrestore
  35         wrpr            %g0, 0, %otherwin
  36         wrpr            %g0, 6, %cansave
  37         wrpr            %g0, 6, %cleanwin
  38         wrpr            %g0, 0, %cwp
  39         wrpr            %g0, 0, %wstate
  40         wrpr            %g0, 0, %tl
  41
  42         sethi           %hi(sparc64_ttable_tl0), %g1
  43         wrpr            %g1, %tba
  44
  45         mov             %o0, %l0
  46
  47         lduw            [%l0 + HVTRAMP_DESCR_CPU], %g1
  48         mov             SCRATCHPAD_CPUID, %g2
  49         stxa            %g1, [%g2] ASI_SCRATCHPAD
  50
  51         ldx             [%l0 + HVTRAMP_DESCR_FAULT_INFO_VA], %g2
  52         stxa            %g2, [%g0] ASI_SCRATCHPAD
  53
  54         mov             0, %l1
  55         lduw            [%l0 + HVTRAMP_DESCR_NUM_MAPPINGS], %l2
  56         add             %l0, HVTRAMP_DESCR_MAPS, %l3
  57
  58 1:      ldx             [%l3 + HVTRAMP_MAPPING_VADDR], %o0
  59         clr             %o1
  60         ldx             [%l3 + HVTRAMP_MAPPING_TTE], %o2
  61         mov             HV_MMU_IMMU | HV_MMU_DMMU, %o3
  62         mov             HV_FAST_MMU_MAP_PERM_ADDR, %o5
  63         ta              HV_FAST_TRAP
  64
  65         brnz,pn         %o0, 80f
  66          nop
  67
  68         add             %l1, 1, %l1
  69         cmp             %l1, %l2
  70         blt,a,pt        %xcc, 1b
  71          add            %l3, HVTRAMP_MAPPING_SIZE, %l3
  72
  73         ldx             [%l0 + HVTRAMP_DESCR_FAULT_INFO_PA], %o0
  74         mov             HV_FAST_MMU_FAULT_AREA_CONF, %o5
  75         ta              HV_FAST_TRAP
  76
  77         brnz,pn         %o0, 80f
  78          nop
  79
  80         wrpr            %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate
  81
  82         ldx             [%l0 + HVTRAMP_DESCR_THREAD_REG], %l6
  83
  84         mov             1, %o0
  85         set             1f, %o1
  86         mov             HV_FAST_MMU_ENABLE, %o5
  87         ta              HV_FAST_TRAP
  88
  89         ba,pt           %xcc, 80f
  90          nop
  91
  92 1:
  93         wr              %g0, 0, %fprs
  94         wr              %g0, ASI_P, %asi
  95
  96         mov             PRIMARY_CONTEXT, %g7
  97         stxa            %g0, [%g7] ASI_MMU
  98         membar          #Sync
  99
 100         mov             SECONDARY_CONTEXT, %g7
 101         stxa            %g0, [%g7] ASI_MMU
 102         membar          #Sync
 103
 104         mov             %l6, %g6
 105         ldx             [%g6 + TI_TASK], %g4
 106
 107         mov             1, %g5
 108         sllx            %g5, THREAD_SHIFT, %g5
 109         sub             %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
 110         add             %g6, %g5, %sp
 111         mov             0, %fp
 112
 113         call            init_irqwork_curcpu
 114          nop
 115         call            hard_smp_processor_id
 116          nop
 117
 118         mov             %o0, %o1
 119         mov             0, %o0
 120         mov             0, %o2
 121         call            sun4v_init_mondo_queues
 122          mov            1, %o3
 123
 124         call            init_cur_cpu_trap
 125          mov            %g6, %o0
 126
 127         wrpr            %g0, (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE), %pstate
 128
 129         call            smp_callin
 130          nop
 131         call            cpu_idle
 132          mov            0, %o0
 133         call            cpu_panic
 134          nop
 135
 136 80:     ba,pt           %xcc, 80b
 137          nop
 138
 139         .align          8
 140 hv_cpu_startup_end: