arch/sparc64/kernel/iommu.c

   1 /* iommu.c: Generic sparc64 IOMMU support.
   2  *
   3  * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
   4  * Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com)
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/module.h>
   9 #include <linux/delay.h>
  10 #include <linux/device.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/errno.h>
  13 #include <linux/scatterlist.h>
  14
  15 #ifdef CONFIG_PCI
  16 #include <linux/pci.h>
  17 #endif
  18
  19 #include <asm/iommu.h>
  20
  21 #include "iommu_common.h"
  22
  23 #define STC_CTXMATCH_ADDR(STC, CTX)     \
  24         ((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
  25 #define STC_FLUSHFLAG_INIT(STC) \
  26         (*((STC)->strbuf_flushflag) = 0UL)
  27 #define STC_FLUSHFLAG_SET(STC) \
  28         (*((STC)->strbuf_flushflag) != 0UL)
  29
  30 #define iommu_read(__reg) \
  31 ({      u64 __ret; \
  32         __asm__ __volatile__("ldxa [%1] %2, %0" \
  33                              : "=r" (__ret) \
  34                              : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
  35                              : "memory"); \
  36         __ret; \
  37 })
  38 #define iommu_write(__reg, __val) \
  39         __asm__ __volatile__("stxa %0, [%1] %2" \
  40                              : /* no outputs */ \
  41                              : "r" (__val), "r" (__reg), \
  42                                "i" (ASI_PHYS_BYPASS_EC_E))
  43
  44 /* Must be invoked under the IOMMU lock. */
  45 static void __iommu_flushall(struct iommu *iommu)
  46 {
  47         if (iommu->iommu_flushinv) {
  48                 iommu_write(iommu->iommu_flushinv, ~(u64)0);
  49         } else {
  50                 unsigned long tag;
  51                 int entry;
  52
  53                 tag = iommu->iommu_tags;
  54                 for (entry = 0; entry < 16; entry++) {
  55                         iommu_write(tag, 0);
  56                         tag += 8;
  57                 }
  58
  59                 /* Ensure completion of previous PIO writes. */
  60                 (void) iommu_read(iommu->write_complete_reg);
  61         }
  62 }
  63
  64 #define IOPTE_CONSISTENT(CTX) \
  65         (IOPTE_VALID | IOPTE_CACHE | \
  66          (((CTX) << 47) & IOPTE_CONTEXT))
  67
  68 #define IOPTE_STREAMING(CTX) \
  69         (IOPTE_CONSISTENT(CTX) | IOPTE_STBUF)
  70
  71 /* Existing mappings are never marked invalid, instead they
  72  * are pointed to a dummy page.
  73  */
  74 #define IOPTE_IS_DUMMY(iommu, iopte)    \
  75         ((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa)
  76
  77 static inline void iopte_make_dummy(struct iommu *iommu, iopte_t *iopte)
  78 {
  79         unsigned long val = iopte_val(*iopte);
  80
  81         val &= ~IOPTE_PAGE;
  82         val |= iommu->dummy_page_pa;
  83
  84         iopte_val(*iopte) = val;
  85 }
  86
  87 /* Based largely upon the ppc64 iommu allocator.  */
  88 static long arena_alloc(struct iommu *iommu, unsigned long npages)
  89 {
  90         struct iommu_arena *arena = &iommu->arena;
  91         unsigned long n, i, start, end, limit;
  92         int pass;
  93
  94         limit = arena->limit;
  95         start = arena->hint;
  96         pass = 0;
  97
  98 again:
  99         n = find_next_zero_bit(arena->map, limit, start);
 100         end = n + npages;
 101         if (unlikely(end >= limit)) {
 102                 if (likely(pass < 1)) {
 103                         limit = start;
 104                         start = 0;
 105                         __iommu_flushall(iommu);
 106                         pass++;
 107                         goto again;
 108                 } else {
 109                         /* Scanned the whole thing, give up. */
 110                         return -1;
 111                 }
 112         }
 113
 114         for (i = n; i < end; i++) {
 115                 if (test_bit(i, arena->map)) {
 116                         start = i + 1;
 117                         goto again;
 118                 }
 119         }
 120
 121         for (i = n; i < end; i++)
 122                 __set_bit(i, arena->map);
 123
 124         arena->hint = end;
 125
 126         return n;
 127 }
 128
 129 static void arena_free(struct iommu_arena *arena, unsigned long base, unsigned long npages)
 130 {
 131         unsigned long i;
 132
 133         for (i = base; i < (base + npages); i++)
 134                 __clear_bit(i, arena->map);
 135 }
 136
 137 int iommu_table_init(struct iommu *iommu, int tsbsize,
 138                      u32 dma_offset, u32 dma_addr_mask)
 139 {
 140         unsigned long i, tsbbase, order, sz, num_tsb_entries;
 141
 142         num_tsb_entries = tsbsize / sizeof(iopte_t);
 143
 144         /* Setup initial software IOMMU state. */
 145         spin_lock_init(&iommu->lock);
 146         iommu->ctx_lowest_free = 1;
 147         iommu->page_table_map_base = dma_offset;
 148         iommu->dma_addr_mask = dma_addr_mask;
 149
 150         /* Allocate and initialize the free area map.  */
 151         sz = num_tsb_entries / 8;
 152         sz = (sz + 7UL) & ~7UL;
 153         iommu->arena.map = kzalloc(sz, GFP_KERNEL);
 154         if (!iommu->arena.map) {
 155                 printk(KERN_ERR "IOMMU: Error, kmalloc(arena.map) failed.\n");
 156                 return -ENOMEM;
 157         }
 158         iommu->arena.limit = num_tsb_entries;
 159
 160         /* Allocate and initialize the dummy page which we
 161          * set inactive IO PTEs to point to.
 162          */
 163         iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0);
 164         if (!iommu->dummy_page) {
 165                 printk(KERN_ERR "IOMMU: Error, gfp(dummy_page) failed.\n");
 166                 goto out_free_map;
 167         }
 168         memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
 169         iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
 170
 171         /* Now allocate and setup the IOMMU page table itself.  */
 172         order = get_order(tsbsize);
 173         tsbbase = __get_free_pages(GFP_KERNEL, order);
 174         if (!tsbbase) {
 175                 printk(KERN_ERR "IOMMU: Error, gfp(tsb) failed.\n");
 176                 goto out_free_dummy_page;
 177         }
 178         iommu->page_table = (iopte_t *)tsbbase;
 179
 180         for (i = 0; i < num_tsb_entries; i++)
 181                 iopte_make_dummy(iommu, &iommu->page_table[i]);
 182
 183         return 0;
 184
 185 out_free_dummy_page:
 186         free_page(iommu->dummy_page);
 187         iommu->dummy_page = 0UL;
 188
 189 out_free_map:
 190         kfree(iommu->arena.map);
 191         iommu->arena.map = NULL;
 192
 193         return -ENOMEM;
 194 }
 195
 196 static inline iopte_t *alloc_npages(struct iommu *iommu, unsigned long npages)
 197 {
 198         long entry;
 199
 200         entry = arena_alloc(iommu, npages);
 201         if (unlikely(entry < 0))
 202                 return NULL;
 203
 204         return iommu->page_table + entry;
 205 }
 206
 207 static inline void free_npages(struct iommu *iommu, dma_addr_t base, unsigned long npages)
 208 {
 209         arena_free(&iommu->arena, base >> IO_PAGE_SHIFT, npages);
 210 }
 211
 212 static int iommu_alloc_ctx(struct iommu *iommu)
 213 {
 214         int lowest = iommu->ctx_lowest_free;
 215         int sz = IOMMU_NUM_CTXS - lowest;
 216         int n = find_next_zero_bit(iommu->ctx_bitmap, sz, lowest);
 217
 218         if (unlikely(n == sz)) {
 219                 n = find_next_zero_bit(iommu->ctx_bitmap, lowest, 1);
 220                 if (unlikely(n == lowest)) {
 221                         printk(KERN_WARNING "IOMMU: Ran out of contexts.\n");
 222                         n = 0;
 223                 }
 224         }
 225         if (n)
 226                 __set_bit(n, iommu->ctx_bitmap);
 227
 228         return n;
 229 }
 230
 231 static inline void iommu_free_ctx(struct iommu *iommu, int ctx)
 232 {
 233         if (likely(ctx)) {
 234                 __clear_bit(ctx, iommu->ctx_bitmap);
 235                 if (ctx < iommu->ctx_lowest_free)
 236                         iommu->ctx_lowest_free = ctx;
 237         }
 238 }
 239
 240 static void *dma_4u_alloc_coherent(struct device *dev, size_t size,
 241                                    dma_addr_t *dma_addrp, gfp_t gfp)
 242 {
 243         struct iommu *iommu;
 244         iopte_t *iopte;
 245         unsigned long flags, order, first_page;
 246         void *ret;
 247         int npages;
 248
 249         size = IO_PAGE_ALIGN(size);
 250         order = get_order(size);
 251         if (order >= 10)
 252                 return NULL;
 253
 254         first_page = __get_free_pages(gfp, order);
 255         if (first_page == 0UL)
 256                 return NULL;
 257         memset((char *)first_page, 0, PAGE_SIZE << order);
 258
 259         iommu = dev->archdata.iommu;
 260
 261         spin_lock_irqsave(&iommu->lock, flags);
 262         iopte = alloc_npages(iommu, size >> IO_PAGE_SHIFT);
 263         spin_unlock_irqrestore(&iommu->lock, flags);
 264
 265         if (unlikely(iopte == NULL)) {
 266                 free_pages(first_page, order);
 267                 return NULL;
 268         }
 269
 270         *dma_addrp = (iommu->page_table_map_base +
 271                       ((iopte - iommu->page_table) << IO_PAGE_SHIFT));
 272         ret = (void *) first_page;
 273         npages = size >> IO_PAGE_SHIFT;
 274         first_page = __pa(first_page);
 275         while (npages--) {
 276                 iopte_val(*iopte) = (IOPTE_CONSISTENT(0UL) |
 277                                      IOPTE_WRITE |
 278                                      (first_page & IOPTE_PAGE));
 279                 iopte++;
 280                 first_page += IO_PAGE_SIZE;
 281         }
 282
 283         return ret;
 284 }
 285
 286 static void dma_4u_free_coherent(struct device *dev, size_t size,
 287                                  void *cpu, dma_addr_t dvma)
 288 {
 289         struct iommu *iommu;
 290         iopte_t *iopte;
 291         unsigned long flags, order, npages;
 292
 293         npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
 294         iommu = dev->archdata.iommu;
 295         iopte = iommu->page_table +
 296                 ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
 297
 298         spin_lock_irqsave(&iommu->lock, flags);
 299
 300         free_npages(iommu, dvma - iommu->page_table_map_base, npages);
 301
 302         spin_unlock_irqrestore(&iommu->lock, flags);
 303
 304         order = get_order(size);
 305         if (order < 10)
 306                 free_pages((unsigned long)cpu, order);
 307 }
 308
 309 static dma_addr_t dma_4u_map_single(struct device *dev, void *ptr, size_t sz,
 310                                     enum dma_data_direction direction)
 311 {
 312         struct iommu *iommu;
 313         struct strbuf *strbuf;
 314         iopte_t *base;
 315         unsigned long flags, npages, oaddr;
 316         unsigned long i, base_paddr, ctx;
 317         u32 bus_addr, ret;
 318         unsigned long iopte_protection;
 319
 320         iommu = dev->archdata.iommu;
 321         strbuf = dev->archdata.stc;
 322
 323         if (unlikely(direction == DMA_NONE))
 324                 goto bad_no_ctx;
 325
 326         oaddr = (unsigned long)ptr;
 327         npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
 328         npages >>= IO_PAGE_SHIFT;
 329
 330         spin_lock_irqsave(&iommu->lock, flags);
 331         base = alloc_npages(iommu, npages);
 332         ctx = 0;
 333         if (iommu->iommu_ctxflush)
 334                 ctx = iommu_alloc_ctx(iommu);
 335         spin_unlock_irqrestore(&iommu->lock, flags);
 336
 337         if (unlikely(!base))
 338                 goto bad;
 339
 340         bus_addr = (iommu->page_table_map_base +
 341                     ((base - iommu->page_table) << IO_PAGE_SHIFT));
 342         ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
 343         base_paddr = __pa(oaddr & IO_PAGE_MASK);
 344         if (strbuf->strbuf_enabled)
 345                 iopte_protection = IOPTE_STREAMING(ctx);
 346         else
 347                 iopte_protection = IOPTE_CONSISTENT(ctx);
 348         if (direction != DMA_TO_DEVICE)
 349                 iopte_protection |= IOPTE_WRITE;
 350
 351         for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE)
 352                 iopte_val(*base) = iopte_protection | base_paddr;
 353
 354         return ret;
 355
 356 bad:
 357         iommu_free_ctx(iommu, ctx);
 358 bad_no_ctx:
 359         if (printk_ratelimit())
 360                 WARN_ON(1);
 361         return DMA_ERROR_CODE;
 362 }
 363
 364 static void strbuf_flush(struct strbuf *strbuf, struct iommu *iommu,
 365                          u32 vaddr, unsigned long ctx, unsigned long npages,
 366                          enum dma_data_direction direction)
 367 {
 368         int limit;
 369
 370         if (strbuf->strbuf_ctxflush &&
 371             iommu->iommu_ctxflush) {
 372                 unsigned long matchreg, flushreg;
 373                 u64 val;
 374
 375                 flushreg = strbuf->strbuf_ctxflush;
 376                 matchreg = STC_CTXMATCH_ADDR(strbuf, ctx);
 377
 378                 iommu_write(flushreg, ctx);
 379                 val = iommu_read(matchreg);
 380                 val &= 0xffff;
 381                 if (!val)
 382                         goto do_flush_sync;
 383
 384                 while (val) {
 385                         if (val & 0x1)
 386                                 iommu_write(flushreg, ctx);
 387                         val >>= 1;
 388                 }
 389                 val = iommu_read(matchreg);
 390                 if (unlikely(val)) {
 391                         printk(KERN_WARNING "strbuf_flush: ctx flush "
 392                                "timeout matchreg[%lx] ctx[%lx]\n",
 393                                val, ctx);
 394                         goto do_page_flush;
 395                 }
 396         } else {
 397                 unsigned long i;
 398
 399         do_page_flush:
 400                 for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE)
 401                         iommu_write(strbuf->strbuf_pflush, vaddr);
 402         }
 403
 404 do_flush_sync:
 405         /* If the device could not have possibly put dirty data into
 406          * the streaming cache, no flush-flag synchronization needs
 407          * to be performed.
 408          */
 409         if (direction == DMA_TO_DEVICE)
 410                 return;
 411
 412         STC_FLUSHFLAG_INIT(strbuf);
 413         iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
 414         (void) iommu_read(iommu->write_complete_reg);
 415
 416         limit = 100000;
 417         while (!STC_FLUSHFLAG_SET(strbuf)) {
 418                 limit--;
 419                 if (!limit)
 420                         break;
 421                 udelay(1);
 422                 rmb();
 423         }
 424         if (!limit)
 425                 printk(KERN_WARNING "strbuf_flush: flushflag timeout "
 426                        "vaddr[%08x] ctx[%lx] npages[%ld]\n",
 427                        vaddr, ctx, npages);
 428 }
 429
 430 static void dma_4u_unmap_single(struct device *dev, dma_addr_t bus_addr,
 431                                 size_t sz, enum dma_data_direction direction)
 432 {
 433         struct iommu *iommu;
 434         struct strbuf *strbuf;
 435         iopte_t *base;
 436         unsigned long flags, npages, ctx, i;
 437
 438         if (unlikely(direction == DMA_NONE)) {
 439                 if (printk_ratelimit())
 440                         WARN_ON(1);
 441                 return;
 442         }
 443
 444         iommu = dev->archdata.iommu;
 445         strbuf = dev->archdata.stc;
 446
 447         npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
 448         npages >>= IO_PAGE_SHIFT;
 449         base = iommu->page_table +
 450                 ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
 451         bus_addr &= IO_PAGE_MASK;
 452
 453         spin_lock_irqsave(&iommu->lock, flags);
 454
 455         /* Record the context, if any. */
 456         ctx = 0;
 457         if (iommu->iommu_ctxflush)
 458                 ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
 459
 460         /* Step 1: Kick data out of streaming buffers if necessary. */
 461         if (strbuf->strbuf_enabled)
 462                 strbuf_flush(strbuf, iommu, bus_addr, ctx,
 463                              npages, direction);
 464
 465         /* Step 2: Clear out TSB entries. */
 466         for (i = 0; i < npages; i++)
 467                 iopte_make_dummy(iommu, base + i);
 468
 469         free_npages(iommu, bus_addr - iommu->page_table_map_base, npages);
 470
 471         iommu_free_ctx(iommu, ctx);
 472
 473         spin_unlock_irqrestore(&iommu->lock, flags);
 474 }
 475
 476 #define SG_ENT_PHYS_ADDRESS(SG) \
 477         (__pa(page_address((SG)->page)) + (SG)->offset)
 478
 479 static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg,
 480                            int nused, int nelems,
 481                            unsigned long iopte_protection)
 482 {
 483         struct scatterlist *dma_sg = sg;
 484         struct scatterlist *sg_end = sg_last(sg, nelems);
 485         int i;
 486
 487         for (i = 0; i < nused; i++) {
 488                 unsigned long pteval = ~0UL;
 489                 u32 dma_npages;
 490
 491                 dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
 492                               dma_sg->dma_length +
 493                               ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
 494                 do {
 495                         unsigned long offset;
 496                         signed int len;
 497
 498                         /* If we are here, we know we have at least one
 499                          * more page to map.  So walk forward until we
 500                          * hit a page crossing, and begin creating new
 501                          * mappings from that spot.
 502                          */
 503                         for (;;) {
 504                                 unsigned long tmp;
 505
 506                                 tmp = SG_ENT_PHYS_ADDRESS(sg);
 507                                 len = sg->length;
 508                                 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
 509                                         pteval = tmp & IO_PAGE_MASK;
 510                                         offset = tmp & (IO_PAGE_SIZE - 1UL);
 511                                         break;
 512                                 }
 513                                 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
 514                                         pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
 515                                         offset = 0UL;
 516                                         len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
 517                                         break;
 518                                 }
 519                                 sg = sg_next(sg);
 520                         }
 521
 522                         pteval = iopte_protection | (pteval & IOPTE_PAGE);
 523                         while (len > 0) {
 524                                 *iopte++ = __iopte(pteval);
 525                                 pteval += IO_PAGE_SIZE;
 526                                 len -= (IO_PAGE_SIZE - offset);
 527                                 offset = 0;
 528                                 dma_npages--;
 529                         }
 530
 531                         pteval = (pteval & IOPTE_PAGE) + len;
 532                         sg = sg_next(sg);
 533
 534                         /* Skip over any tail mappings we've fully mapped,
 535                          * adjusting pteval along the way.  Stop when we
 536                          * detect a page crossing event.
 537                          */
 538                         while (sg != sg_end &&
 539                                (pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
 540                                (pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
 541                                ((pteval ^
 542                                  (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
 543                                 pteval += sg->length;
 544                                 sg = sg_next(sg);
 545                         }
 546                         if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
 547                                 pteval = ~0UL;
 548                 } while (dma_npages != 0);
 549                 dma_sg = sg_next(dma_sg);
 550         }
 551 }
 552
 553 static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
 554                          int nelems, enum dma_data_direction direction)
 555 {
 556         struct iommu *iommu;
 557         struct strbuf *strbuf;
 558         unsigned long flags, ctx, npages, iopte_protection;
 559         iopte_t *base;
 560         u32 dma_base;
 561         struct scatterlist *sgtmp;
 562         int used;
 563
 564         /* Fast path single entry scatterlists. */
 565         if (nelems == 1) {
 566                 sglist->dma_address =
 567                         dma_4u_map_single(dev,
 568                                           (page_address(sglist->page) +
 569                                            sglist->offset),
 570                                           sglist->length, direction);
 571                 if (unlikely(sglist->dma_address == DMA_ERROR_CODE))
 572                         return 0;
 573                 sglist->dma_length = sglist->length;
 574                 return 1;
 575         }
 576
 577         iommu = dev->archdata.iommu;
 578         strbuf = dev->archdata.stc;
 579
 580         if (unlikely(direction == DMA_NONE))
 581                 goto bad_no_ctx;
 582
 583         /* Step 1: Prepare scatter list. */
 584
 585         npages = prepare_sg(sglist, nelems);
 586
 587         /* Step 2: Allocate a cluster and context, if necessary. */
 588
 589         spin_lock_irqsave(&iommu->lock, flags);
 590
 591         base = alloc_npages(iommu, npages);
 592         ctx = 0;
 593         if (iommu->iommu_ctxflush)
 594                 ctx = iommu_alloc_ctx(iommu);
 595
 596         spin_unlock_irqrestore(&iommu->lock, flags);
 597
 598         if (base == NULL)
 599                 goto bad;
 600
 601         dma_base = iommu->page_table_map_base +
 602                 ((base - iommu->page_table) << IO_PAGE_SHIFT);
 603
 604         /* Step 3: Normalize DMA addresses. */
 605         used = nelems;
 606
 607         sgtmp = sglist;
 608         while (used && sgtmp->dma_length) {
 609                 sgtmp->dma_address += dma_base;
 610                 sgtmp = sg_next(sgtmp);
 611                 used--;
 612         }
 613         used = nelems - used;
 614
 615         /* Step 4: Create the mappings. */
 616         if (strbuf->strbuf_enabled)
 617                 iopte_protection = IOPTE_STREAMING(ctx);
 618         else
 619                 iopte_protection = IOPTE_CONSISTENT(ctx);
 620         if (direction != DMA_TO_DEVICE)
 621                 iopte_protection |= IOPTE_WRITE;
 622
 623         fill_sg(base, sglist, used, nelems, iopte_protection);
 624
 625 #ifdef VERIFY_SG
 626         verify_sglist(sglist, nelems, base, npages);
 627 #endif
 628
 629         return used;
 630
 631 bad:
 632         iommu_free_ctx(iommu, ctx);
 633 bad_no_ctx:
 634         if (printk_ratelimit())
 635                 WARN_ON(1);
 636         return 0;
 637 }
 638
 639 static void dma_4u_unmap_sg(struct device *dev, struct scatterlist *sglist,
 640                             int nelems, enum dma_data_direction direction)
 641 {
 642         struct iommu *iommu;
 643         struct strbuf *strbuf;
 644         iopte_t *base;
 645         unsigned long flags, ctx, i, npages;
 646         struct scatterlist *sg, *sgprv;
 647         u32 bus_addr;
 648
 649         if (unlikely(direction == DMA_NONE)) {
 650                 if (printk_ratelimit())
 651                         WARN_ON(1);
 652         }
 653
 654         iommu = dev->archdata.iommu;
 655         strbuf = dev->archdata.stc;
 656
 657         bus_addr = sglist->dma_address & IO_PAGE_MASK;
 658
 659         sgprv = NULL;
 660         for_each_sg(sglist, sg, nelems, i) {
 661                 if (sg->dma_length == 0)
 662                         break;
 663                 sgprv = sg;
 664         }
 665
 666         npages = (IO_PAGE_ALIGN(sgprv->dma_address + sgprv->dma_length) -
 667                   bus_addr) >> IO_PAGE_SHIFT;
 668
 669         base = iommu->page_table +
 670                 ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
 671
 672         spin_lock_irqsave(&iommu->lock, flags);
 673
 674         /* Record the context, if any. */
 675         ctx = 0;
 676         if (iommu->iommu_ctxflush)
 677                 ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
 678
 679         /* Step 1: Kick data out of streaming buffers if necessary. */
 680         if (strbuf->strbuf_enabled)
 681                 strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
 682
 683         /* Step 2: Clear out the TSB entries. */
 684         for (i = 0; i < npages; i++)
 685                 iopte_make_dummy(iommu, base + i);
 686
 687         free_npages(iommu, bus_addr - iommu->page_table_map_base, npages);
 688
 689         iommu_free_ctx(iommu, ctx);
 690
 691         spin_unlock_irqrestore(&iommu->lock, flags);
 692 }
 693
 694 static void dma_4u_sync_single_for_cpu(struct device *dev,
 695                                        dma_addr_t bus_addr, size_t sz,
 696                                        enum dma_data_direction direction)
 697 {
 698         struct iommu *iommu;
 699         struct strbuf *strbuf;
 700         unsigned long flags, ctx, npages;
 701
 702         iommu = dev->archdata.iommu;
 703         strbuf = dev->archdata.stc;
 704
 705         if (!strbuf->strbuf_enabled)
 706                 return;
 707
 708         spin_lock_irqsave(&iommu->lock, flags);
 709
 710         npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
 711         npages >>= IO_PAGE_SHIFT;
 712         bus_addr &= IO_PAGE_MASK;
 713
 714         /* Step 1: Record the context, if any. */
 715         ctx = 0;
 716         if (iommu->iommu_ctxflush &&
 717             strbuf->strbuf_ctxflush) {
 718                 iopte_t *iopte;
 719
 720                 iopte = iommu->page_table +
 721                         ((bus_addr - iommu->page_table_map_base)>>IO_PAGE_SHIFT);
 722                 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
 723         }
 724
 725         /* Step 2: Kick data out of streaming buffers. */
 726         strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
 727
 728         spin_unlock_irqrestore(&iommu->lock, flags);
 729 }
 730
 731 static void dma_4u_sync_sg_for_cpu(struct device *dev,
 732                                    struct scatterlist *sglist, int nelems,
 733                                    enum dma_data_direction direction)
 734 {
 735         struct iommu *iommu;
 736         struct strbuf *strbuf;
 737         unsigned long flags, ctx, npages, i;
 738         struct scatterlist *sg, *sgprv;
 739         u32 bus_addr;
 740
 741         iommu = dev->archdata.iommu;
 742         strbuf = dev->archdata.stc;
 743
 744         if (!strbuf->strbuf_enabled)
 745                 return;
 746
 747         spin_lock_irqsave(&iommu->lock, flags);
 748
 749         /* Step 1: Record the context, if any. */
 750         ctx = 0;
 751         if (iommu->iommu_ctxflush &&
 752             strbuf->strbuf_ctxflush) {
 753                 iopte_t *iopte;
 754
 755                 iopte = iommu->page_table +
 756                         ((sglist[0].dma_address - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
 757                 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
 758         }
 759
 760         /* Step 2: Kick data out of streaming buffers. */
 761         bus_addr = sglist[0].dma_address & IO_PAGE_MASK;
 762         sgprv = NULL;
 763         for_each_sg(sglist, sg, nelems, i) {
 764                 if (sg->dma_length == 0)
 765                         break;
 766                 sgprv = sg;
 767         }
 768
 769         npages = (IO_PAGE_ALIGN(sgprv->dma_address + sgprv->dma_length)
 770                   - bus_addr) >> IO_PAGE_SHIFT;
 771         strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
 772
 773         spin_unlock_irqrestore(&iommu->lock, flags);
 774 }
 775
 776 const struct dma_ops sun4u_dma_ops = {
 777         .alloc_coherent         = dma_4u_alloc_coherent,
 778         .free_coherent          = dma_4u_free_coherent,
 779         .map_single             = dma_4u_map_single,
 780         .unmap_single           = dma_4u_unmap_single,
 781         .map_sg                 = dma_4u_map_sg,
 782         .unmap_sg               = dma_4u_unmap_sg,
 783         .sync_single_for_cpu    = dma_4u_sync_single_for_cpu,
 784         .sync_sg_for_cpu        = dma_4u_sync_sg_for_cpu,
 785 };
 786
 787 const struct dma_ops *dma_ops = &sun4u_dma_ops;
 788 EXPORT_SYMBOL(dma_ops);
 789
 790 int dma_supported(struct device *dev, u64 device_mask)
 791 {
 792         struct iommu *iommu = dev->archdata.iommu;
 793         u64 dma_addr_mask = iommu->dma_addr_mask;
 794
 795         if (device_mask >= (1UL << 32UL))
 796                 return 0;
 797
 798         if ((device_mask & dma_addr_mask) == dma_addr_mask)
 799                 return 1;
 800
 801 #ifdef CONFIG_PCI
 802         if (dev->bus == &pci_bus_type)
 803                 return pci_dma_supported(to_pci_dev(dev), device_mask);
 804 #endif
 805
 806         return 0;
 807 }
 808 EXPORT_SYMBOL(dma_supported);
 809
 810 int dma_set_mask(struct device *dev, u64 dma_mask)
 811 {
 812 #ifdef CONFIG_PCI
 813         if (dev->bus == &pci_bus_type)
 814                 return pci_set_dma_mask(to_pci_dev(dev), dma_mask);
 815 #endif
 816         return -EINVAL;
 817 }
 818 EXPORT_SYMBOL(dma_set_mask);