1 /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
2 * irq.c: UltraSparc IRQ handling/init/registry.
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
9 #include <linux/config.h>
10 #include <linux/module.h>
11 #include <linux/sched.h>
12 #include <linux/ptrace.h>
13 #include <linux/errno.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/signal.h>
17 #include <linux/interrupt.h>
18 #include <linux/slab.h>
19 #include <linux/random.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/proc_fs.h>
23 #include <linux/seq_file.h>
25 #include <asm/ptrace.h>
26 #include <asm/processor.h>
27 #include <asm/atomic.h>
28 #include <asm/system.h>
32 #include <asm/iommu.h>
34 #include <asm/oplib.h>
35 #include <asm/timer.h>
37 #include <asm/starfire.h>
38 #include <asm/uaccess.h>
39 #include <asm/cache.h>
40 #include <asm/cpudata.h>
41 #include <asm/auxio.h>
44 static void distribute_irqs(void);
47 /* UPA nodes send interrupt packet to UltraSparc with first data reg
48 * value low 5 (7 on Starfire) bits holding the IRQ identifier being
49 * delivered. We must translate this into a non-vector IRQ so we can
50 * set the softint on this cpu.
52 * To make processing these packets efficient and race free we use
53 * an array of irq buckets below. The interrupt vector handler in
54 * entry.S feeds incoming packets into per-cpu pil-indexed lists.
55 * The IVEC handler does not need to act atomically, the PIL dispatch
56 * code uses CAS to get an atomic snapshot of the list and clear it
60 struct ino_bucket ivector_table
[NUM_IVECS
] __attribute__ ((aligned (SMP_CACHE_BYTES
)));
62 /* This has to be in the main kernel image, it cannot be
63 * turned into per-cpu data. The reason is that the main
64 * kernel image is locked into the TLB and this structure
65 * is accessed from the vectored interrupt trap handler. If
66 * access to this structure takes a TLB miss it could cause
67 * the 5-level sparc v9 trap stack to overflow.
69 struct irq_work_struct
{
70 unsigned int irq_worklists
[16];
72 struct irq_work_struct __irq_work
[NR_CPUS
];
73 #define irq_work(__cpu, __pil) &(__irq_work[(__cpu)].irq_worklists[(__pil)])
75 static struct irqaction
*irq_action
[NR_IRQS
+1];
77 /* This only synchronizes entities which modify IRQ handler
78 * state and some selected user-level spots that want to
79 * read things in the table. IRQ handler processing orders
80 * its' accesses such that no locking is needed.
82 static DEFINE_SPINLOCK(irq_action_lock
);
84 static void register_irq_proc (unsigned int irq
);
87 * Upper 2b of irqaction->flags holds the ino.
88 * irqaction->mask holds the smp affinity information.
90 #define put_ino_in_irqaction(action, irq) \
91 action->flags &= 0xffffffffffffUL; \
92 if (__bucket(irq) == &pil0_dummy_bucket) \
93 action->flags |= 0xdeadUL << 48; \
95 action->flags |= __irq_ino(irq) << 48;
96 #define get_ino_in_irqaction(action) (action->flags >> 48)
98 #define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff)
99 #define get_smpaff_in_irqaction(action) ((action)->mask)
101 int show_interrupts(struct seq_file
*p
, void *v
)
104 int i
= *(loff_t
*) v
;
105 struct irqaction
*action
;
110 spin_lock_irqsave(&irq_action_lock
, flags
);
112 if (!(action
= *(i
+ irq_action
)))
114 seq_printf(p
, "%3d: ", i
);
116 seq_printf(p
, "%10u ", kstat_irqs(i
));
118 for (j
= 0; j
< NR_CPUS
; j
++) {
121 seq_printf(p
, "%10u ",
122 kstat_cpu(j
).irqs
[i
]);
125 seq_printf(p
, " %s:%lx", action
->name
,
126 get_ino_in_irqaction(action
));
127 for (action
= action
->next
; action
; action
= action
->next
) {
128 seq_printf(p
, ", %s:%lx", action
->name
,
129 get_ino_in_irqaction(action
));
134 spin_unlock_irqrestore(&irq_action_lock
, flags
);
139 /* Now these are always passed a true fully specified sun4u INO. */
140 void enable_irq(unsigned int irq
)
142 struct ino_bucket
*bucket
= __bucket(irq
);
152 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
155 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
156 if ((ver
>> 32) == 0x003e0016) {
157 /* We set it to our JBUS ID. */
158 __asm__
__volatile__("ldxa [%%g0] %1, %0"
160 : "i" (ASI_JBUS_CONFIG
));
161 tid
= ((tid
& (0x1fUL
<<17)) << 9);
162 tid
&= IMAP_TID_JBUS
;
164 /* We set it to our Safari AID. */
165 __asm__
__volatile__("ldxa [%%g0] %1, %0"
167 : "i" (ASI_SAFARI_CONFIG
));
168 tid
= ((tid
& (0x3ffUL
<<17)) << 9);
169 tid
&= IMAP_AID_SAFARI
;
171 } else if (this_is_starfire
== 0) {
172 /* We set it to our UPA MID. */
173 __asm__
__volatile__("ldxa [%%g0] %1, %0"
175 : "i" (ASI_UPA_CONFIG
));
176 tid
= ((tid
& UPA_CONFIG_MID
) << 9);
179 tid
= (starfire_translate(imap
, smp_processor_id()) << 26);
183 /* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product
184 * of this SYSIO's preconfigured IGN in the SYSIO Control
185 * Register, the hardware just mirrors that value here.
186 * However for Graphics and UPA Slave devices the full
187 * IMAP_INR field can be set by the programmer here.
189 * Things like FFB can now be handled via the new IRQ mechanism.
191 upa_writel(tid
| IMAP_VALID
, imap
);
196 /* This now gets passed true ino's as well. */
197 void disable_irq(unsigned int irq
)
199 struct ino_bucket
*bucket
= __bucket(irq
);
206 /* NOTE: We do not want to futz with the IRQ clear registers
207 * and move the state to IDLE, the SCSI code does call
208 * disable_irq() to assure atomicity in the queue cmd
209 * SCSI adapter driver code. Thus we'd lose interrupts.
211 tmp
= upa_readl(imap
);
213 upa_writel(tmp
, imap
);
217 /* The timer is the one "weird" interrupt which is generated by
218 * the CPU %tick register and not by some normal vectored interrupt
219 * source. To handle this special case, we use this dummy INO bucket.
221 static struct irq_desc pil0_dummy_desc
;
222 static struct ino_bucket pil0_dummy_bucket
= {
223 .irq_info
= &pil0_dummy_desc
,
226 static void build_irq_error(const char *msg
, unsigned int ino
, int pil
, int inofixup
,
227 unsigned long iclr
, unsigned long imap
,
228 struct ino_bucket
*bucket
)
230 prom_printf("IRQ: INO %04x (%d:%016lx:%016lx) --> "
231 "(%d:%d:%016lx:%016lx), halting...\n",
232 ino
, bucket
->pil
, bucket
->iclr
, bucket
->imap
,
233 pil
, inofixup
, iclr
, imap
);
237 unsigned int build_irq(int pil
, int inofixup
, unsigned long iclr
, unsigned long imap
)
239 struct ino_bucket
*bucket
;
243 if (iclr
!= 0UL || imap
!= 0UL) {
244 prom_printf("Invalid dummy bucket for PIL0 (%lx:%lx)\n",
248 return __irq(&pil0_dummy_bucket
);
251 /* RULE: Both must be specified in all other cases. */
252 if (iclr
== 0UL || imap
== 0UL) {
253 prom_printf("Invalid build_irq %d %d %016lx %016lx\n",
254 pil
, inofixup
, iclr
, imap
);
258 ino
= (upa_readl(imap
) & (IMAP_IGN
| IMAP_INO
)) + inofixup
;
259 if (ino
> NUM_IVECS
) {
260 prom_printf("Invalid INO %04x (%d:%d:%016lx:%016lx)\n",
261 ino
, pil
, inofixup
, iclr
, imap
);
265 bucket
= &ivector_table
[ino
];
266 if (bucket
->flags
& IBF_ACTIVE
)
267 build_irq_error("IRQ: Trying to build active INO bucket.\n",
268 ino
, pil
, inofixup
, iclr
, imap
, bucket
);
270 if (bucket
->irq_info
) {
271 if (bucket
->imap
!= imap
|| bucket
->iclr
!= iclr
)
272 build_irq_error("IRQ: Trying to reinit INO bucket.\n",
273 ino
, pil
, inofixup
, iclr
, imap
, bucket
);
278 bucket
->irq_info
= kmalloc(sizeof(struct irq_desc
), GFP_ATOMIC
);
279 if (!bucket
->irq_info
) {
280 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
283 memset(bucket
->irq_info
, 0, sizeof(struct irq_desc
));
285 /* Ok, looks good, set it up. Don't touch the irq_chain or
294 return __irq(bucket
);
297 static void atomic_bucket_insert(struct ino_bucket
*bucket
)
299 unsigned long pstate
;
302 __asm__
__volatile__("rdpr %%pstate, %0" : "=r" (pstate
));
303 __asm__
__volatile__("wrpr %0, %1, %%pstate"
304 : : "r" (pstate
), "i" (PSTATE_IE
));
305 ent
= irq_work(smp_processor_id(), bucket
->pil
);
306 bucket
->irq_chain
= *ent
;
307 *ent
= __irq(bucket
);
308 __asm__
__volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate
));
311 static int check_irq_sharing(int pil
, unsigned long irqflags
)
313 struct irqaction
*action
, *tmp
;
315 action
= *(irq_action
+ pil
);
317 if ((action
->flags
& SA_SHIRQ
) && (irqflags
& SA_SHIRQ
)) {
318 for (tmp
= action
; tmp
->next
; tmp
= tmp
->next
)
327 static void append_irq_action(int pil
, struct irqaction
*action
)
329 struct irqaction
**pp
= irq_action
+ pil
;
336 static struct irqaction
*get_action_slot(struct ino_bucket
*bucket
)
338 struct irq_desc
*desc
= bucket
->irq_info
;
342 if (bucket
->flags
& IBF_PCI
)
343 max_irq
= MAX_IRQ_DESC_ACTION
;
344 for (i
= 0; i
< max_irq
; i
++) {
345 struct irqaction
*p
= &desc
->action
[i
];
348 if (desc
->action_active_mask
& mask
)
351 desc
->action_active_mask
|= mask
;
357 int request_irq(unsigned int irq
, irqreturn_t (*handler
)(int, void *, struct pt_regs
*),
358 unsigned long irqflags
, const char *name
, void *dev_id
)
360 struct irqaction
*action
;
361 struct ino_bucket
*bucket
= __bucket(irq
);
365 if (unlikely(!handler
))
368 if (unlikely(!bucket
->irq_info
))
371 if ((bucket
!= &pil0_dummy_bucket
) && (irqflags
& SA_SAMPLE_RANDOM
)) {
373 * This function might sleep, we want to call it first,
374 * outside of the atomic block. In SA_STATIC_ALLOC case,
375 * random driver's kmalloc will fail, but it is safe.
376 * If already initialized, random driver will not reinit.
377 * Yes, this might clear the entropy pool if the wrong
378 * driver is attempted to be loaded, without actually
379 * installing a new handler, but is this really a problem,
380 * only the sysadmin is able to do this.
382 rand_initialize_irq(irq
);
385 spin_lock_irqsave(&irq_action_lock
, flags
);
387 if (check_irq_sharing(bucket
->pil
, irqflags
)) {
388 spin_unlock_irqrestore(&irq_action_lock
, flags
);
392 action
= get_action_slot(bucket
);
394 spin_unlock_irqrestore(&irq_action_lock
, flags
);
398 bucket
->flags
|= IBF_ACTIVE
;
400 if (bucket
!= &pil0_dummy_bucket
) {
401 pending
= bucket
->pending
;
406 action
->handler
= handler
;
407 action
->flags
= irqflags
;
410 action
->dev_id
= dev_id
;
411 put_ino_in_irqaction(action
, irq
);
412 put_smpaff_in_irqaction(action
, CPU_MASK_NONE
);
414 append_irq_action(bucket
->pil
, action
);
418 /* We ate the IVEC already, this makes sure it does not get lost. */
420 atomic_bucket_insert(bucket
);
421 set_softint(1 << bucket
->pil
);
424 spin_unlock_irqrestore(&irq_action_lock
, flags
);
426 if (bucket
!= &pil0_dummy_bucket
)
427 register_irq_proc(__irq_ino(irq
));
435 EXPORT_SYMBOL(request_irq
);
437 static struct irqaction
*unlink_irq_action(unsigned int irq
, void *dev_id
)
439 struct ino_bucket
*bucket
= __bucket(irq
);
440 struct irqaction
*action
, **pp
;
442 pp
= irq_action
+ bucket
->pil
;
444 if (unlikely(!action
))
447 if (unlikely(!action
->handler
)) {
448 printk("Freeing free IRQ %d\n", bucket
->pil
);
452 while (action
&& action
->dev_id
!= dev_id
) {
463 void free_irq(unsigned int irq
, void *dev_id
)
465 struct irqaction
*action
;
466 struct ino_bucket
*bucket
;
469 spin_lock_irqsave(&irq_action_lock
, flags
);
471 action
= unlink_irq_action(irq
, dev_id
);
473 spin_unlock_irqrestore(&irq_action_lock
, flags
);
475 if (unlikely(!action
))
478 synchronize_irq(irq
);
480 spin_lock_irqsave(&irq_action_lock
, flags
);
482 bucket
= __bucket(irq
);
483 if (bucket
!= &pil0_dummy_bucket
) {
484 struct irq_desc
*desc
= bucket
->irq_info
;
485 unsigned long imap
= bucket
->imap
;
488 for (i
= 0; i
< MAX_IRQ_DESC_ACTION
; i
++) {
489 struct irqaction
*p
= &desc
->action
[i
];
492 desc
->action_active_mask
&= ~(1 << i
);
497 if (!desc
->action_active_mask
) {
498 /* This unique interrupt source is now inactive. */
499 bucket
->flags
&= ~IBF_ACTIVE
;
501 /* See if any other buckets share this bucket's IMAP
502 * and are still active.
504 for (ent
= 0; ent
< NUM_IVECS
; ent
++) {
505 struct ino_bucket
*bp
= &ivector_table
[ent
];
508 (bp
->flags
& IBF_ACTIVE
) != 0)
512 /* Only disable when no other sub-irq levels of
513 * the same IMAP are active.
515 if (ent
== NUM_IVECS
)
520 spin_unlock_irqrestore(&irq_action_lock
, flags
);
523 EXPORT_SYMBOL(free_irq
);
526 void synchronize_irq(unsigned int irq
)
528 struct ino_bucket
*bucket
= __bucket(irq
);
531 /* The following is how I wish I could implement this.
532 * Unfortunately the ICLR registers are read-only, you can
533 * only write ICLR_foo values to them. To get the current
534 * IRQ status you would need to get at the IRQ diag registers
535 * in the PCI/SBUS controller and the layout of those vary
536 * from one controller to the next, sigh... -DaveM
538 unsigned long iclr
= bucket
->iclr
;
541 u32 tmp
= upa_readl(iclr
);
543 if (tmp
== ICLR_TRANSMIT
||
544 tmp
== ICLR_PENDING
) {
551 /* So we have to do this with a INPROGRESS bit just like x86. */
552 while (bucket
->flags
& IBF_INPROGRESS
)
556 #endif /* CONFIG_SMP */
558 static void process_bucket(int irq
, struct ino_bucket
*bp
, struct pt_regs
*regs
)
560 struct irq_desc
*desc
= bp
->irq_info
;
561 unsigned char flags
= bp
->flags
;
565 bp
->flags
|= IBF_INPROGRESS
;
567 if (unlikely(!(flags
& IBF_ACTIVE
))) {
572 if (desc
->pre_handler
)
573 desc
->pre_handler(bp
,
574 desc
->pre_handler_arg1
,
575 desc
->pre_handler_arg2
);
577 action_mask
= desc
->action_active_mask
;
579 for (i
= 0; i
< MAX_IRQ_DESC_ACTION
; i
++) {
580 struct irqaction
*p
= &desc
->action
[i
];
583 if (!(action_mask
& mask
))
586 action_mask
&= ~mask
;
588 if (p
->handler(__irq(bp
), p
->dev_id
, regs
) == IRQ_HANDLED
)
595 upa_writel(ICLR_IDLE
, bp
->iclr
);
596 /* Test and add entropy */
597 if (random
& SA_SAMPLE_RANDOM
)
598 add_interrupt_randomness(irq
);
601 bp
->flags
&= ~IBF_INPROGRESS
;
604 void handler_irq(int irq
, struct pt_regs
*regs
)
606 struct ino_bucket
*bp
;
607 int cpu
= smp_processor_id();
611 * Check for TICK_INT on level 14 softint.
614 unsigned long clr_mask
= 1 << irq
;
615 unsigned long tick_mask
= tick_ops
->softint_mask
;
617 if ((irq
== 14) && (get_softint() & tick_mask
)) {
619 clr_mask
= tick_mask
;
621 clear_softint(clr_mask
);
624 clear_softint(1 << irq
);
628 kstat_this_cpu
.irqs
[irq
]++;
633 __bucket(xchg32(irq_work(cpu
, irq
), 0)) :
636 bp
= __bucket(xchg32(irq_work(cpu
, irq
), 0));
639 struct ino_bucket
*nbp
= __bucket(bp
->irq_chain
);
642 process_bucket(irq
, bp
, regs
);
648 #ifdef CONFIG_BLK_DEV_FD
649 extern irqreturn_t
floppy_interrupt(int, void *, struct pt_regs
*);;
651 /* XXX No easy way to include asm/floppy.h XXX */
652 extern unsigned char *pdma_vaddr
;
653 extern unsigned long pdma_size
;
654 extern volatile int doing_pdma
;
655 extern unsigned long fdc_status
;
657 irqreturn_t
sparc_floppy_irq(int irq
, void *dev_cookie
, struct pt_regs
*regs
)
659 if (likely(doing_pdma
)) {
660 void __iomem
*stat
= (void __iomem
*) fdc_status
;
661 unsigned char *vaddr
= pdma_vaddr
;
662 unsigned long size
= pdma_size
;
667 if (unlikely(!(val
& 0x80))) {
672 if (unlikely(!(val
& 0x20))) {
680 *vaddr
++ = readb(stat
+ 1);
682 unsigned char data
= *vaddr
++;
685 writeb(data
, stat
+ 1);
693 /* Send Terminal Count pulse to floppy controller. */
694 val
= readb(auxio_register
);
695 val
|= AUXIO_AUX1_FTCNT
;
696 writeb(val
, auxio_register
);
697 val
&= ~AUXIO_AUX1_FTCNT
;
698 writeb(val
, auxio_register
);
704 return floppy_interrupt(irq
, dev_cookie
, regs
);
706 EXPORT_SYMBOL(sparc_floppy_irq
);
709 /* We really don't need these at all on the Sparc. We only have
710 * stubs here because they are exported to modules.
712 unsigned long probe_irq_on(void)
717 EXPORT_SYMBOL(probe_irq_on
);
719 int probe_irq_off(unsigned long mask
)
724 EXPORT_SYMBOL(probe_irq_off
);
727 static int retarget_one_irq(struct irqaction
*p
, int goal_cpu
)
729 struct ino_bucket
*bucket
= get_ino_in_irqaction(p
) + ivector_table
;
730 unsigned long imap
= bucket
->imap
;
733 while (!cpu_online(goal_cpu
)) {
734 if (++goal_cpu
>= NR_CPUS
)
738 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
739 tid
= goal_cpu
<< 26;
740 tid
&= IMAP_AID_SAFARI
;
741 } else if (this_is_starfire
== 0) {
742 tid
= goal_cpu
<< 26;
745 tid
= (starfire_translate(imap
, goal_cpu
) << 26);
748 upa_writel(tid
| IMAP_VALID
, imap
);
751 if (++goal_cpu
>= NR_CPUS
)
753 } while (!cpu_online(goal_cpu
));
758 /* Called from request_irq. */
759 static void distribute_irqs(void)
764 spin_lock_irqsave(&irq_action_lock
, flags
);
768 * Skip the timer at [0], and very rare error/power intrs at [15].
769 * Also level [12], it causes problems on Ex000 systems.
771 for (level
= 1; level
< NR_IRQS
; level
++) {
772 struct irqaction
*p
= irq_action
[level
];
778 cpu
= retarget_one_irq(p
, cpu
);
782 spin_unlock_irqrestore(&irq_action_lock
, flags
);
793 static struct sun5_timer
*prom_timers
;
794 static u64 prom_limit0
, prom_limit1
;
796 static void map_prom_timers(void)
798 unsigned int addr
[3];
801 /* PROM timer node hangs out in the top level of device siblings... */
802 tnode
= prom_finddevice("/counter-timer");
804 /* Assume if node is not present, PROM uses different tick mechanism
805 * which we should not care about.
807 if (tnode
== 0 || tnode
== -1) {
808 prom_timers
= (struct sun5_timer
*) 0;
812 /* If PROM is really using this, it must be mapped by him. */
813 err
= prom_getproperty(tnode
, "address", (char *)addr
, sizeof(addr
));
815 prom_printf("PROM does not have timer mapped, trying to continue.\n");
816 prom_timers
= (struct sun5_timer
*) 0;
819 prom_timers
= (struct sun5_timer
*) ((unsigned long)addr
[0]);
822 static void kill_prom_timer(void)
827 /* Save them away for later. */
828 prom_limit0
= prom_timers
->limit0
;
829 prom_limit1
= prom_timers
->limit1
;
831 /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
832 * We turn both off here just to be paranoid.
834 prom_timers
->limit0
= 0;
835 prom_timers
->limit1
= 0;
837 /* Wheee, eat the interrupt packet too... */
838 __asm__
__volatile__(
840 " ldxa [%%g0] %0, %%g1\n"
841 " ldxa [%%g2] %1, %%g1\n"
842 " stxa %%g0, [%%g0] %0\n"
845 : "i" (ASI_INTR_RECEIVE
), "i" (ASI_INTR_R
)
849 void init_irqwork_curcpu(void)
851 register struct irq_work_struct
*workp
asm("o2");
852 register unsigned long tmp
asm("o3");
853 int cpu
= hard_smp_processor_id();
855 memset(__irq_work
+ cpu
, 0, sizeof(*workp
));
857 /* Make sure we are called with PSTATE_IE disabled. */
858 __asm__
__volatile__("rdpr %%pstate, %0\n\t"
860 if (tmp
& PSTATE_IE
) {
861 prom_printf("BUG: init_irqwork_curcpu() called with "
862 "PSTATE_IE enabled, bailing.\n");
863 __asm__
__volatile__("mov %%i7, %0\n\t"
865 prom_printf("BUG: Called from %lx\n", tmp
);
869 /* Set interrupt globals. */
870 workp
= &__irq_work
[cpu
];
871 __asm__
__volatile__(
872 "rdpr %%pstate, %0\n\t"
873 "wrpr %0, %1, %%pstate\n\t"
875 "wrpr %0, 0x0, %%pstate\n\t"
877 : "i" (PSTATE_IG
), "r" (workp
));
880 /* Only invoked on boot processor. */
881 void __init
init_IRQ(void)
885 memset(&ivector_table
[0], 0, sizeof(ivector_table
));
887 /* We need to clear any IRQ's pending in the soft interrupt
888 * registers, a spurious one could be left around from the
889 * PROM timer which we just disabled.
891 clear_softint(get_softint());
893 /* Now that ivector table is initialized, it is safe
894 * to receive IRQ vector traps. We will normally take
895 * one or two right now, in case some device PROM used
896 * to boot us wants to speak to us. We just ignore them.
898 __asm__
__volatile__("rdpr %%pstate, %%g1\n\t"
899 "or %%g1, %0, %%g1\n\t"
900 "wrpr %%g1, 0x0, %%pstate"
906 static struct proc_dir_entry
* root_irq_dir
;
907 static struct proc_dir_entry
* irq_dir
[NUM_IVECS
];
911 static int irq_affinity_read_proc (char *page
, char **start
, off_t off
,
912 int count
, int *eof
, void *data
)
914 struct ino_bucket
*bp
= ivector_table
+ (long)data
;
915 struct irq_desc
*desc
= bp
->irq_info
;
916 struct irqaction
*ap
= desc
->action
;
920 mask
= get_smpaff_in_irqaction(ap
);
921 if (cpus_empty(mask
))
922 mask
= cpu_online_map
;
924 len
= cpumask_scnprintf(page
, count
, mask
);
927 len
+= sprintf(page
+ len
, "\n");
931 static inline void set_intr_affinity(int irq
, cpumask_t hw_aff
)
933 struct ino_bucket
*bp
= ivector_table
+ irq
;
934 struct irq_desc
*desc
= bp
->irq_info
;
935 struct irqaction
*ap
= desc
->action
;
937 /* Users specify affinity in terms of hw cpu ids.
938 * As soon as we do this, handler_irq() might see and take action.
940 put_smpaff_in_irqaction(ap
, hw_aff
);
942 /* Migration is simply done by the next cpu to service this
947 static int irq_affinity_write_proc (struct file
*file
, const char __user
*buffer
,
948 unsigned long count
, void *data
)
950 int irq
= (long) data
, full_count
= count
, err
;
953 err
= cpumask_parse(buffer
, count
, new_value
);
956 * Do not allow disabling IRQs completely - it's a too easy
957 * way to make the system unusable accidentally :-) At least
958 * one online CPU still has to be targeted.
960 cpus_and(new_value
, new_value
, cpu_online_map
);
961 if (cpus_empty(new_value
))
964 set_intr_affinity(irq
, new_value
);
971 #define MAX_NAMELEN 10
973 static void register_irq_proc (unsigned int irq
)
975 char name
[MAX_NAMELEN
];
977 if (!root_irq_dir
|| irq_dir
[irq
])
980 memset(name
, 0, MAX_NAMELEN
);
981 sprintf(name
, "%x", irq
);
983 /* create /proc/irq/1234 */
984 irq_dir
[irq
] = proc_mkdir(name
, root_irq_dir
);
987 /* XXX SMP affinity not supported on starfire yet. */
988 if (this_is_starfire
== 0) {
989 struct proc_dir_entry
*entry
;
991 /* create /proc/irq/1234/smp_affinity */
992 entry
= create_proc_entry("smp_affinity", 0600, irq_dir
[irq
]);
996 entry
->data
= (void *)(long)irq
;
997 entry
->read_proc
= irq_affinity_read_proc
;
998 entry
->write_proc
= irq_affinity_write_proc
;
1004 void init_irq_proc (void)
1006 /* create /proc/irq */
1007 root_irq_dir
= proc_mkdir("irq", NULL
);