arch/sparc64/kernel/pci.c

   1 /* pci.c: UltraSparc PCI controller support.
   2  *
   3  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
   4  * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
   5  * Copyright (C) 1999 Jakub Jelinek   (jj@ultra.linux.cz)
   6  *
   7  * OF tree based PCI bus probing taken from the PowerPC port
   8  * with minor modifications, see there for credits.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/string.h>
  14 #include <linux/sched.h>
  15 #include <linux/capability.h>
  16 #include <linux/errno.h>
  17 #include <linux/pci.h>
  18 #include <linux/msi.h>
  19 #include <linux/irq.h>
  20 #include <linux/init.h>
  21
  22 #include <asm/uaccess.h>
  23 #include <asm/pgtable.h>
  24 #include <asm/irq.h>
  25 #include <asm/ebus.h>
  26 #include <asm/isa.h>
  27 #include <asm/prom.h>
  28 #include <asm/apb.h>
  29
  30 #include "pci_impl.h"
  31
  32 unsigned long pci_memspace_mask = 0xffffffffUL;
  33
  34 #ifndef CONFIG_PCI
  35 /* A "nop" PCI implementation. */
  36 asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
  37                                   unsigned long off, unsigned long len,
  38                                   unsigned char *buf)
  39 {
  40         return 0;
  41 }
  42 asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
  43                                    unsigned long off, unsigned long len,
  44                                    unsigned char *buf)
  45 {
  46         return 0;
  47 }
  48 #else
  49
  50 /* List of all PCI controllers found in the system. */
  51 struct pci_pbm_info *pci_pbm_root = NULL;
  52
  53 /* Each PBM found gets a unique index. */
  54 int pci_num_pbms = 0;
  55
  56 volatile int pci_poke_in_progress;
  57 volatile int pci_poke_cpu = -1;
  58 volatile int pci_poke_faulted;
  59
  60 static DEFINE_SPINLOCK(pci_poke_lock);
  61
  62 void pci_config_read8(u8 *addr, u8 *ret)
  63 {
  64         unsigned long flags;
  65         u8 byte;
  66
  67         spin_lock_irqsave(&pci_poke_lock, flags);
  68         pci_poke_cpu = smp_processor_id();
  69         pci_poke_in_progress = 1;
  70         pci_poke_faulted = 0;
  71         __asm__ __volatile__("membar #Sync\n\t"
  72                              "lduba [%1] %2, %0\n\t"
  73                              "membar #Sync"
  74                              : "=r" (byte)
  75                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  76                              : "memory");
  77         pci_poke_in_progress = 0;
  78         pci_poke_cpu = -1;
  79         if (!pci_poke_faulted)
  80                 *ret = byte;
  81         spin_unlock_irqrestore(&pci_poke_lock, flags);
  82 }
  83
  84 void pci_config_read16(u16 *addr, u16 *ret)
  85 {
  86         unsigned long flags;
  87         u16 word;
  88
  89         spin_lock_irqsave(&pci_poke_lock, flags);
  90         pci_poke_cpu = smp_processor_id();
  91         pci_poke_in_progress = 1;
  92         pci_poke_faulted = 0;
  93         __asm__ __volatile__("membar #Sync\n\t"
  94                              "lduha [%1] %2, %0\n\t"
  95                              "membar #Sync"
  96                              : "=r" (word)
  97                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
  98                              : "memory");
  99         pci_poke_in_progress = 0;
 100         pci_poke_cpu = -1;
 101         if (!pci_poke_faulted)
 102                 *ret = word;
 103         spin_unlock_irqrestore(&pci_poke_lock, flags);
 104 }
 105
 106 void pci_config_read32(u32 *addr, u32 *ret)
 107 {
 108         unsigned long flags;
 109         u32 dword;
 110
 111         spin_lock_irqsave(&pci_poke_lock, flags);
 112         pci_poke_cpu = smp_processor_id();
 113         pci_poke_in_progress = 1;
 114         pci_poke_faulted = 0;
 115         __asm__ __volatile__("membar #Sync\n\t"
 116                              "lduwa [%1] %2, %0\n\t"
 117                              "membar #Sync"
 118                              : "=r" (dword)
 119                              : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 120                              : "memory");
 121         pci_poke_in_progress = 0;
 122         pci_poke_cpu = -1;
 123         if (!pci_poke_faulted)
 124                 *ret = dword;
 125         spin_unlock_irqrestore(&pci_poke_lock, flags);
 126 }
 127
 128 void pci_config_write8(u8 *addr, u8 val)
 129 {
 130         unsigned long flags;
 131
 132         spin_lock_irqsave(&pci_poke_lock, flags);
 133         pci_poke_cpu = smp_processor_id();
 134         pci_poke_in_progress = 1;
 135         pci_poke_faulted = 0;
 136         __asm__ __volatile__("membar #Sync\n\t"
 137                              "stba %0, [%1] %2\n\t"
 138                              "membar #Sync"
 139                              : /* no outputs */
 140                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 141                              : "memory");
 142         pci_poke_in_progress = 0;
 143         pci_poke_cpu = -1;
 144         spin_unlock_irqrestore(&pci_poke_lock, flags);
 145 }
 146
 147 void pci_config_write16(u16 *addr, u16 val)
 148 {
 149         unsigned long flags;
 150
 151         spin_lock_irqsave(&pci_poke_lock, flags);
 152         pci_poke_cpu = smp_processor_id();
 153         pci_poke_in_progress = 1;
 154         pci_poke_faulted = 0;
 155         __asm__ __volatile__("membar #Sync\n\t"
 156                              "stha %0, [%1] %2\n\t"
 157                              "membar #Sync"
 158                              : /* no outputs */
 159                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 160                              : "memory");
 161         pci_poke_in_progress = 0;
 162         pci_poke_cpu = -1;
 163         spin_unlock_irqrestore(&pci_poke_lock, flags);
 164 }
 165
 166 void pci_config_write32(u32 *addr, u32 val)
 167 {
 168         unsigned long flags;
 169
 170         spin_lock_irqsave(&pci_poke_lock, flags);
 171         pci_poke_cpu = smp_processor_id();
 172         pci_poke_in_progress = 1;
 173         pci_poke_faulted = 0;
 174         __asm__ __volatile__("membar #Sync\n\t"
 175                              "stwa %0, [%1] %2\n\t"
 176                              "membar #Sync"
 177                              : /* no outputs */
 178                              : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
 179                              : "memory");
 180         pci_poke_in_progress = 0;
 181         pci_poke_cpu = -1;
 182         spin_unlock_irqrestore(&pci_poke_lock, flags);
 183 }
 184
 185 /* Probe for all PCI controllers in the system. */
 186 extern void sabre_init(struct device_node *, const char *);
 187 extern void psycho_init(struct device_node *, const char *);
 188 extern void schizo_init(struct device_node *, const char *);
 189 extern void schizo_plus_init(struct device_node *, const char *);
 190 extern void tomatillo_init(struct device_node *, const char *);
 191 extern void sun4v_pci_init(struct device_node *, const char *);
 192 extern void fire_pci_init(struct device_node *, const char *);
 193
 194 static struct {
 195         char *model_name;
 196         void (*init)(struct device_node *, const char *);
 197 } pci_controller_table[] __initdata = {
 198         { "SUNW,sabre", sabre_init },
 199         { "pci108e,a000", sabre_init },
 200         { "pci108e,a001", sabre_init },
 201         { "SUNW,psycho", psycho_init },
 202         { "pci108e,8000", psycho_init },
 203         { "SUNW,schizo", schizo_init },
 204         { "pci108e,8001", schizo_init },
 205         { "SUNW,schizo+", schizo_plus_init },
 206         { "pci108e,8002", schizo_plus_init },
 207         { "SUNW,tomatillo", tomatillo_init },
 208         { "pci108e,a801", tomatillo_init },
 209         { "SUNW,sun4v-pci", sun4v_pci_init },
 210         { "pciex108e,80f0", fire_pci_init },
 211 };
 212 #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
 213                                   sizeof(pci_controller_table[0]))
 214
 215 static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp)
 216 {
 217         int i;
 218
 219         for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
 220                 if (!strncmp(model_name,
 221                              pci_controller_table[i].model_name,
 222                              namelen)) {
 223                         pci_controller_table[i].init(dp, model_name);
 224                         return 1;
 225                 }
 226         }
 227
 228         return 0;
 229 }
 230
 231 static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp)
 232 {
 233         int i;
 234
 235         for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
 236                 if (!strncmp(model_name,
 237                              pci_controller_table[i].model_name,
 238                              namelen)) {
 239                         return 1;
 240                 }
 241         }
 242         return 0;
 243 }
 244
 245 static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *))
 246 {
 247         struct device_node *dp;
 248         int count = 0;
 249
 250         for_each_node_by_name(dp, "pci") {
 251                 struct property *prop;
 252                 int len;
 253
 254                 prop = of_find_property(dp, "model", &len);
 255                 if (!prop)
 256                         prop = of_find_property(dp, "compatible", &len);
 257
 258                 if (prop) {
 259                         const char *model = prop->value;
 260                         int item_len = 0;
 261
 262                         /* Our value may be a multi-valued string in the
 263                          * case of some compatible properties. For sanity,
 264                          * only try the first one.
 265                          */
 266                         while (model[item_len] && len) {
 267                                 len--;
 268                                 item_len++;
 269                         }
 270
 271                         if (handler(model, item_len, dp))
 272                                 count++;
 273                 }
 274         }
 275
 276         return count;
 277 }
 278
 279
 280 /* Is there some PCI controller in the system?  */
 281 int __init pcic_present(void)
 282 {
 283         return pci_controller_scan(pci_is_controller);
 284 }
 285
 286 const struct pci_iommu_ops *pci_iommu_ops;
 287 EXPORT_SYMBOL(pci_iommu_ops);
 288
 289 extern const struct pci_iommu_ops pci_sun4u_iommu_ops,
 290         pci_sun4v_iommu_ops;
 291
 292 /* Find each controller in the system, attach and initialize
 293  * software state structure for each and link into the
 294  * pci_pbm_root.  Setup the controller enough such
 295  * that bus scanning can be done.
 296  */
 297 static void __init pci_controller_probe(void)
 298 {
 299         if (tlb_type == hypervisor)
 300                 pci_iommu_ops = &pci_sun4v_iommu_ops;
 301         else
 302                 pci_iommu_ops = &pci_sun4u_iommu_ops;
 303
 304         printk("PCI: Probing for controllers.\n");
 305
 306         pci_controller_scan(pci_controller_init);
 307 }
 308
 309 static int ofpci_verbose;
 310
 311 static int __init ofpci_debug(char *str)
 312 {
 313         int val = 0;
 314
 315         get_option(&str, &val);
 316         if (val)
 317                 ofpci_verbose = 1;
 318         return 1;
 319 }
 320
 321 __setup("ofpci_debug=", ofpci_debug);
 322
 323 static unsigned long pci_parse_of_flags(u32 addr0)
 324 {
 325         unsigned long flags = 0;
 326
 327         if (addr0 & 0x02000000) {
 328                 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
 329                 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
 330                 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
 331                 if (addr0 & 0x40000000)
 332                         flags |= IORESOURCE_PREFETCH
 333                                  | PCI_BASE_ADDRESS_MEM_PREFETCH;
 334         } else if (addr0 & 0x01000000)
 335                 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
 336         return flags;
 337 }
 338
 339 /* The of_device layer has translated all of the assigned-address properties
 340  * into physical address resources, we only have to figure out the register
 341  * mapping.
 342  */
 343 static void pci_parse_of_addrs(struct of_device *op,
 344                                struct device_node *node,
 345                                struct pci_dev *dev)
 346 {
 347         struct resource *op_res;
 348         const u32 *addrs;
 349         int proplen;
 350
 351         addrs = of_get_property(node, "assigned-addresses", &proplen);
 352         if (!addrs)
 353                 return;
 354         if (ofpci_verbose)
 355                 printk("    parse addresses (%d bytes) @ %p\n",
 356                        proplen, addrs);
 357         op_res = &op->resource[0];
 358         for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
 359                 struct resource *res;
 360                 unsigned long flags;
 361                 int i;
 362
 363                 flags = pci_parse_of_flags(addrs[0]);
 364                 if (!flags)
 365                         continue;
 366                 i = addrs[0] & 0xff;
 367                 if (ofpci_verbose)
 368                         printk("  start: %lx, end: %lx, i: %x\n",
 369                                op_res->start, op_res->end, i);
 370
 371                 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
 372                         res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
 373                 } else if (i == dev->rom_base_reg) {
 374                         res = &dev->resource[PCI_ROM_RESOURCE];
 375                         flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
 376                 } else {
 377                         printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
 378                         continue;
 379                 }
 380                 res->start = op_res->start;
 381                 res->end = op_res->end;
 382                 res->flags = flags;
 383                 res->name = pci_name(dev);
 384         }
 385 }
 386
 387 struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
 388                                   struct device_node *node,
 389                                   struct pci_bus *bus, int devfn,
 390                                   int host_controller)
 391 {
 392         struct dev_archdata *sd;
 393         struct pci_dev *dev;
 394         const char *type;
 395         u32 class;
 396
 397         dev = alloc_pci_dev();
 398         if (!dev)
 399                 return NULL;
 400
 401         sd = &dev->dev.archdata;
 402         sd->iommu = pbm->iommu;
 403         sd->stc = &pbm->stc;
 404         sd->host_controller = pbm;
 405         sd->prom_node = node;
 406         sd->op = of_find_device_by_node(node);
 407         sd->msi_num = 0xffffffff;
 408
 409         type = of_get_property(node, "device_type", NULL);
 410         if (type == NULL)
 411                 type = "";
 412
 413         if (ofpci_verbose)
 414                 printk("    create device, devfn: %x, type: %s\n",
 415                        devfn, type);
 416
 417         dev->bus = bus;
 418         dev->sysdata = node;
 419         dev->dev.parent = bus->bridge;
 420         dev->dev.bus = &pci_bus_type;
 421         dev->devfn = devfn;
 422         dev->multifunction = 0;         /* maybe a lie? */
 423
 424         if (host_controller) {
 425                 dev->vendor = 0x108e;
 426                 dev->device = 0x8000;
 427                 dev->subsystem_vendor = 0x0000;
 428                 dev->subsystem_device = 0x0000;
 429                 dev->cfg_size = 256;
 430                 dev->class = PCI_CLASS_BRIDGE_HOST << 8;
 431                 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
 432                         0x00, PCI_SLOT(devfn), PCI_FUNC(devfn));
 433         } else {
 434                 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
 435                 dev->device = of_getintprop_default(node, "device-id", 0xffff);
 436                 dev->subsystem_vendor =
 437                         of_getintprop_default(node, "subsystem-vendor-id", 0);
 438                 dev->subsystem_device =
 439                         of_getintprop_default(node, "subsystem-id", 0);
 440
 441                 dev->cfg_size = pci_cfg_space_size(dev);
 442
 443                 /* We can't actually use the firmware value, we have
 444                  * to read what is in the register right now.  One
 445                  * reason is that in the case of IDE interfaces the
 446                  * firmware can sample the value before the the IDE
 447                  * interface is programmed into native mode.
 448                  */
 449                 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
 450                 dev->class = class >> 8;
 451                 dev->revision = class & 0xff;
 452
 453                 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
 454                         dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
 455         }
 456         if (ofpci_verbose)
 457                 printk("    class: 0x%x device name: %s\n",
 458                        dev->class, pci_name(dev));
 459
 460         /* I have seen IDE devices which will not respond to
 461          * the bmdma simplex check reads if bus mastering is
 462          * disabled.
 463          */
 464         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
 465                 pci_set_master(dev);
 466
 467         dev->current_state = 4;         /* unknown power state */
 468         dev->error_state = pci_channel_io_normal;
 469
 470         if (host_controller) {
 471                 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
 472                 dev->rom_base_reg = PCI_ROM_ADDRESS1;
 473                 dev->irq = PCI_IRQ_NONE;
 474         } else {
 475                 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
 476                         /* a PCI-PCI bridge */
 477                         dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
 478                         dev->rom_base_reg = PCI_ROM_ADDRESS1;
 479                 } else if (!strcmp(type, "cardbus")) {
 480                         dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
 481                 } else {
 482                         dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
 483                         dev->rom_base_reg = PCI_ROM_ADDRESS;
 484
 485                         dev->irq = sd->op->irqs[0];
 486                         if (dev->irq == 0xffffffff)
 487                                 dev->irq = PCI_IRQ_NONE;
 488                 }
 489         }
 490         pci_parse_of_addrs(sd->op, node, dev);
 491
 492         if (ofpci_verbose)
 493                 printk("    adding to system ...\n");
 494
 495         pci_device_add(dev, bus);
 496
 497         return dev;
 498 }
 499
 500 static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
 501 {
 502         u32 idx, first, last;
 503
 504         first = 8;
 505         last = 0;
 506         for (idx = 0; idx < 8; idx++) {
 507                 if ((map & (1 << idx)) != 0) {
 508                         if (first > idx)
 509                                 first = idx;
 510                         if (last < idx)
 511                                 last = idx;
 512                 }
 513         }
 514
 515         *first_p = first;
 516         *last_p = last;
 517 }
 518
 519 static void pci_resource_adjust(struct resource *res,
 520                                 struct resource *root)
 521 {
 522         res->start += root->start;
 523         res->end += root->start;
 524 }
 525
 526 /* For PCI bus devices which lack a 'ranges' property we interrogate
 527  * the config space values to set the resources, just like the generic
 528  * Linux PCI probing code does.
 529  */
 530 static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
 531                                           struct pci_bus *bus,
 532                                           struct pci_pbm_info *pbm)
 533 {
 534         struct resource *res;
 535         u8 io_base_lo, io_limit_lo;
 536         u16 mem_base_lo, mem_limit_lo;
 537         unsigned long base, limit;
 538
 539         pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
 540         pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
 541         base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
 542         limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
 543
 544         if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
 545                 u16 io_base_hi, io_limit_hi;
 546
 547                 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
 548                 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
 549                 base |= (io_base_hi << 16);
 550                 limit |= (io_limit_hi << 16);
 551         }
 552
 553         res = bus->resource[0];
 554         if (base <= limit) {
 555                 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
 556                 if (!res->start)
 557                         res->start = base;
 558                 if (!res->end)
 559                         res->end = limit + 0xfff;
 560                 pci_resource_adjust(res, &pbm->io_space);
 561         }
 562
 563         pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
 564         pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
 565         base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
 566         limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
 567
 568         res = bus->resource[1];
 569         if (base <= limit) {
 570                 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
 571                               IORESOURCE_MEM);
 572                 res->start = base;
 573                 res->end = limit + 0xfffff;
 574                 pci_resource_adjust(res, &pbm->mem_space);
 575         }
 576
 577         pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
 578         pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
 579         base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
 580         limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
 581
 582         if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
 583                 u32 mem_base_hi, mem_limit_hi;
 584
 585                 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
 586                 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
 587
 588                 /*
 589                  * Some bridges set the base > limit by default, and some
 590                  * (broken) BIOSes do not initialize them.  If we find
 591                  * this, just assume they are not being used.
 592                  */
 593                 if (mem_base_hi <= mem_limit_hi) {
 594                         base |= ((long) mem_base_hi) << 32;
 595                         limit |= ((long) mem_limit_hi) << 32;
 596                 }
 597         }
 598
 599         res = bus->resource[2];
 600         if (base <= limit) {
 601                 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
 602                               IORESOURCE_MEM | IORESOURCE_PREFETCH);
 603                 res->start = base;
 604                 res->end = limit + 0xfffff;
 605                 pci_resource_adjust(res, &pbm->mem_space);
 606         }
 607 }
 608
 609 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
 610  * a proper 'ranges' property.
 611  */
 612 static void __devinit apb_fake_ranges(struct pci_dev *dev,
 613                                       struct pci_bus *bus,
 614                                       struct pci_pbm_info *pbm)
 615 {
 616         struct resource *res;
 617         u32 first, last;
 618         u8 map;
 619
 620         pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
 621         apb_calc_first_last(map, &first, &last);
 622         res = bus->resource[0];
 623         res->start = (first << 21);
 624         res->end = (last << 21) + ((1 << 21) - 1);
 625         res->flags = IORESOURCE_IO;
 626         pci_resource_adjust(res, &pbm->io_space);
 627
 628         pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
 629         apb_calc_first_last(map, &first, &last);
 630         res = bus->resource[1];
 631         res->start = (first << 21);
 632         res->end = (last << 21) + ((1 << 21) - 1);
 633         res->flags = IORESOURCE_MEM;
 634         pci_resource_adjust(res, &pbm->mem_space);
 635 }
 636
 637 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
 638                                       struct device_node *node,
 639                                       struct pci_bus *bus);
 640
 641 #define GET_64BIT(prop, i)      ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
 642
 643 static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
 644                                          struct device_node *node,
 645                                          struct pci_dev *dev)
 646 {
 647         struct pci_bus *bus;
 648         const u32 *busrange, *ranges;
 649         int len, i, simba;
 650         struct resource *res;
 651         unsigned int flags;
 652         u64 size;
 653
 654         if (ofpci_verbose)
 655                 printk("of_scan_pci_bridge(%s)\n", node->full_name);
 656
 657         /* parse bus-range property */
 658         busrange = of_get_property(node, "bus-range", &len);
 659         if (busrange == NULL || len != 8) {
 660                 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
 661                        node->full_name);
 662                 return;
 663         }
 664         ranges = of_get_property(node, "ranges", &len);
 665         simba = 0;
 666         if (ranges == NULL) {
 667                 const char *model = of_get_property(node, "model", NULL);
 668                 if (model && !strcmp(model, "SUNW,simba"))
 669                         simba = 1;
 670         }
 671
 672         bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
 673         if (!bus) {
 674                 printk(KERN_ERR "Failed to create pci bus for %s\n",
 675                        node->full_name);
 676                 return;
 677         }
 678
 679         bus->primary = dev->bus->number;
 680         bus->subordinate = busrange[1];
 681         bus->bridge_ctl = 0;
 682
 683         /* parse ranges property, or cook one up by hand for Simba */
 684         /* PCI #address-cells == 3 and #size-cells == 2 always */
 685         res = &dev->resource[PCI_BRIDGE_RESOURCES];
 686         for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
 687                 res->flags = 0;
 688                 bus->resource[i] = res;
 689                 ++res;
 690         }
 691         if (simba) {
 692                 apb_fake_ranges(dev, bus, pbm);
 693                 goto after_ranges;
 694         } else if (ranges == NULL) {
 695                 pci_cfg_fake_ranges(dev, bus, pbm);
 696                 goto after_ranges;
 697         }
 698         i = 1;
 699         for (; len >= 32; len -= 32, ranges += 8) {
 700                 struct resource *root;
 701
 702                 flags = pci_parse_of_flags(ranges[0]);
 703                 size = GET_64BIT(ranges, 6);
 704                 if (flags == 0 || size == 0)
 705                         continue;
 706                 if (flags & IORESOURCE_IO) {
 707                         res = bus->resource[0];
 708                         if (res->flags) {
 709                                 printk(KERN_ERR "PCI: ignoring extra I/O range"
 710                                        " for bridge %s\n", node->full_name);
 711                                 continue;
 712                         }
 713                         root = &pbm->io_space;
 714                 } else {
 715                         if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
 716                                 printk(KERN_ERR "PCI: too many memory ranges"
 717                                        " for bridge %s\n", node->full_name);
 718                                 continue;
 719                         }
 720                         res = bus->resource[i];
 721                         ++i;
 722                         root = &pbm->mem_space;
 723                 }
 724
 725                 res->start = GET_64BIT(ranges, 1);
 726                 res->end = res->start + size - 1;
 727                 res->flags = flags;
 728
 729                 /* Another way to implement this would be to add an of_device
 730                  * layer routine that can calculate a resource for a given
 731                  * range property value in a PCI device.
 732                  */
 733                 pci_resource_adjust(res, root);
 734         }
 735 after_ranges:
 736         sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
 737                 bus->number);
 738         if (ofpci_verbose)
 739                 printk("    bus name: %s\n", bus->name);
 740
 741         pci_of_scan_bus(pbm, node, bus);
 742 }
 743
 744 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
 745                                       struct device_node *node,
 746                                       struct pci_bus *bus)
 747 {
 748         struct device_node *child;
 749         const u32 *reg;
 750         int reglen, devfn;
 751         struct pci_dev *dev;
 752
 753         if (ofpci_verbose)
 754                 printk("PCI: scan_bus[%s] bus no %d\n",
 755                        node->full_name, bus->number);
 756
 757         child = NULL;
 758         while ((child = of_get_next_child(node, child)) != NULL) {
 759                 if (ofpci_verbose)
 760                         printk("  * %s\n", child->full_name);
 761                 reg = of_get_property(child, "reg", &reglen);
 762                 if (reg == NULL || reglen < 20)
 763                         continue;
 764                 devfn = (reg[0] >> 8) & 0xff;
 765
 766                 /* create a new pci_dev for this device */
 767                 dev = of_create_pci_dev(pbm, child, bus, devfn, 0);
 768                 if (!dev)
 769                         continue;
 770                 if (ofpci_verbose)
 771                         printk("PCI: dev header type: %x\n",
 772                                dev->hdr_type);
 773
 774                 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
 775                     dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
 776                         of_scan_pci_bridge(pbm, child, dev);
 777         }
 778 }
 779
 780 static ssize_t
 781 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
 782 {
 783         struct pci_dev *pdev;
 784         struct device_node *dp;
 785
 786         pdev = to_pci_dev(dev);
 787         dp = pdev->dev.archdata.prom_node;
 788
 789         return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
 790 }
 791
 792 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
 793
 794 static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
 795 {
 796         struct pci_dev *dev;
 797         struct pci_bus *child_bus;
 798         int err;
 799
 800         list_for_each_entry(dev, &bus->devices, bus_list) {
 801                 /* we don't really care if we can create this file or
 802                  * not, but we need to assign the result of the call
 803                  * or the world will fall under alien invasion and
 804                  * everybody will be frozen on a spaceship ready to be
 805                  * eaten on alpha centauri by some green and jelly
 806                  * humanoid.
 807                  */
 808                 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
 809         }
 810         list_for_each_entry(child_bus, &bus->children, node)
 811                 pci_bus_register_of_sysfs(child_bus);
 812 }
 813
 814 int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev,
 815                                  unsigned int devfn,
 816                                  int where, int size,
 817                                  u32 *value)
 818 {
 819         static u8 fake_pci_config[] = {
 820                 0x8e, 0x10, /* Vendor: 0x108e (Sun) */
 821                 0x00, 0x80, /* Device: 0x8000 (PBM) */
 822                 0x46, 0x01, /* Command: 0x0146 (SERR, PARITY, MASTER, MEM) */
 823                 0xa0, 0x22, /* Status: 0x02a0 (DEVSEL_MED, FB2B, 66MHZ) */
 824                 0x00, 0x00, 0x00, 0x06, /* Class: 0x06000000 host bridge */
 825                 0x00, /* Cacheline: 0x00 */
 826                 0x40, /* Latency: 0x40 */
 827                 0x00, /* Header-Type: 0x00 normal */
 828         };
 829
 830         *value = 0;
 831         if (where >= 0 && where < sizeof(fake_pci_config) &&
 832             (where + size) >= 0 &&
 833             (where + size) < sizeof(fake_pci_config) &&
 834             size <= sizeof(u32)) {
 835                 while (size--) {
 836                         *value <<= 8;
 837                         *value |= fake_pci_config[where + size];
 838                 }
 839         }
 840
 841         return PCIBIOS_SUCCESSFUL;
 842 }
 843
 844 int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev,
 845                                   unsigned int devfn,
 846                                   int where, int size,
 847                                   u32 value)
 848 {
 849         return PCIBIOS_SUCCESSFUL;
 850 }
 851
 852 struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm)
 853 {
 854         struct device_node *node = pbm->prom_node;
 855         struct pci_dev *host_pdev;
 856         struct pci_bus *bus;
 857
 858         printk("PCI: Scanning PBM %s\n", node->full_name);
 859
 860         /* XXX parent device? XXX */
 861         bus = pci_create_bus(NULL, pbm->pci_first_busno, pbm->pci_ops, pbm);
 862         if (!bus) {
 863                 printk(KERN_ERR "Failed to create bus for %s\n",
 864                        node->full_name);
 865                 return NULL;
 866         }
 867         bus->secondary = pbm->pci_first_busno;
 868         bus->subordinate = pbm->pci_last_busno;
 869
 870         bus->resource[0] = &pbm->io_space;
 871         bus->resource[1] = &pbm->mem_space;
 872
 873         /* Create the dummy host bridge and link it in.  */
 874         host_pdev = of_create_pci_dev(pbm, node, bus, 0x00, 1);
 875         bus->self = host_pdev;
 876
 877         pci_of_scan_bus(pbm, node, bus);
 878         pci_bus_add_devices(bus);
 879         pci_bus_register_of_sysfs(bus);
 880
 881         return bus;
 882 }
 883
 884 static void __init pci_scan_each_controller_bus(void)
 885 {
 886         struct pci_pbm_info *pbm;
 887
 888         for (pbm = pci_pbm_root; pbm; pbm = pbm->next)
 889                 pbm->scan_bus(pbm);
 890 }
 891
 892 extern void power_init(void);
 893
 894 static int __init pcibios_init(void)
 895 {
 896         pci_controller_probe();
 897         if (pci_pbm_root == NULL)
 898                 return 0;
 899
 900         pci_scan_each_controller_bus();
 901
 902         isa_init();
 903         ebus_init();
 904         power_init();
 905
 906         return 0;
 907 }
 908
 909 subsys_initcall(pcibios_init);
 910
 911 void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
 912 {
 913         struct pci_pbm_info *pbm = pbus->sysdata;
 914
 915         /* Generic PCI bus probing sets these to point at
 916          * &io{port,mem}_resouce which is wrong for us.
 917          */
 918         pbus->resource[0] = &pbm->io_space;
 919         pbus->resource[1] = &pbm->mem_space;
 920 }
 921
 922 struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
 923 {
 924         struct pci_pbm_info *pbm = pdev->bus->sysdata;
 925         struct resource *root = NULL;
 926
 927         if (r->flags & IORESOURCE_IO)
 928                 root = &pbm->io_space;
 929         if (r->flags & IORESOURCE_MEM)
 930                 root = &pbm->mem_space;
 931
 932         return root;
 933 }
 934
 935 void pcibios_update_irq(struct pci_dev *pdev, int irq)
 936 {
 937 }
 938
 939 void pcibios_align_resource(void *data, struct resource *res,
 940                             resource_size_t size, resource_size_t align)
 941 {
 942 }
 943
 944 int pcibios_enable_device(struct pci_dev *dev, int mask)
 945 {
 946         u16 cmd, oldcmd;
 947         int i;
 948
 949         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 950         oldcmd = cmd;
 951
 952         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 953                 struct resource *res = &dev->resource[i];
 954
 955                 /* Only set up the requested stuff */
 956                 if (!(mask & (1<<i)))
 957                         continue;
 958
 959                 if (res->flags & IORESOURCE_IO)
 960                         cmd |= PCI_COMMAND_IO;
 961                 if (res->flags & IORESOURCE_MEM)
 962                         cmd |= PCI_COMMAND_MEMORY;
 963         }
 964
 965         if (cmd != oldcmd) {
 966                 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
 967                        pci_name(dev), cmd);
 968                 /* Enable the appropriate bits in the PCI command register.  */
 969                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 970         }
 971         return 0;
 972 }
 973
 974 void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
 975                              struct resource *res)
 976 {
 977         struct pci_pbm_info *pbm = pdev->bus->sysdata;
 978         struct resource zero_res, *root;
 979
 980         zero_res.start = 0;
 981         zero_res.end = 0;
 982         zero_res.flags = res->flags;
 983
 984         if (res->flags & IORESOURCE_IO)
 985                 root = &pbm->io_space;
 986         else
 987                 root = &pbm->mem_space;
 988
 989         pci_resource_adjust(&zero_res, root);
 990
 991         region->start = res->start - zero_res.start;
 992         region->end = res->end - zero_res.start;
 993 }
 994 EXPORT_SYMBOL(pcibios_resource_to_bus);
 995
 996 void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
 997                              struct pci_bus_region *region)
 998 {
 999         struct pci_pbm_info *pbm = pdev->bus->sysdata;
1000         struct resource *root;
1001
1002         res->start = region->start;
1003         res->end = region->end;
1004
1005         if (res->flags & IORESOURCE_IO)
1006                 root = &pbm->io_space;
1007         else
1008                 root = &pbm->mem_space;
1009
1010         pci_resource_adjust(res, root);
1011 }
1012 EXPORT_SYMBOL(pcibios_bus_to_resource);
1013
1014 char * __devinit pcibios_setup(char *str)
1015 {
1016         return str;
1017 }
1018
1019 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
1020
1021 /* If the user uses a host-bridge as the PCI device, he may use
1022  * this to perform a raw mmap() of the I/O or MEM space behind
1023  * that controller.
1024  *
1025  * This can be useful for execution of x86 PCI bios initialization code
1026  * on a PCI card, like the xfree86 int10 stuff does.
1027  */
1028 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
1029                                       enum pci_mmap_state mmap_state)
1030 {
1031         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1032         unsigned long space_size, user_offset, user_size;
1033
1034         if (mmap_state == pci_mmap_io) {
1035                 space_size = (pbm->io_space.end -
1036                               pbm->io_space.start) + 1;
1037         } else {
1038                 space_size = (pbm->mem_space.end -
1039                               pbm->mem_space.start) + 1;
1040         }
1041
1042         /* Make sure the request is in range. */
1043         user_offset = vma->vm_pgoff << PAGE_SHIFT;
1044         user_size = vma->vm_end - vma->vm_start;
1045
1046         if (user_offset >= space_size ||
1047             (user_offset + user_size) > space_size)
1048                 return -EINVAL;
1049
1050         if (mmap_state == pci_mmap_io) {
1051                 vma->vm_pgoff = (pbm->io_space.start +
1052                                  user_offset) >> PAGE_SHIFT;
1053         } else {
1054                 vma->vm_pgoff = (pbm->mem_space.start +
1055                                  user_offset) >> PAGE_SHIFT;
1056         }
1057
1058         return 0;
1059 }
1060
1061 /* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
1062  * to the 32-bit pci bus offset for DEV requested by the user.
1063  *
1064  * Basically, the user finds the base address for his device which he wishes
1065  * to mmap.  They read the 32-bit value from the config space base register,
1066  * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
1067  * offset parameter of mmap on /proc/bus/pci/XXX for that device.
1068  *
1069  * Returns negative error code on failure, zero on success.
1070  */
1071 static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
1072                                   enum pci_mmap_state mmap_state)
1073 {
1074         unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
1075         unsigned long user32 = user_offset & pci_memspace_mask;
1076         unsigned long largest_base, this_base, addr32;
1077         int i;
1078
1079         if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
1080                 return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
1081
1082         /* Figure out which base address this is for. */
1083         largest_base = 0UL;
1084         for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
1085                 struct resource *rp = &dev->resource[i];
1086
1087                 /* Active? */
1088                 if (!rp->flags)
1089                         continue;
1090
1091                 /* Same type? */
1092                 if (i == PCI_ROM_RESOURCE) {
1093                         if (mmap_state != pci_mmap_mem)
1094                                 continue;
1095                 } else {
1096                         if ((mmap_state == pci_mmap_io &&
1097                              (rp->flags & IORESOURCE_IO) == 0) ||
1098                             (mmap_state == pci_mmap_mem &&
1099                              (rp->flags & IORESOURCE_MEM) == 0))
1100                                 continue;
1101                 }
1102
1103                 this_base = rp->start;
1104
1105                 addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
1106
1107                 if (mmap_state == pci_mmap_io)
1108                         addr32 &= 0xffffff;
1109
1110                 if (addr32 <= user32 && this_base > largest_base)
1111                         largest_base = this_base;
1112         }
1113
1114         if (largest_base == 0UL)
1115                 return -EINVAL;
1116
1117         /* Now construct the final physical address. */
1118         if (mmap_state == pci_mmap_io)
1119                 vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
1120         else
1121                 vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
1122
1123         return 0;
1124 }
1125
1126 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
1127  * mapping.
1128  */
1129 static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
1130                                             enum pci_mmap_state mmap_state)
1131 {
1132         vma->vm_flags |= (VM_IO | VM_RESERVED);
1133 }
1134
1135 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1136  * device mapping.
1137  */
1138 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
1139                                              enum pci_mmap_state mmap_state)
1140 {
1141         /* Our io_remap_pfn_range takes care of this, do nothing.  */
1142 }
1143
1144 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
1145  * for this architecture.  The region in the process to map is described by vm_start
1146  * and vm_end members of VMA, the base physical address is found in vm_pgoff.
1147  * The pci device structure is provided so that architectures may make mapping
1148  * decisions on a per-device or per-bus basis.
1149  *
1150  * Returns a negative error code on failure, zero on success.
1151  */
1152 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1153                         enum pci_mmap_state mmap_state,
1154                         int write_combine)
1155 {
1156         int ret;
1157
1158         ret = __pci_mmap_make_offset(dev, vma, mmap_state);
1159         if (ret < 0)
1160                 return ret;
1161
1162         __pci_mmap_set_flags(dev, vma, mmap_state);
1163         __pci_mmap_set_pgprot(dev, vma, mmap_state);
1164
1165         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1166         ret = io_remap_pfn_range(vma, vma->vm_start,
1167                                  vma->vm_pgoff,
1168                                  vma->vm_end - vma->vm_start,
1169                                  vma->vm_page_prot);
1170         if (ret)
1171                 return ret;
1172
1173         return 0;
1174 }
1175
1176 /* Return the domain nuber for this pci bus */
1177
1178 int pci_domain_nr(struct pci_bus *pbus)
1179 {
1180         struct pci_pbm_info *pbm = pbus->sysdata;
1181         int ret;
1182
1183         if (pbm == NULL || pbm->parent == NULL) {
1184                 ret = -ENXIO;
1185         } else {
1186                 ret = pbm->index;
1187         }
1188
1189         return ret;
1190 }
1191 EXPORT_SYMBOL(pci_domain_nr);
1192
1193 #ifdef CONFIG_PCI_MSI
1194 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1195 {
1196         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1197         int virt_irq;
1198
1199         if (!pbm->setup_msi_irq)
1200                 return -EINVAL;
1201
1202         return pbm->setup_msi_irq(&virt_irq, pdev, desc);
1203 }
1204
1205 void arch_teardown_msi_irq(unsigned int virt_irq)
1206 {
1207         struct msi_desc *entry = get_irq_msi(virt_irq);
1208         struct pci_dev *pdev = entry->dev;
1209         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1210
1211         if (!pbm->teardown_msi_irq)
1212                 return;
1213
1214         return pbm->teardown_msi_irq(virt_irq, pdev);
1215 }
1216 #endif /* !(CONFIG_PCI_MSI) */
1217
1218 struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1219 {
1220         return pdev->dev.archdata.prom_node;
1221 }
1222 EXPORT_SYMBOL(pci_device_to_OF_node);
1223
1224 #endif /* !(CONFIG_PCI) */