1 /* pci_fire.c: Sun4u platform PCI-E controller support.
3 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
5 #include <linux/kernel.h>
7 #include <linux/slab.h>
8 #include <linux/init.h>
11 #include <asm/oplib.h>
16 #define fire_read(__reg) \
18 __asm__ __volatile__("ldxa [%1] %2, %0" \
20 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
24 #define fire_write(__reg, __val) \
25 __asm__ __volatile__("stxa %0, [%1] %2" \
27 : "r" (__val), "r" (__reg), \
28 "i" (ASI_PHYS_BYPASS_EC_E) \
31 /* Fire config space address format is nearly identical to
32 * that of SCHIZO and PSYCHO, except that in order to accomodate
33 * PCI-E extended config space the encoding can handle 12 bits
34 * of register address:
36 * 32 28 27 20 19 15 14 12 11 2 1 0
37 * -------------------------------------------------
38 * |0 0 0 0 0| bus | device | function | reg | 0 0 |
39 * -------------------------------------------------
41 #define FIRE_CONFIG_BASE(PBM) ((PBM)->config_space)
42 #define FIRE_CONFIG_ENCODE(BUS, DEVFN, REG) \
43 (((unsigned long)(BUS) << 20) | \
44 ((unsigned long)(DEVFN) << 12) | \
45 ((unsigned long)(REG)))
47 static void *fire_pci_config_mkaddr(struct pci_pbm_info
*pbm
,
55 (FIRE_CONFIG_BASE(pbm
) |
56 FIRE_CONFIG_ENCODE(bus
, devfn
, where
));
59 /* FIRE PCI configuration space accessors. */
61 static int fire_read_pci_cfg(struct pci_bus
*bus_dev
, unsigned int devfn
,
62 int where
, int size
, u32
*value
)
64 struct pci_pbm_info
*pbm
= bus_dev
->sysdata
;
65 unsigned char bus
= bus_dev
->number
;
70 if (bus_dev
== pbm
->pci_bus
&& devfn
== 0x00)
71 return pci_host_bridge_read_pci_cfg(bus_dev
, devfn
, where
,
85 addr
= fire_pci_config_mkaddr(pbm
, bus
, devfn
, where
);
87 return PCIBIOS_SUCCESSFUL
;
91 pci_config_read8((u8
*)addr
, &tmp8
);
97 printk("pci_read_config_word: misaligned reg [%x]\n",
99 return PCIBIOS_SUCCESSFUL
;
101 pci_config_read16((u16
*)addr
, &tmp16
);
107 printk("pci_read_config_dword: misaligned reg [%x]\n",
109 return PCIBIOS_SUCCESSFUL
;
112 pci_config_read32(addr
, value
);
115 return PCIBIOS_SUCCESSFUL
;
118 static int fire_write_pci_cfg(struct pci_bus
*bus_dev
, unsigned int devfn
,
119 int where
, int size
, u32 value
)
121 struct pci_pbm_info
*pbm
= bus_dev
->sysdata
;
122 unsigned char bus
= bus_dev
->number
;
125 if (bus_dev
== pbm
->pci_bus
&& devfn
== 0x00)
126 return pci_host_bridge_write_pci_cfg(bus_dev
, devfn
, where
,
128 addr
= fire_pci_config_mkaddr(pbm
, bus
, devfn
, where
);
130 return PCIBIOS_SUCCESSFUL
;
134 pci_config_write8((u8
*)addr
, value
);
139 printk("pci_write_config_word: misaligned reg [%x]\n",
141 return PCIBIOS_SUCCESSFUL
;
143 pci_config_write16((u16
*)addr
, value
);
148 printk("pci_write_config_dword: misaligned reg [%x]\n",
150 return PCIBIOS_SUCCESSFUL
;
153 pci_config_write32(addr
, value
);
155 return PCIBIOS_SUCCESSFUL
;
158 static struct pci_ops pci_fire_ops
= {
159 .read
= fire_read_pci_cfg
,
160 .write
= fire_write_pci_cfg
,
163 static void pbm_scan_bus(struct pci_controller_info
*p
,
164 struct pci_pbm_info
*pbm
)
166 pbm
->pci_bus
= pci_scan_one_pbm(pbm
);
169 static void pci_fire_scan_bus(struct pci_controller_info
*p
)
171 struct device_node
*dp
;
173 if ((dp
= p
->pbm_A
.prom_node
) != NULL
)
174 pbm_scan_bus(p
, &p
->pbm_A
);
176 if ((dp
= p
->pbm_B
.prom_node
) != NULL
)
177 pbm_scan_bus(p
, &p
->pbm_B
);
179 /* XXX register error interrupt handlers XXX */
182 #define FIRE_IOMMU_CONTROL 0x40000UL
183 #define FIRE_IOMMU_TSBBASE 0x40008UL
184 #define FIRE_IOMMU_FLUSH 0x40100UL
185 #define FIRE_IOMMU_FLUSHINV 0x40100UL
187 static void pci_fire_pbm_iommu_init(struct pci_pbm_info
*pbm
)
189 struct iommu
*iommu
= pbm
->iommu
;
190 u32 vdma
[2], dma_mask
;
194 /* No virtual-dma property on these guys, use largest size. */
195 vdma
[0] = 0xc0000000; /* base */
196 vdma
[1] = 0x40000000; /* size */
197 dma_mask
= 0xffffffff;
200 /* Register addresses. */
201 iommu
->iommu_control
= pbm
->pbm_regs
+ FIRE_IOMMU_CONTROL
;
202 iommu
->iommu_tsbbase
= pbm
->pbm_regs
+ FIRE_IOMMU_TSBBASE
;
203 iommu
->iommu_flush
= pbm
->pbm_regs
+ FIRE_IOMMU_FLUSH
;
204 iommu
->iommu_flushinv
= pbm
->pbm_regs
+ FIRE_IOMMU_FLUSHINV
;
206 /* We use the main control/status register of FIRE as the write
207 * completion register.
209 iommu
->write_complete_reg
= pbm
->controller_regs
+ 0x410000UL
;
212 * Invalidate TLB Entries.
214 fire_write(iommu
->iommu_flushinv
, ~(u64
)0);
216 pci_iommu_table_init(iommu
, tsbsize
* 8 * 1024, vdma
[0], dma_mask
);
218 fire_write(iommu
->iommu_tsbbase
, __pa(iommu
->page_table
) | 0x7UL
);
220 control
= fire_read(iommu
->iommu_control
);
221 control
|= (0x00000400 /* TSB cache snoop enable */ |
222 0x00000300 /* Cache mode */ |
223 0x00000002 /* Bypass enable */ |
224 0x00000001 /* Translation enable */);
225 fire_write(iommu
->iommu_control
, control
);
228 /* Based at pbm->controller_regs */
229 #define FIRE_PARITY_CONTROL 0x470010UL
230 #define FIRE_PARITY_ENAB 0x8000000000000000UL
231 #define FIRE_FATAL_RESET_CTL 0x471028UL
232 #define FIRE_FATAL_RESET_SPARE 0x0000000004000000UL
233 #define FIRE_FATAL_RESET_MB 0x0000000002000000UL
234 #define FIRE_FATAL_RESET_CPE 0x0000000000008000UL
235 #define FIRE_FATAL_RESET_APE 0x0000000000004000UL
236 #define FIRE_FATAL_RESET_PIO 0x0000000000000040UL
237 #define FIRE_FATAL_RESET_JW 0x0000000000000004UL
238 #define FIRE_FATAL_RESET_JI 0x0000000000000002UL
239 #define FIRE_FATAL_RESET_JR 0x0000000000000001UL
240 #define FIRE_CORE_INTR_ENABLE 0x471800UL
242 /* Based at pbm->pbm_regs */
243 #define FIRE_TLU_CTRL 0x80000UL
244 #define FIRE_TLU_CTRL_TIM 0x00000000da000000UL
245 #define FIRE_TLU_CTRL_QDET 0x0000000000000100UL
246 #define FIRE_TLU_CTRL_CFG 0x0000000000000001UL
247 #define FIRE_TLU_DEV_CTRL 0x90008UL
248 #define FIRE_TLU_LINK_CTRL 0x90020UL
249 #define FIRE_TLU_LINK_CTRL_CLK 0x0000000000000040UL
250 #define FIRE_LPU_RESET 0xe2008UL
251 #define FIRE_LPU_LLCFG 0xe2200UL
252 #define FIRE_LPU_LLCFG_VC0 0x0000000000000100UL
253 #define FIRE_LPU_FCTRL_UCTRL 0xe2240UL
254 #define FIRE_LPU_FCTRL_UCTRL_N 0x0000000000000002UL
255 #define FIRE_LPU_FCTRL_UCTRL_P 0x0000000000000001UL
256 #define FIRE_LPU_TXL_FIFOP 0xe2430UL
257 #define FIRE_LPU_LTSSM_CFG2 0xe2788UL
258 #define FIRE_LPU_LTSSM_CFG3 0xe2790UL
259 #define FIRE_LPU_LTSSM_CFG4 0xe2798UL
260 #define FIRE_LPU_LTSSM_CFG5 0xe27a0UL
261 #define FIRE_DMC_IENAB 0x31800UL
262 #define FIRE_DMC_DBG_SEL_A 0x53000UL
263 #define FIRE_DMC_DBG_SEL_B 0x53008UL
264 #define FIRE_PEC_IENAB 0x51800UL
266 static void pci_fire_hw_init(struct pci_pbm_info
*pbm
)
270 fire_write(pbm
->controller_regs
+ FIRE_PARITY_CONTROL
,
273 fire_write(pbm
->controller_regs
+ FIRE_FATAL_RESET_CTL
,
274 (FIRE_FATAL_RESET_SPARE
|
275 FIRE_FATAL_RESET_MB
|
276 FIRE_FATAL_RESET_CPE
|
277 FIRE_FATAL_RESET_APE
|
278 FIRE_FATAL_RESET_PIO
|
279 FIRE_FATAL_RESET_JW
|
280 FIRE_FATAL_RESET_JI
|
281 FIRE_FATAL_RESET_JR
));
283 fire_write(pbm
->controller_regs
+ FIRE_CORE_INTR_ENABLE
, ~(u64
)0);
285 val
= fire_read(pbm
->pbm_regs
+ FIRE_TLU_CTRL
);
286 val
|= (FIRE_TLU_CTRL_TIM
|
289 fire_write(pbm
->pbm_regs
+ FIRE_TLU_CTRL
, val
);
290 fire_write(pbm
->pbm_regs
+ FIRE_TLU_DEV_CTRL
, 0);
291 fire_write(pbm
->pbm_regs
+ FIRE_TLU_LINK_CTRL
,
292 FIRE_TLU_LINK_CTRL_CLK
);
294 fire_write(pbm
->pbm_regs
+ FIRE_LPU_RESET
, 0);
295 fire_write(pbm
->pbm_regs
+ FIRE_LPU_LLCFG
,
297 fire_write(pbm
->pbm_regs
+ FIRE_LPU_FCTRL_UCTRL
,
298 (FIRE_LPU_FCTRL_UCTRL_N
|
299 FIRE_LPU_FCTRL_UCTRL_P
));
300 fire_write(pbm
->pbm_regs
+ FIRE_LPU_TXL_FIFOP
,
301 ((0xffff << 16) | (0x0000 << 0)));
302 fire_write(pbm
->pbm_regs
+ FIRE_LPU_LTSSM_CFG2
, 3000000);
303 fire_write(pbm
->pbm_regs
+ FIRE_LPU_LTSSM_CFG3
, 500000);
304 fire_write(pbm
->pbm_regs
+ FIRE_LPU_LTSSM_CFG4
,
305 (2 << 16) | (140 << 8));
306 fire_write(pbm
->pbm_regs
+ FIRE_LPU_LTSSM_CFG5
, 0);
308 fire_write(pbm
->pbm_regs
+ FIRE_DMC_IENAB
, ~(u64
)0);
309 fire_write(pbm
->pbm_regs
+ FIRE_DMC_DBG_SEL_A
, 0);
310 fire_write(pbm
->pbm_regs
+ FIRE_DMC_DBG_SEL_B
, 0);
312 fire_write(pbm
->pbm_regs
+ FIRE_PEC_IENAB
, ~(u64
)0);
315 static void pci_fire_pbm_init(struct pci_controller_info
*p
,
316 struct device_node
*dp
, u32 portid
)
318 const struct linux_prom64_registers
*regs
;
319 struct pci_pbm_info
*pbm
;
320 const u32
*ino_bitmap
;
321 const unsigned int *busrange
;
323 if ((portid
& 1) == 0)
328 pbm
->portid
= portid
;
331 pbm
->name
= dp
->full_name
;
333 regs
= of_get_property(dp
, "reg", NULL
);
334 pbm
->pbm_regs
= regs
[0].phys_addr
;
335 pbm
->controller_regs
= regs
[1].phys_addr
- 0x410000UL
;
337 printk("%s: SUN4U PCIE Bus Module\n", pbm
->name
);
339 pci_determine_mem_io_space(pbm
);
341 ino_bitmap
= of_get_property(dp
, "ino-bitmap", NULL
);
342 pbm
->ino_bitmap
= (((u64
)ino_bitmap
[1] << 32UL) |
343 ((u64
)ino_bitmap
[0] << 0UL));
345 busrange
= of_get_property(dp
, "bus-range", NULL
);
346 pbm
->pci_first_busno
= busrange
[0];
347 pbm
->pci_last_busno
= busrange
[1];
349 pci_fire_hw_init(pbm
);
350 pci_fire_pbm_iommu_init(pbm
);
353 static inline int portid_compare(u32 x
, u32 y
)
360 void fire_pci_init(struct device_node
*dp
, const char *model_name
)
362 struct pci_controller_info
*p
;
363 u32 portid
= of_getintprop_default(dp
, "portid", 0xff);
366 for (p
= pci_controller_root
; p
; p
= p
->next
) {
367 struct pci_pbm_info
*pbm
;
369 if (p
->pbm_A
.prom_node
&& p
->pbm_B
.prom_node
)
372 pbm
= (p
->pbm_A
.prom_node
?
376 if (portid_compare(pbm
->portid
, portid
)) {
377 pci_fire_pbm_init(p
, dp
, portid
);
382 p
= kzalloc(sizeof(struct pci_controller_info
), GFP_ATOMIC
);
384 goto fatal_memory_error
;
386 iommu
= kzalloc(sizeof(struct iommu
), GFP_ATOMIC
);
388 goto fatal_memory_error
;
390 p
->pbm_A
.iommu
= iommu
;
392 iommu
= kzalloc(sizeof(struct iommu
), GFP_ATOMIC
);
394 goto fatal_memory_error
;
396 p
->pbm_B
.iommu
= iommu
;
398 p
->next
= pci_controller_root
;
399 pci_controller_root
= p
;
401 p
->index
= pci_num_controllers
++;
403 p
->scan_bus
= pci_fire_scan_bus
;
404 /* XXX MSI support XXX */
405 p
->pci_ops
= &pci_fire_ops
;
407 /* Like PSYCHO and SCHIZO we have a 2GB aligned area
410 pci_memspace_mask
= 0x7fffffffUL
;
412 pci_fire_pbm_init(p
, dp
, portid
);
416 prom_printf("PCI_FIRE: Fatal memory allocation error.\n");
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