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Merge branch 'master' of ssh://master.kernel.org/pub/scm/linux/kernel/git/mchehab...
[deliverable/linux.git] / arch / sparc64 / kernel / traps.c
1 /* $Id: traps.c,v 1.85 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/kernel/traps.c
3 *
4 * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997,1999,2000 Jakub Jelinek (jakub@redhat.com)
6 */
7
8 /*
9 * I like traps on v9, :))))
10 */
11
12 #include <linux/module.h>
13 #include <linux/sched.h>
14 #include <linux/kernel.h>
15 #include <linux/kallsyms.h>
16 #include <linux/signal.h>
17 #include <linux/smp.h>
18 #include <linux/mm.h>
19 #include <linux/init.h>
20 #include <linux/kdebug.h>
21
22 #include <asm/smp.h>
23 #include <asm/delay.h>
24 #include <asm/system.h>
25 #include <asm/ptrace.h>
26 #include <asm/oplib.h>
27 #include <asm/page.h>
28 #include <asm/pgtable.h>
29 #include <asm/unistd.h>
30 #include <asm/uaccess.h>
31 #include <asm/fpumacro.h>
32 #include <asm/lsu.h>
33 #include <asm/dcu.h>
34 #include <asm/estate.h>
35 #include <asm/chafsr.h>
36 #include <asm/sfafsr.h>
37 #include <asm/psrcompat.h>
38 #include <asm/processor.h>
39 #include <asm/timer.h>
40 #include <asm/head.h>
41 #ifdef CONFIG_KMOD
42 #include <linux/kmod.h>
43 #endif
44 #include <asm/prom.h>
45
46
47 /* When an irrecoverable trap occurs at tl > 0, the trap entry
48 * code logs the trap state registers at every level in the trap
49 * stack. It is found at (pt_regs + sizeof(pt_regs)) and the layout
50 * is as follows:
51 */
52 struct tl1_traplog {
53 struct {
54 unsigned long tstate;
55 unsigned long tpc;
56 unsigned long tnpc;
57 unsigned long tt;
58 } trapstack[4];
59 unsigned long tl;
60 };
61
62 static void dump_tl1_traplog(struct tl1_traplog *p)
63 {
64 int i, limit;
65
66 printk(KERN_EMERG "TRAPLOG: Error at trap level 0x%lx, "
67 "dumping track stack.\n", p->tl);
68
69 limit = (tlb_type == hypervisor) ? 2 : 4;
70 for (i = 0; i < limit; i++) {
71 printk(KERN_EMERG
72 "TRAPLOG: Trap level %d TSTATE[%016lx] TPC[%016lx] "
73 "TNPC[%016lx] TT[%lx]\n",
74 i + 1,
75 p->trapstack[i].tstate, p->trapstack[i].tpc,
76 p->trapstack[i].tnpc, p->trapstack[i].tt);
77 print_symbol("TRAPLOG: TPC<%s>\n", p->trapstack[i].tpc);
78 }
79 }
80
81 void do_call_debug(struct pt_regs *regs)
82 {
83 notify_die(DIE_CALL, "debug call", regs, 0, 255, SIGINT);
84 }
85
86 void bad_trap(struct pt_regs *regs, long lvl)
87 {
88 char buffer[32];
89 siginfo_t info;
90
91 if (notify_die(DIE_TRAP, "bad trap", regs,
92 0, lvl, SIGTRAP) == NOTIFY_STOP)
93 return;
94
95 if (lvl < 0x100) {
96 sprintf(buffer, "Bad hw trap %lx at tl0\n", lvl);
97 die_if_kernel(buffer, regs);
98 }
99
100 lvl -= 0x100;
101 if (regs->tstate & TSTATE_PRIV) {
102 sprintf(buffer, "Kernel bad sw trap %lx", lvl);
103 die_if_kernel(buffer, regs);
104 }
105 if (test_thread_flag(TIF_32BIT)) {
106 regs->tpc &= 0xffffffff;
107 regs->tnpc &= 0xffffffff;
108 }
109 info.si_signo = SIGILL;
110 info.si_errno = 0;
111 info.si_code = ILL_ILLTRP;
112 info.si_addr = (void __user *)regs->tpc;
113 info.si_trapno = lvl;
114 force_sig_info(SIGILL, &info, current);
115 }
116
117 void bad_trap_tl1(struct pt_regs *regs, long lvl)
118 {
119 char buffer[32];
120
121 if (notify_die(DIE_TRAP_TL1, "bad trap tl1", regs,
122 0, lvl, SIGTRAP) == NOTIFY_STOP)
123 return;
124
125 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
126
127 sprintf (buffer, "Bad trap %lx at tl>0", lvl);
128 die_if_kernel (buffer, regs);
129 }
130
131 #ifdef CONFIG_DEBUG_BUGVERBOSE
132 void do_BUG(const char *file, int line)
133 {
134 bust_spinlocks(1);
135 printk("kernel BUG at %s:%d!\n", file, line);
136 }
137 #endif
138
139 void spitfire_insn_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
140 {
141 siginfo_t info;
142
143 if (notify_die(DIE_TRAP, "instruction access exception", regs,
144 0, 0x8, SIGTRAP) == NOTIFY_STOP)
145 return;
146
147 if (regs->tstate & TSTATE_PRIV) {
148 printk("spitfire_insn_access_exception: SFSR[%016lx] "
149 "SFAR[%016lx], going.\n", sfsr, sfar);
150 die_if_kernel("Iax", regs);
151 }
152 if (test_thread_flag(TIF_32BIT)) {
153 regs->tpc &= 0xffffffff;
154 regs->tnpc &= 0xffffffff;
155 }
156 info.si_signo = SIGSEGV;
157 info.si_errno = 0;
158 info.si_code = SEGV_MAPERR;
159 info.si_addr = (void __user *)regs->tpc;
160 info.si_trapno = 0;
161 force_sig_info(SIGSEGV, &info, current);
162 }
163
164 void spitfire_insn_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
165 {
166 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
167 0, 0x8, SIGTRAP) == NOTIFY_STOP)
168 return;
169
170 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
171 spitfire_insn_access_exception(regs, sfsr, sfar);
172 }
173
174 void sun4v_insn_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
175 {
176 unsigned short type = (type_ctx >> 16);
177 unsigned short ctx = (type_ctx & 0xffff);
178 siginfo_t info;
179
180 if (notify_die(DIE_TRAP, "instruction access exception", regs,
181 0, 0x8, SIGTRAP) == NOTIFY_STOP)
182 return;
183
184 if (regs->tstate & TSTATE_PRIV) {
185 printk("sun4v_insn_access_exception: ADDR[%016lx] "
186 "CTX[%04x] TYPE[%04x], going.\n",
187 addr, ctx, type);
188 die_if_kernel("Iax", regs);
189 }
190
191 if (test_thread_flag(TIF_32BIT)) {
192 regs->tpc &= 0xffffffff;
193 regs->tnpc &= 0xffffffff;
194 }
195 info.si_signo = SIGSEGV;
196 info.si_errno = 0;
197 info.si_code = SEGV_MAPERR;
198 info.si_addr = (void __user *) addr;
199 info.si_trapno = 0;
200 force_sig_info(SIGSEGV, &info, current);
201 }
202
203 void sun4v_insn_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
204 {
205 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
206 0, 0x8, SIGTRAP) == NOTIFY_STOP)
207 return;
208
209 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
210 sun4v_insn_access_exception(regs, addr, type_ctx);
211 }
212
213 void spitfire_data_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
214 {
215 siginfo_t info;
216
217 if (notify_die(DIE_TRAP, "data access exception", regs,
218 0, 0x30, SIGTRAP) == NOTIFY_STOP)
219 return;
220
221 if (regs->tstate & TSTATE_PRIV) {
222 /* Test if this comes from uaccess places. */
223 const struct exception_table_entry *entry;
224
225 entry = search_exception_tables(regs->tpc);
226 if (entry) {
227 /* Ouch, somebody is trying VM hole tricks on us... */
228 #ifdef DEBUG_EXCEPTIONS
229 printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
230 printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
231 regs->tpc, entry->fixup);
232 #endif
233 regs->tpc = entry->fixup;
234 regs->tnpc = regs->tpc + 4;
235 return;
236 }
237 /* Shit... */
238 printk("spitfire_data_access_exception: SFSR[%016lx] "
239 "SFAR[%016lx], going.\n", sfsr, sfar);
240 die_if_kernel("Dax", regs);
241 }
242
243 info.si_signo = SIGSEGV;
244 info.si_errno = 0;
245 info.si_code = SEGV_MAPERR;
246 info.si_addr = (void __user *)sfar;
247 info.si_trapno = 0;
248 force_sig_info(SIGSEGV, &info, current);
249 }
250
251 void spitfire_data_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
252 {
253 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
254 0, 0x30, SIGTRAP) == NOTIFY_STOP)
255 return;
256
257 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
258 spitfire_data_access_exception(regs, sfsr, sfar);
259 }
260
261 void sun4v_data_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
262 {
263 unsigned short type = (type_ctx >> 16);
264 unsigned short ctx = (type_ctx & 0xffff);
265 siginfo_t info;
266
267 if (notify_die(DIE_TRAP, "data access exception", regs,
268 0, 0x8, SIGTRAP) == NOTIFY_STOP)
269 return;
270
271 if (regs->tstate & TSTATE_PRIV) {
272 printk("sun4v_data_access_exception: ADDR[%016lx] "
273 "CTX[%04x] TYPE[%04x], going.\n",
274 addr, ctx, type);
275 die_if_kernel("Dax", regs);
276 }
277
278 if (test_thread_flag(TIF_32BIT)) {
279 regs->tpc &= 0xffffffff;
280 regs->tnpc &= 0xffffffff;
281 }
282 info.si_signo = SIGSEGV;
283 info.si_errno = 0;
284 info.si_code = SEGV_MAPERR;
285 info.si_addr = (void __user *) addr;
286 info.si_trapno = 0;
287 force_sig_info(SIGSEGV, &info, current);
288 }
289
290 void sun4v_data_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
291 {
292 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
293 0, 0x8, SIGTRAP) == NOTIFY_STOP)
294 return;
295
296 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
297 sun4v_data_access_exception(regs, addr, type_ctx);
298 }
299
300 #ifdef CONFIG_PCI
301 /* This is really pathetic... */
302 extern volatile int pci_poke_in_progress;
303 extern volatile int pci_poke_cpu;
304 extern volatile int pci_poke_faulted;
305 #endif
306
307 /* When access exceptions happen, we must do this. */
308 static void spitfire_clean_and_reenable_l1_caches(void)
309 {
310 unsigned long va;
311
312 if (tlb_type != spitfire)
313 BUG();
314
315 /* Clean 'em. */
316 for (va = 0; va < (PAGE_SIZE << 1); va += 32) {
317 spitfire_put_icache_tag(va, 0x0);
318 spitfire_put_dcache_tag(va, 0x0);
319 }
320
321 /* Re-enable in LSU. */
322 __asm__ __volatile__("flush %%g6\n\t"
323 "membar #Sync\n\t"
324 "stxa %0, [%%g0] %1\n\t"
325 "membar #Sync"
326 : /* no outputs */
327 : "r" (LSU_CONTROL_IC | LSU_CONTROL_DC |
328 LSU_CONTROL_IM | LSU_CONTROL_DM),
329 "i" (ASI_LSU_CONTROL)
330 : "memory");
331 }
332
333 static void spitfire_enable_estate_errors(void)
334 {
335 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
336 "membar #Sync"
337 : /* no outputs */
338 : "r" (ESTATE_ERR_ALL),
339 "i" (ASI_ESTATE_ERROR_EN));
340 }
341
342 static char ecc_syndrome_table[] = {
343 0x4c, 0x40, 0x41, 0x48, 0x42, 0x48, 0x48, 0x49,
344 0x43, 0x48, 0x48, 0x49, 0x48, 0x49, 0x49, 0x4a,
345 0x44, 0x48, 0x48, 0x20, 0x48, 0x39, 0x4b, 0x48,
346 0x48, 0x25, 0x31, 0x48, 0x28, 0x48, 0x48, 0x2c,
347 0x45, 0x48, 0x48, 0x21, 0x48, 0x3d, 0x04, 0x48,
348 0x48, 0x4b, 0x35, 0x48, 0x2d, 0x48, 0x48, 0x29,
349 0x48, 0x00, 0x01, 0x48, 0x0a, 0x48, 0x48, 0x4b,
350 0x0f, 0x48, 0x48, 0x4b, 0x48, 0x49, 0x49, 0x48,
351 0x46, 0x48, 0x48, 0x2a, 0x48, 0x3b, 0x27, 0x48,
352 0x48, 0x4b, 0x33, 0x48, 0x22, 0x48, 0x48, 0x2e,
353 0x48, 0x19, 0x1d, 0x48, 0x1b, 0x4a, 0x48, 0x4b,
354 0x1f, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
355 0x48, 0x4b, 0x24, 0x48, 0x07, 0x48, 0x48, 0x36,
356 0x4b, 0x48, 0x48, 0x3e, 0x48, 0x30, 0x38, 0x48,
357 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x16, 0x48,
358 0x48, 0x12, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
359 0x47, 0x48, 0x48, 0x2f, 0x48, 0x3f, 0x4b, 0x48,
360 0x48, 0x06, 0x37, 0x48, 0x23, 0x48, 0x48, 0x2b,
361 0x48, 0x05, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x32,
362 0x26, 0x48, 0x48, 0x3a, 0x48, 0x34, 0x3c, 0x48,
363 0x48, 0x11, 0x15, 0x48, 0x13, 0x4a, 0x48, 0x4b,
364 0x17, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
365 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x1e, 0x48,
366 0x48, 0x1a, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
367 0x48, 0x08, 0x0d, 0x48, 0x02, 0x48, 0x48, 0x49,
368 0x03, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x4b, 0x48,
369 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x10, 0x48,
370 0x48, 0x14, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
371 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x18, 0x48,
372 0x48, 0x1c, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
373 0x4a, 0x0c, 0x09, 0x48, 0x0e, 0x48, 0x48, 0x4b,
374 0x0b, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x4b, 0x4a
375 };
376
377 static char *syndrome_unknown = "<Unknown>";
378
379 static void spitfire_log_udb_syndrome(unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long bit)
380 {
381 unsigned short scode;
382 char memmod_str[64], *p;
383
384 if (udbl & bit) {
385 scode = ecc_syndrome_table[udbl & 0xff];
386 if (prom_getunumber(scode, afar,
387 memmod_str, sizeof(memmod_str)) == -1)
388 p = syndrome_unknown;
389 else
390 p = memmod_str;
391 printk(KERN_WARNING "CPU[%d]: UDBL Syndrome[%x] "
392 "Memory Module \"%s\"\n",
393 smp_processor_id(), scode, p);
394 }
395
396 if (udbh & bit) {
397 scode = ecc_syndrome_table[udbh & 0xff];
398 if (prom_getunumber(scode, afar,
399 memmod_str, sizeof(memmod_str)) == -1)
400 p = syndrome_unknown;
401 else
402 p = memmod_str;
403 printk(KERN_WARNING "CPU[%d]: UDBH Syndrome[%x] "
404 "Memory Module \"%s\"\n",
405 smp_processor_id(), scode, p);
406 }
407
408 }
409
410 static void spitfire_cee_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, int tl1, struct pt_regs *regs)
411 {
412
413 printk(KERN_WARNING "CPU[%d]: Correctable ECC Error "
414 "AFSR[%lx] AFAR[%016lx] UDBL[%lx] UDBH[%lx] TL>1[%d]\n",
415 smp_processor_id(), afsr, afar, udbl, udbh, tl1);
416
417 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_CE);
418
419 /* We always log it, even if someone is listening for this
420 * trap.
421 */
422 notify_die(DIE_TRAP, "Correctable ECC Error", regs,
423 0, TRAP_TYPE_CEE, SIGTRAP);
424
425 /* The Correctable ECC Error trap does not disable I/D caches. So
426 * we only have to restore the ESTATE Error Enable register.
427 */
428 spitfire_enable_estate_errors();
429 }
430
431 static void spitfire_ue_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long tt, int tl1, struct pt_regs *regs)
432 {
433 siginfo_t info;
434
435 printk(KERN_WARNING "CPU[%d]: Uncorrectable Error AFSR[%lx] "
436 "AFAR[%lx] UDBL[%lx] UDBH[%ld] TT[%lx] TL>1[%d]\n",
437 smp_processor_id(), afsr, afar, udbl, udbh, tt, tl1);
438
439 /* XXX add more human friendly logging of the error status
440 * XXX as is implemented for cheetah
441 */
442
443 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_UE);
444
445 /* We always log it, even if someone is listening for this
446 * trap.
447 */
448 notify_die(DIE_TRAP, "Uncorrectable Error", regs,
449 0, tt, SIGTRAP);
450
451 if (regs->tstate & TSTATE_PRIV) {
452 if (tl1)
453 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
454 die_if_kernel("UE", regs);
455 }
456
457 /* XXX need more intelligent processing here, such as is implemented
458 * XXX for cheetah errors, in fact if the E-cache still holds the
459 * XXX line with bad parity this will loop
460 */
461
462 spitfire_clean_and_reenable_l1_caches();
463 spitfire_enable_estate_errors();
464
465 if (test_thread_flag(TIF_32BIT)) {
466 regs->tpc &= 0xffffffff;
467 regs->tnpc &= 0xffffffff;
468 }
469 info.si_signo = SIGBUS;
470 info.si_errno = 0;
471 info.si_code = BUS_OBJERR;
472 info.si_addr = (void *)0;
473 info.si_trapno = 0;
474 force_sig_info(SIGBUS, &info, current);
475 }
476
477 void spitfire_access_error(struct pt_regs *regs, unsigned long status_encoded, unsigned long afar)
478 {
479 unsigned long afsr, tt, udbh, udbl;
480 int tl1;
481
482 afsr = (status_encoded & SFSTAT_AFSR_MASK) >> SFSTAT_AFSR_SHIFT;
483 tt = (status_encoded & SFSTAT_TRAP_TYPE) >> SFSTAT_TRAP_TYPE_SHIFT;
484 tl1 = (status_encoded & SFSTAT_TL_GT_ONE) ? 1 : 0;
485 udbl = (status_encoded & SFSTAT_UDBL_MASK) >> SFSTAT_UDBL_SHIFT;
486 udbh = (status_encoded & SFSTAT_UDBH_MASK) >> SFSTAT_UDBH_SHIFT;
487
488 #ifdef CONFIG_PCI
489 if (tt == TRAP_TYPE_DAE &&
490 pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
491 spitfire_clean_and_reenable_l1_caches();
492 spitfire_enable_estate_errors();
493
494 pci_poke_faulted = 1;
495 regs->tnpc = regs->tpc + 4;
496 return;
497 }
498 #endif
499
500 if (afsr & SFAFSR_UE)
501 spitfire_ue_log(afsr, afar, udbh, udbl, tt, tl1, regs);
502
503 if (tt == TRAP_TYPE_CEE) {
504 /* Handle the case where we took a CEE trap, but ACK'd
505 * only the UE state in the UDB error registers.
506 */
507 if (afsr & SFAFSR_UE) {
508 if (udbh & UDBE_CE) {
509 __asm__ __volatile__(
510 "stxa %0, [%1] %2\n\t"
511 "membar #Sync"
512 : /* no outputs */
513 : "r" (udbh & UDBE_CE),
514 "r" (0x0), "i" (ASI_UDB_ERROR_W));
515 }
516 if (udbl & UDBE_CE) {
517 __asm__ __volatile__(
518 "stxa %0, [%1] %2\n\t"
519 "membar #Sync"
520 : /* no outputs */
521 : "r" (udbl & UDBE_CE),
522 "r" (0x18), "i" (ASI_UDB_ERROR_W));
523 }
524 }
525
526 spitfire_cee_log(afsr, afar, udbh, udbl, tl1, regs);
527 }
528 }
529
530 int cheetah_pcache_forced_on;
531
532 void cheetah_enable_pcache(void)
533 {
534 unsigned long dcr;
535
536 printk("CHEETAH: Enabling P-Cache on cpu %d.\n",
537 smp_processor_id());
538
539 __asm__ __volatile__("ldxa [%%g0] %1, %0"
540 : "=r" (dcr)
541 : "i" (ASI_DCU_CONTROL_REG));
542 dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL);
543 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
544 "membar #Sync"
545 : /* no outputs */
546 : "r" (dcr), "i" (ASI_DCU_CONTROL_REG));
547 }
548
549 /* Cheetah error trap handling. */
550 static unsigned long ecache_flush_physbase;
551 static unsigned long ecache_flush_linesize;
552 static unsigned long ecache_flush_size;
553
554 /* WARNING: The error trap handlers in assembly know the precise
555 * layout of the following structure.
556 *
557 * C-level handlers below use this information to log the error
558 * and then determine how to recover (if possible).
559 */
560 struct cheetah_err_info {
561 /*0x00*/u64 afsr;
562 /*0x08*/u64 afar;
563
564 /* D-cache state */
565 /*0x10*/u64 dcache_data[4]; /* The actual data */
566 /*0x30*/u64 dcache_index; /* D-cache index */
567 /*0x38*/u64 dcache_tag; /* D-cache tag/valid */
568 /*0x40*/u64 dcache_utag; /* D-cache microtag */
569 /*0x48*/u64 dcache_stag; /* D-cache snooptag */
570
571 /* I-cache state */
572 /*0x50*/u64 icache_data[8]; /* The actual insns + predecode */
573 /*0x90*/u64 icache_index; /* I-cache index */
574 /*0x98*/u64 icache_tag; /* I-cache phys tag */
575 /*0xa0*/u64 icache_utag; /* I-cache microtag */
576 /*0xa8*/u64 icache_stag; /* I-cache snooptag */
577 /*0xb0*/u64 icache_upper; /* I-cache upper-tag */
578 /*0xb8*/u64 icache_lower; /* I-cache lower-tag */
579
580 /* E-cache state */
581 /*0xc0*/u64 ecache_data[4]; /* 32 bytes from staging registers */
582 /*0xe0*/u64 ecache_index; /* E-cache index */
583 /*0xe8*/u64 ecache_tag; /* E-cache tag/state */
584
585 /*0xf0*/u64 __pad[32 - 30];
586 };
587 #define CHAFSR_INVALID ((u64)-1L)
588
589 /* This table is ordered in priority of errors and matches the
590 * AFAR overwrite policy as well.
591 */
592
593 struct afsr_error_table {
594 unsigned long mask;
595 const char *name;
596 };
597
598 static const char CHAFSR_PERR_msg[] =
599 "System interface protocol error";
600 static const char CHAFSR_IERR_msg[] =
601 "Internal processor error";
602 static const char CHAFSR_ISAP_msg[] =
603 "System request parity error on incoming addresss";
604 static const char CHAFSR_UCU_msg[] =
605 "Uncorrectable E-cache ECC error for ifetch/data";
606 static const char CHAFSR_UCC_msg[] =
607 "SW Correctable E-cache ECC error for ifetch/data";
608 static const char CHAFSR_UE_msg[] =
609 "Uncorrectable system bus data ECC error for read";
610 static const char CHAFSR_EDU_msg[] =
611 "Uncorrectable E-cache ECC error for stmerge/blkld";
612 static const char CHAFSR_EMU_msg[] =
613 "Uncorrectable system bus MTAG error";
614 static const char CHAFSR_WDU_msg[] =
615 "Uncorrectable E-cache ECC error for writeback";
616 static const char CHAFSR_CPU_msg[] =
617 "Uncorrectable ECC error for copyout";
618 static const char CHAFSR_CE_msg[] =
619 "HW corrected system bus data ECC error for read";
620 static const char CHAFSR_EDC_msg[] =
621 "HW corrected E-cache ECC error for stmerge/blkld";
622 static const char CHAFSR_EMC_msg[] =
623 "HW corrected system bus MTAG ECC error";
624 static const char CHAFSR_WDC_msg[] =
625 "HW corrected E-cache ECC error for writeback";
626 static const char CHAFSR_CPC_msg[] =
627 "HW corrected ECC error for copyout";
628 static const char CHAFSR_TO_msg[] =
629 "Unmapped error from system bus";
630 static const char CHAFSR_BERR_msg[] =
631 "Bus error response from system bus";
632 static const char CHAFSR_IVC_msg[] =
633 "HW corrected system bus data ECC error for ivec read";
634 static const char CHAFSR_IVU_msg[] =
635 "Uncorrectable system bus data ECC error for ivec read";
636 static struct afsr_error_table __cheetah_error_table[] = {
637 { CHAFSR_PERR, CHAFSR_PERR_msg },
638 { CHAFSR_IERR, CHAFSR_IERR_msg },
639 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
640 { CHAFSR_UCU, CHAFSR_UCU_msg },
641 { CHAFSR_UCC, CHAFSR_UCC_msg },
642 { CHAFSR_UE, CHAFSR_UE_msg },
643 { CHAFSR_EDU, CHAFSR_EDU_msg },
644 { CHAFSR_EMU, CHAFSR_EMU_msg },
645 { CHAFSR_WDU, CHAFSR_WDU_msg },
646 { CHAFSR_CPU, CHAFSR_CPU_msg },
647 { CHAFSR_CE, CHAFSR_CE_msg },
648 { CHAFSR_EDC, CHAFSR_EDC_msg },
649 { CHAFSR_EMC, CHAFSR_EMC_msg },
650 { CHAFSR_WDC, CHAFSR_WDC_msg },
651 { CHAFSR_CPC, CHAFSR_CPC_msg },
652 { CHAFSR_TO, CHAFSR_TO_msg },
653 { CHAFSR_BERR, CHAFSR_BERR_msg },
654 /* These two do not update the AFAR. */
655 { CHAFSR_IVC, CHAFSR_IVC_msg },
656 { CHAFSR_IVU, CHAFSR_IVU_msg },
657 { 0, NULL },
658 };
659 static const char CHPAFSR_DTO_msg[] =
660 "System bus unmapped error for prefetch/storequeue-read";
661 static const char CHPAFSR_DBERR_msg[] =
662 "System bus error for prefetch/storequeue-read";
663 static const char CHPAFSR_THCE_msg[] =
664 "Hardware corrected E-cache Tag ECC error";
665 static const char CHPAFSR_TSCE_msg[] =
666 "SW handled correctable E-cache Tag ECC error";
667 static const char CHPAFSR_TUE_msg[] =
668 "Uncorrectable E-cache Tag ECC error";
669 static const char CHPAFSR_DUE_msg[] =
670 "System bus uncorrectable data ECC error due to prefetch/store-fill";
671 static struct afsr_error_table __cheetah_plus_error_table[] = {
672 { CHAFSR_PERR, CHAFSR_PERR_msg },
673 { CHAFSR_IERR, CHAFSR_IERR_msg },
674 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
675 { CHAFSR_UCU, CHAFSR_UCU_msg },
676 { CHAFSR_UCC, CHAFSR_UCC_msg },
677 { CHAFSR_UE, CHAFSR_UE_msg },
678 { CHAFSR_EDU, CHAFSR_EDU_msg },
679 { CHAFSR_EMU, CHAFSR_EMU_msg },
680 { CHAFSR_WDU, CHAFSR_WDU_msg },
681 { CHAFSR_CPU, CHAFSR_CPU_msg },
682 { CHAFSR_CE, CHAFSR_CE_msg },
683 { CHAFSR_EDC, CHAFSR_EDC_msg },
684 { CHAFSR_EMC, CHAFSR_EMC_msg },
685 { CHAFSR_WDC, CHAFSR_WDC_msg },
686 { CHAFSR_CPC, CHAFSR_CPC_msg },
687 { CHAFSR_TO, CHAFSR_TO_msg },
688 { CHAFSR_BERR, CHAFSR_BERR_msg },
689 { CHPAFSR_DTO, CHPAFSR_DTO_msg },
690 { CHPAFSR_DBERR, CHPAFSR_DBERR_msg },
691 { CHPAFSR_THCE, CHPAFSR_THCE_msg },
692 { CHPAFSR_TSCE, CHPAFSR_TSCE_msg },
693 { CHPAFSR_TUE, CHPAFSR_TUE_msg },
694 { CHPAFSR_DUE, CHPAFSR_DUE_msg },
695 /* These two do not update the AFAR. */
696 { CHAFSR_IVC, CHAFSR_IVC_msg },
697 { CHAFSR_IVU, CHAFSR_IVU_msg },
698 { 0, NULL },
699 };
700 static const char JPAFSR_JETO_msg[] =
701 "System interface protocol error, hw timeout caused";
702 static const char JPAFSR_SCE_msg[] =
703 "Parity error on system snoop results";
704 static const char JPAFSR_JEIC_msg[] =
705 "System interface protocol error, illegal command detected";
706 static const char JPAFSR_JEIT_msg[] =
707 "System interface protocol error, illegal ADTYPE detected";
708 static const char JPAFSR_OM_msg[] =
709 "Out of range memory error has occurred";
710 static const char JPAFSR_ETP_msg[] =
711 "Parity error on L2 cache tag SRAM";
712 static const char JPAFSR_UMS_msg[] =
713 "Error due to unsupported store";
714 static const char JPAFSR_RUE_msg[] =
715 "Uncorrectable ECC error from remote cache/memory";
716 static const char JPAFSR_RCE_msg[] =
717 "Correctable ECC error from remote cache/memory";
718 static const char JPAFSR_BP_msg[] =
719 "JBUS parity error on returned read data";
720 static const char JPAFSR_WBP_msg[] =
721 "JBUS parity error on data for writeback or block store";
722 static const char JPAFSR_FRC_msg[] =
723 "Foreign read to DRAM incurring correctable ECC error";
724 static const char JPAFSR_FRU_msg[] =
725 "Foreign read to DRAM incurring uncorrectable ECC error";
726 static struct afsr_error_table __jalapeno_error_table[] = {
727 { JPAFSR_JETO, JPAFSR_JETO_msg },
728 { JPAFSR_SCE, JPAFSR_SCE_msg },
729 { JPAFSR_JEIC, JPAFSR_JEIC_msg },
730 { JPAFSR_JEIT, JPAFSR_JEIT_msg },
731 { CHAFSR_PERR, CHAFSR_PERR_msg },
732 { CHAFSR_IERR, CHAFSR_IERR_msg },
733 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
734 { CHAFSR_UCU, CHAFSR_UCU_msg },
735 { CHAFSR_UCC, CHAFSR_UCC_msg },
736 { CHAFSR_UE, CHAFSR_UE_msg },
737 { CHAFSR_EDU, CHAFSR_EDU_msg },
738 { JPAFSR_OM, JPAFSR_OM_msg },
739 { CHAFSR_WDU, CHAFSR_WDU_msg },
740 { CHAFSR_CPU, CHAFSR_CPU_msg },
741 { CHAFSR_CE, CHAFSR_CE_msg },
742 { CHAFSR_EDC, CHAFSR_EDC_msg },
743 { JPAFSR_ETP, JPAFSR_ETP_msg },
744 { CHAFSR_WDC, CHAFSR_WDC_msg },
745 { CHAFSR_CPC, CHAFSR_CPC_msg },
746 { CHAFSR_TO, CHAFSR_TO_msg },
747 { CHAFSR_BERR, CHAFSR_BERR_msg },
748 { JPAFSR_UMS, JPAFSR_UMS_msg },
749 { JPAFSR_RUE, JPAFSR_RUE_msg },
750 { JPAFSR_RCE, JPAFSR_RCE_msg },
751 { JPAFSR_BP, JPAFSR_BP_msg },
752 { JPAFSR_WBP, JPAFSR_WBP_msg },
753 { JPAFSR_FRC, JPAFSR_FRC_msg },
754 { JPAFSR_FRU, JPAFSR_FRU_msg },
755 /* These two do not update the AFAR. */
756 { CHAFSR_IVU, CHAFSR_IVU_msg },
757 { 0, NULL },
758 };
759 static struct afsr_error_table *cheetah_error_table;
760 static unsigned long cheetah_afsr_errors;
761
762 /* This is allocated at boot time based upon the largest hardware
763 * cpu ID in the system. We allocate two entries per cpu, one for
764 * TL==0 logging and one for TL >= 1 logging.
765 */
766 struct cheetah_err_info *cheetah_error_log;
767
768 static __inline__ struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
769 {
770 struct cheetah_err_info *p;
771 int cpu = smp_processor_id();
772
773 if (!cheetah_error_log)
774 return NULL;
775
776 p = cheetah_error_log + (cpu * 2);
777 if ((afsr & CHAFSR_TL1) != 0UL)
778 p++;
779
780 return p;
781 }
782
783 extern unsigned int tl0_icpe[], tl1_icpe[];
784 extern unsigned int tl0_dcpe[], tl1_dcpe[];
785 extern unsigned int tl0_fecc[], tl1_fecc[];
786 extern unsigned int tl0_cee[], tl1_cee[];
787 extern unsigned int tl0_iae[], tl1_iae[];
788 extern unsigned int tl0_dae[], tl1_dae[];
789 extern unsigned int cheetah_plus_icpe_trap_vector[], cheetah_plus_icpe_trap_vector_tl1[];
790 extern unsigned int cheetah_plus_dcpe_trap_vector[], cheetah_plus_dcpe_trap_vector_tl1[];
791 extern unsigned int cheetah_fecc_trap_vector[], cheetah_fecc_trap_vector_tl1[];
792 extern unsigned int cheetah_cee_trap_vector[], cheetah_cee_trap_vector_tl1[];
793 extern unsigned int cheetah_deferred_trap_vector[], cheetah_deferred_trap_vector_tl1[];
794
795 void __init cheetah_ecache_flush_init(void)
796 {
797 unsigned long largest_size, smallest_linesize, order, ver;
798 struct device_node *dp;
799 int i, instance, sz;
800
801 /* Scan all cpu device tree nodes, note two values:
802 * 1) largest E-cache size
803 * 2) smallest E-cache line size
804 */
805 largest_size = 0UL;
806 smallest_linesize = ~0UL;
807
808 instance = 0;
809 while (!cpu_find_by_instance(instance, &dp, NULL)) {
810 unsigned long val;
811
812 val = of_getintprop_default(dp, "ecache-size",
813 (2 * 1024 * 1024));
814 if (val > largest_size)
815 largest_size = val;
816 val = of_getintprop_default(dp, "ecache-line-size", 64);
817 if (val < smallest_linesize)
818 smallest_linesize = val;
819 instance++;
820 }
821
822 if (largest_size == 0UL || smallest_linesize == ~0UL) {
823 prom_printf("cheetah_ecache_flush_init: Cannot probe cpu E-cache "
824 "parameters.\n");
825 prom_halt();
826 }
827
828 ecache_flush_size = (2 * largest_size);
829 ecache_flush_linesize = smallest_linesize;
830
831 ecache_flush_physbase = find_ecache_flush_span(ecache_flush_size);
832
833 if (ecache_flush_physbase == ~0UL) {
834 prom_printf("cheetah_ecache_flush_init: Cannot find %d byte "
835 "contiguous physical memory.\n",
836 ecache_flush_size);
837 prom_halt();
838 }
839
840 /* Now allocate error trap reporting scoreboard. */
841 sz = NR_CPUS * (2 * sizeof(struct cheetah_err_info));
842 for (order = 0; order < MAX_ORDER; order++) {
843 if ((PAGE_SIZE << order) >= sz)
844 break;
845 }
846 cheetah_error_log = (struct cheetah_err_info *)
847 __get_free_pages(GFP_KERNEL, order);
848 if (!cheetah_error_log) {
849 prom_printf("cheetah_ecache_flush_init: Failed to allocate "
850 "error logging scoreboard (%d bytes).\n", sz);
851 prom_halt();
852 }
853 memset(cheetah_error_log, 0, PAGE_SIZE << order);
854
855 /* Mark all AFSRs as invalid so that the trap handler will
856 * log new new information there.
857 */
858 for (i = 0; i < 2 * NR_CPUS; i++)
859 cheetah_error_log[i].afsr = CHAFSR_INVALID;
860
861 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
862 if ((ver >> 32) == __JALAPENO_ID ||
863 (ver >> 32) == __SERRANO_ID) {
864 cheetah_error_table = &__jalapeno_error_table[0];
865 cheetah_afsr_errors = JPAFSR_ERRORS;
866 } else if ((ver >> 32) == 0x003e0015) {
867 cheetah_error_table = &__cheetah_plus_error_table[0];
868 cheetah_afsr_errors = CHPAFSR_ERRORS;
869 } else {
870 cheetah_error_table = &__cheetah_error_table[0];
871 cheetah_afsr_errors = CHAFSR_ERRORS;
872 }
873
874 /* Now patch trap tables. */
875 memcpy(tl0_fecc, cheetah_fecc_trap_vector, (8 * 4));
876 memcpy(tl1_fecc, cheetah_fecc_trap_vector_tl1, (8 * 4));
877 memcpy(tl0_cee, cheetah_cee_trap_vector, (8 * 4));
878 memcpy(tl1_cee, cheetah_cee_trap_vector_tl1, (8 * 4));
879 memcpy(tl0_iae, cheetah_deferred_trap_vector, (8 * 4));
880 memcpy(tl1_iae, cheetah_deferred_trap_vector_tl1, (8 * 4));
881 memcpy(tl0_dae, cheetah_deferred_trap_vector, (8 * 4));
882 memcpy(tl1_dae, cheetah_deferred_trap_vector_tl1, (8 * 4));
883 if (tlb_type == cheetah_plus) {
884 memcpy(tl0_dcpe, cheetah_plus_dcpe_trap_vector, (8 * 4));
885 memcpy(tl1_dcpe, cheetah_plus_dcpe_trap_vector_tl1, (8 * 4));
886 memcpy(tl0_icpe, cheetah_plus_icpe_trap_vector, (8 * 4));
887 memcpy(tl1_icpe, cheetah_plus_icpe_trap_vector_tl1, (8 * 4));
888 }
889 flushi(PAGE_OFFSET);
890 }
891
892 static void cheetah_flush_ecache(void)
893 {
894 unsigned long flush_base = ecache_flush_physbase;
895 unsigned long flush_linesize = ecache_flush_linesize;
896 unsigned long flush_size = ecache_flush_size;
897
898 __asm__ __volatile__("1: subcc %0, %4, %0\n\t"
899 " bne,pt %%xcc, 1b\n\t"
900 " ldxa [%2 + %0] %3, %%g0\n\t"
901 : "=&r" (flush_size)
902 : "0" (flush_size), "r" (flush_base),
903 "i" (ASI_PHYS_USE_EC), "r" (flush_linesize));
904 }
905
906 static void cheetah_flush_ecache_line(unsigned long physaddr)
907 {
908 unsigned long alias;
909
910 physaddr &= ~(8UL - 1UL);
911 physaddr = (ecache_flush_physbase +
912 (physaddr & ((ecache_flush_size>>1UL) - 1UL)));
913 alias = physaddr + (ecache_flush_size >> 1UL);
914 __asm__ __volatile__("ldxa [%0] %2, %%g0\n\t"
915 "ldxa [%1] %2, %%g0\n\t"
916 "membar #Sync"
917 : /* no outputs */
918 : "r" (physaddr), "r" (alias),
919 "i" (ASI_PHYS_USE_EC));
920 }
921
922 /* Unfortunately, the diagnostic access to the I-cache tags we need to
923 * use to clear the thing interferes with I-cache coherency transactions.
924 *
925 * So we must only flush the I-cache when it is disabled.
926 */
927 static void __cheetah_flush_icache(void)
928 {
929 unsigned int icache_size, icache_line_size;
930 unsigned long addr;
931
932 icache_size = local_cpu_data().icache_size;
933 icache_line_size = local_cpu_data().icache_line_size;
934
935 /* Clear the valid bits in all the tags. */
936 for (addr = 0; addr < icache_size; addr += icache_line_size) {
937 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
938 "membar #Sync"
939 : /* no outputs */
940 : "r" (addr | (2 << 3)),
941 "i" (ASI_IC_TAG));
942 }
943 }
944
945 static void cheetah_flush_icache(void)
946 {
947 unsigned long dcu_save;
948
949 /* Save current DCU, disable I-cache. */
950 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
951 "or %0, %2, %%g1\n\t"
952 "stxa %%g1, [%%g0] %1\n\t"
953 "membar #Sync"
954 : "=r" (dcu_save)
955 : "i" (ASI_DCU_CONTROL_REG), "i" (DCU_IC)
956 : "g1");
957
958 __cheetah_flush_icache();
959
960 /* Restore DCU register */
961 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
962 "membar #Sync"
963 : /* no outputs */
964 : "r" (dcu_save), "i" (ASI_DCU_CONTROL_REG));
965 }
966
967 static void cheetah_flush_dcache(void)
968 {
969 unsigned int dcache_size, dcache_line_size;
970 unsigned long addr;
971
972 dcache_size = local_cpu_data().dcache_size;
973 dcache_line_size = local_cpu_data().dcache_line_size;
974
975 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
976 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
977 "membar #Sync"
978 : /* no outputs */
979 : "r" (addr), "i" (ASI_DCACHE_TAG));
980 }
981 }
982
983 /* In order to make the even parity correct we must do two things.
984 * First, we clear DC_data_parity and set DC_utag to an appropriate value.
985 * Next, we clear out all 32-bytes of data for that line. Data of
986 * all-zero + tag parity value of zero == correct parity.
987 */
988 static void cheetah_plus_zap_dcache_parity(void)
989 {
990 unsigned int dcache_size, dcache_line_size;
991 unsigned long addr;
992
993 dcache_size = local_cpu_data().dcache_size;
994 dcache_line_size = local_cpu_data().dcache_line_size;
995
996 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
997 unsigned long tag = (addr >> 14);
998 unsigned long line;
999
1000 __asm__ __volatile__("membar #Sync\n\t"
1001 "stxa %0, [%1] %2\n\t"
1002 "membar #Sync"
1003 : /* no outputs */
1004 : "r" (tag), "r" (addr),
1005 "i" (ASI_DCACHE_UTAG));
1006 for (line = addr; line < addr + dcache_line_size; line += 8)
1007 __asm__ __volatile__("membar #Sync\n\t"
1008 "stxa %%g0, [%0] %1\n\t"
1009 "membar #Sync"
1010 : /* no outputs */
1011 : "r" (line),
1012 "i" (ASI_DCACHE_DATA));
1013 }
1014 }
1015
1016 /* Conversion tables used to frob Cheetah AFSR syndrome values into
1017 * something palatable to the memory controller driver get_unumber
1018 * routine.
1019 */
1020 #define MT0 137
1021 #define MT1 138
1022 #define MT2 139
1023 #define NONE 254
1024 #define MTC0 140
1025 #define MTC1 141
1026 #define MTC2 142
1027 #define MTC3 143
1028 #define C0 128
1029 #define C1 129
1030 #define C2 130
1031 #define C3 131
1032 #define C4 132
1033 #define C5 133
1034 #define C6 134
1035 #define C7 135
1036 #define C8 136
1037 #define M2 144
1038 #define M3 145
1039 #define M4 146
1040 #define M 147
1041 static unsigned char cheetah_ecc_syntab[] = {
1042 /*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
1043 /*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16,
1044 /*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
1045 /*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
1046 /*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6,
1047 /*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
1048 /*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
1049 /*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
1050 /*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5,
1051 /*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M,
1052 /*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
1053 /*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
1054 /*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
1055 /*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
1056 /*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
1057 /*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
1058 /*10*/C8, M, M2, 39, M, 34, 105, M2, M, 30, 104, M, 101, M, M, 4,
1059 /*11*/M, M, 100, M, 83, M, M2, 12, 87, M, M, 57, M2, M, M3, M,
1060 /*12*/M2, 97, 82, M2, 78, M2, M2, 1, 96, M, M, M, M, M, M3, M2,
1061 /*13*/94, M, M2, M3, M2, M, M3, M, M2, M, 79, M, 69, M, M4, M,
1062 /*14*/M2, 93, 92, M, 91, M, M2, 8, 90, M2, M2, M, M, M, M, M4,
1063 /*15*/89, M, M, M3, M2, M3, M3, M, M, M, M3, M2, M3, M2, M, M3,
1064 /*16*/86, M, M2, M3, M2, M, M3, M, M2, M, M3, M, M3, M, M, M3,
1065 /*17*/M, M, M3, M2, M3, M2, M4, M, 60, M, M2, M3, M4, M, M, M2,
1066 /*18*/M2, 88, 85, M2, 84, M, M2, 55, 81, M2, M2, M3, M2, M3, M3, M4,
1067 /*19*/77, M, M, M, M2, M3, M, M, M2, M3, M3, M4, M3, M2, M, M,
1068 /*1a*/74, M, M2, M3, M, M, M3, M, M, M, M3, M, M3, M, M4, M3,
1069 /*1b*/M2, 70, 107, M4, 65, M2, M2, M, 127, M, M, M, M2, M3, M3, M,
1070 /*1c*/80, M2, M2, 72, M, 119, 118, M, M2, 126, 76, M, 125, M, M4, M3,
1071 /*1d*/M2, 115, 124, M, 75, M, M, M3, 61, M, M4, M, M4, M, M, M,
1072 /*1e*/M, 123, 122, M4, 121, M4, M, M3, 117, M2, M2, M3, M4, M3, M, M,
1073 /*1f*/111, M, M, M, M4, M3, M3, M, M, M, M3, M, M3, M2, M, M
1074 };
1075 static unsigned char cheetah_mtag_syntab[] = {
1076 NONE, MTC0,
1077 MTC1, NONE,
1078 MTC2, NONE,
1079 NONE, MT0,
1080 MTC3, NONE,
1081 NONE, MT1,
1082 NONE, MT2,
1083 NONE, NONE
1084 };
1085
1086 /* Return the highest priority error conditon mentioned. */
1087 static __inline__ unsigned long cheetah_get_hipri(unsigned long afsr)
1088 {
1089 unsigned long tmp = 0;
1090 int i;
1091
1092 for (i = 0; cheetah_error_table[i].mask; i++) {
1093 if ((tmp = (afsr & cheetah_error_table[i].mask)) != 0UL)
1094 return tmp;
1095 }
1096 return tmp;
1097 }
1098
1099 static const char *cheetah_get_string(unsigned long bit)
1100 {
1101 int i;
1102
1103 for (i = 0; cheetah_error_table[i].mask; i++) {
1104 if ((bit & cheetah_error_table[i].mask) != 0UL)
1105 return cheetah_error_table[i].name;
1106 }
1107 return "???";
1108 }
1109
1110 extern int chmc_getunumber(int, unsigned long, char *, int);
1111
1112 static void cheetah_log_errors(struct pt_regs *regs, struct cheetah_err_info *info,
1113 unsigned long afsr, unsigned long afar, int recoverable)
1114 {
1115 unsigned long hipri;
1116 char unum[256];
1117
1118 printk("%s" "ERROR(%d): Cheetah error trap taken afsr[%016lx] afar[%016lx] TL1(%d)\n",
1119 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1120 afsr, afar,
1121 (afsr & CHAFSR_TL1) ? 1 : 0);
1122 printk("%s" "ERROR(%d): TPC[%lx] TNPC[%lx] O7[%lx] TSTATE[%lx]\n",
1123 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1124 regs->tpc, regs->tnpc, regs->u_regs[UREG_I7], regs->tstate);
1125 printk("%s" "ERROR(%d): ",
1126 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id());
1127 print_symbol("TPC<%s>\n", regs->tpc);
1128 printk("%s" "ERROR(%d): M_SYND(%lx), E_SYND(%lx)%s%s\n",
1129 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1130 (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT,
1131 (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT,
1132 (afsr & CHAFSR_ME) ? ", Multiple Errors" : "",
1133 (afsr & CHAFSR_PRIV) ? ", Privileged" : "");
1134 hipri = cheetah_get_hipri(afsr);
1135 printk("%s" "ERROR(%d): Highest priority error (%016lx) \"%s\"\n",
1136 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1137 hipri, cheetah_get_string(hipri));
1138
1139 /* Try to get unumber if relevant. */
1140 #define ESYND_ERRORS (CHAFSR_IVC | CHAFSR_IVU | \
1141 CHAFSR_CPC | CHAFSR_CPU | \
1142 CHAFSR_UE | CHAFSR_CE | \
1143 CHAFSR_EDC | CHAFSR_EDU | \
1144 CHAFSR_UCC | CHAFSR_UCU | \
1145 CHAFSR_WDU | CHAFSR_WDC)
1146 #define MSYND_ERRORS (CHAFSR_EMC | CHAFSR_EMU)
1147 if (afsr & ESYND_ERRORS) {
1148 int syndrome;
1149 int ret;
1150
1151 syndrome = (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT;
1152 syndrome = cheetah_ecc_syntab[syndrome];
1153 ret = chmc_getunumber(syndrome, afar, unum, sizeof(unum));
1154 if (ret != -1)
1155 printk("%s" "ERROR(%d): AFAR E-syndrome [%s]\n",
1156 (recoverable ? KERN_WARNING : KERN_CRIT),
1157 smp_processor_id(), unum);
1158 } else if (afsr & MSYND_ERRORS) {
1159 int syndrome;
1160 int ret;
1161
1162 syndrome = (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT;
1163 syndrome = cheetah_mtag_syntab[syndrome];
1164 ret = chmc_getunumber(syndrome, afar, unum, sizeof(unum));
1165 if (ret != -1)
1166 printk("%s" "ERROR(%d): AFAR M-syndrome [%s]\n",
1167 (recoverable ? KERN_WARNING : KERN_CRIT),
1168 smp_processor_id(), unum);
1169 }
1170
1171 /* Now dump the cache snapshots. */
1172 printk("%s" "ERROR(%d): D-cache idx[%x] tag[%016lx] utag[%016lx] stag[%016lx]\n",
1173 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1174 (int) info->dcache_index,
1175 info->dcache_tag,
1176 info->dcache_utag,
1177 info->dcache_stag);
1178 printk("%s" "ERROR(%d): D-cache data0[%016lx] data1[%016lx] data2[%016lx] data3[%016lx]\n",
1179 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1180 info->dcache_data[0],
1181 info->dcache_data[1],
1182 info->dcache_data[2],
1183 info->dcache_data[3]);
1184 printk("%s" "ERROR(%d): I-cache idx[%x] tag[%016lx] utag[%016lx] stag[%016lx] "
1185 "u[%016lx] l[%016lx]\n",
1186 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1187 (int) info->icache_index,
1188 info->icache_tag,
1189 info->icache_utag,
1190 info->icache_stag,
1191 info->icache_upper,
1192 info->icache_lower);
1193 printk("%s" "ERROR(%d): I-cache INSN0[%016lx] INSN1[%016lx] INSN2[%016lx] INSN3[%016lx]\n",
1194 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1195 info->icache_data[0],
1196 info->icache_data[1],
1197 info->icache_data[2],
1198 info->icache_data[3]);
1199 printk("%s" "ERROR(%d): I-cache INSN4[%016lx] INSN5[%016lx] INSN6[%016lx] INSN7[%016lx]\n",
1200 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1201 info->icache_data[4],
1202 info->icache_data[5],
1203 info->icache_data[6],
1204 info->icache_data[7]);
1205 printk("%s" "ERROR(%d): E-cache idx[%x] tag[%016lx]\n",
1206 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1207 (int) info->ecache_index, info->ecache_tag);
1208 printk("%s" "ERROR(%d): E-cache data0[%016lx] data1[%016lx] data2[%016lx] data3[%016lx]\n",
1209 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1210 info->ecache_data[0],
1211 info->ecache_data[1],
1212 info->ecache_data[2],
1213 info->ecache_data[3]);
1214
1215 afsr = (afsr & ~hipri) & cheetah_afsr_errors;
1216 while (afsr != 0UL) {
1217 unsigned long bit = cheetah_get_hipri(afsr);
1218
1219 printk("%s" "ERROR: Multiple-error (%016lx) \"%s\"\n",
1220 (recoverable ? KERN_WARNING : KERN_CRIT),
1221 bit, cheetah_get_string(bit));
1222
1223 afsr &= ~bit;
1224 }
1225
1226 if (!recoverable)
1227 printk(KERN_CRIT "ERROR: This condition is not recoverable.\n");
1228 }
1229
1230 static int cheetah_recheck_errors(struct cheetah_err_info *logp)
1231 {
1232 unsigned long afsr, afar;
1233 int ret = 0;
1234
1235 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1236 : "=r" (afsr)
1237 : "i" (ASI_AFSR));
1238 if ((afsr & cheetah_afsr_errors) != 0) {
1239 if (logp != NULL) {
1240 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1241 : "=r" (afar)
1242 : "i" (ASI_AFAR));
1243 logp->afsr = afsr;
1244 logp->afar = afar;
1245 }
1246 ret = 1;
1247 }
1248 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1249 "membar #Sync\n\t"
1250 : : "r" (afsr), "i" (ASI_AFSR));
1251
1252 return ret;
1253 }
1254
1255 void cheetah_fecc_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1256 {
1257 struct cheetah_err_info local_snapshot, *p;
1258 int recoverable;
1259
1260 /* Flush E-cache */
1261 cheetah_flush_ecache();
1262
1263 p = cheetah_get_error_log(afsr);
1264 if (!p) {
1265 prom_printf("ERROR: Early Fast-ECC error afsr[%016lx] afar[%016lx]\n",
1266 afsr, afar);
1267 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1268 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1269 prom_halt();
1270 }
1271
1272 /* Grab snapshot of logged error. */
1273 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1274
1275 /* If the current trap snapshot does not match what the
1276 * trap handler passed along into our args, big trouble.
1277 * In such a case, mark the local copy as invalid.
1278 *
1279 * Else, it matches and we mark the afsr in the non-local
1280 * copy as invalid so we may log new error traps there.
1281 */
1282 if (p->afsr != afsr || p->afar != afar)
1283 local_snapshot.afsr = CHAFSR_INVALID;
1284 else
1285 p->afsr = CHAFSR_INVALID;
1286
1287 cheetah_flush_icache();
1288 cheetah_flush_dcache();
1289
1290 /* Re-enable I-cache/D-cache */
1291 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1292 "or %%g1, %1, %%g1\n\t"
1293 "stxa %%g1, [%%g0] %0\n\t"
1294 "membar #Sync"
1295 : /* no outputs */
1296 : "i" (ASI_DCU_CONTROL_REG),
1297 "i" (DCU_DC | DCU_IC)
1298 : "g1");
1299
1300 /* Re-enable error reporting */
1301 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1302 "or %%g1, %1, %%g1\n\t"
1303 "stxa %%g1, [%%g0] %0\n\t"
1304 "membar #Sync"
1305 : /* no outputs */
1306 : "i" (ASI_ESTATE_ERROR_EN),
1307 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1308 : "g1");
1309
1310 /* Decide if we can continue after handling this trap and
1311 * logging the error.
1312 */
1313 recoverable = 1;
1314 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1315 recoverable = 0;
1316
1317 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1318 * error was logged while we had error reporting traps disabled.
1319 */
1320 if (cheetah_recheck_errors(&local_snapshot)) {
1321 unsigned long new_afsr = local_snapshot.afsr;
1322
1323 /* If we got a new asynchronous error, die... */
1324 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1325 CHAFSR_WDU | CHAFSR_CPU |
1326 CHAFSR_IVU | CHAFSR_UE |
1327 CHAFSR_BERR | CHAFSR_TO))
1328 recoverable = 0;
1329 }
1330
1331 /* Log errors. */
1332 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1333
1334 if (!recoverable)
1335 panic("Irrecoverable Fast-ECC error trap.\n");
1336
1337 /* Flush E-cache to kick the error trap handlers out. */
1338 cheetah_flush_ecache();
1339 }
1340
1341 /* Try to fix a correctable error by pushing the line out from
1342 * the E-cache. Recheck error reporting registers to see if the
1343 * problem is intermittent.
1344 */
1345 static int cheetah_fix_ce(unsigned long physaddr)
1346 {
1347 unsigned long orig_estate;
1348 unsigned long alias1, alias2;
1349 int ret;
1350
1351 /* Make sure correctable error traps are disabled. */
1352 __asm__ __volatile__("ldxa [%%g0] %2, %0\n\t"
1353 "andn %0, %1, %%g1\n\t"
1354 "stxa %%g1, [%%g0] %2\n\t"
1355 "membar #Sync"
1356 : "=&r" (orig_estate)
1357 : "i" (ESTATE_ERROR_CEEN),
1358 "i" (ASI_ESTATE_ERROR_EN)
1359 : "g1");
1360
1361 /* We calculate alias addresses that will force the
1362 * cache line in question out of the E-cache. Then
1363 * we bring it back in with an atomic instruction so
1364 * that we get it in some modified/exclusive state,
1365 * then we displace it again to try and get proper ECC
1366 * pushed back into the system.
1367 */
1368 physaddr &= ~(8UL - 1UL);
1369 alias1 = (ecache_flush_physbase +
1370 (physaddr & ((ecache_flush_size >> 1) - 1)));
1371 alias2 = alias1 + (ecache_flush_size >> 1);
1372 __asm__ __volatile__("ldxa [%0] %3, %%g0\n\t"
1373 "ldxa [%1] %3, %%g0\n\t"
1374 "casxa [%2] %3, %%g0, %%g0\n\t"
1375 "membar #StoreLoad | #StoreStore\n\t"
1376 "ldxa [%0] %3, %%g0\n\t"
1377 "ldxa [%1] %3, %%g0\n\t"
1378 "membar #Sync"
1379 : /* no outputs */
1380 : "r" (alias1), "r" (alias2),
1381 "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1382
1383 /* Did that trigger another error? */
1384 if (cheetah_recheck_errors(NULL)) {
1385 /* Try one more time. */
1386 __asm__ __volatile__("ldxa [%0] %1, %%g0\n\t"
1387 "membar #Sync"
1388 : : "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1389 if (cheetah_recheck_errors(NULL))
1390 ret = 2;
1391 else
1392 ret = 1;
1393 } else {
1394 /* No new error, intermittent problem. */
1395 ret = 0;
1396 }
1397
1398 /* Restore error enables. */
1399 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1400 "membar #Sync"
1401 : : "r" (orig_estate), "i" (ASI_ESTATE_ERROR_EN));
1402
1403 return ret;
1404 }
1405
1406 /* Return non-zero if PADDR is a valid physical memory address. */
1407 static int cheetah_check_main_memory(unsigned long paddr)
1408 {
1409 unsigned long vaddr = PAGE_OFFSET + paddr;
1410
1411 if (vaddr > (unsigned long) high_memory)
1412 return 0;
1413
1414 return kern_addr_valid(vaddr);
1415 }
1416
1417 void cheetah_cee_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1418 {
1419 struct cheetah_err_info local_snapshot, *p;
1420 int recoverable, is_memory;
1421
1422 p = cheetah_get_error_log(afsr);
1423 if (!p) {
1424 prom_printf("ERROR: Early CEE error afsr[%016lx] afar[%016lx]\n",
1425 afsr, afar);
1426 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1427 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1428 prom_halt();
1429 }
1430
1431 /* Grab snapshot of logged error. */
1432 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1433
1434 /* If the current trap snapshot does not match what the
1435 * trap handler passed along into our args, big trouble.
1436 * In such a case, mark the local copy as invalid.
1437 *
1438 * Else, it matches and we mark the afsr in the non-local
1439 * copy as invalid so we may log new error traps there.
1440 */
1441 if (p->afsr != afsr || p->afar != afar)
1442 local_snapshot.afsr = CHAFSR_INVALID;
1443 else
1444 p->afsr = CHAFSR_INVALID;
1445
1446 is_memory = cheetah_check_main_memory(afar);
1447
1448 if (is_memory && (afsr & CHAFSR_CE) != 0UL) {
1449 /* XXX Might want to log the results of this operation
1450 * XXX somewhere... -DaveM
1451 */
1452 cheetah_fix_ce(afar);
1453 }
1454
1455 {
1456 int flush_all, flush_line;
1457
1458 flush_all = flush_line = 0;
1459 if ((afsr & CHAFSR_EDC) != 0UL) {
1460 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDC)
1461 flush_line = 1;
1462 else
1463 flush_all = 1;
1464 } else if ((afsr & CHAFSR_CPC) != 0UL) {
1465 if ((afsr & cheetah_afsr_errors) == CHAFSR_CPC)
1466 flush_line = 1;
1467 else
1468 flush_all = 1;
1469 }
1470
1471 /* Trap handler only disabled I-cache, flush it. */
1472 cheetah_flush_icache();
1473
1474 /* Re-enable I-cache */
1475 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1476 "or %%g1, %1, %%g1\n\t"
1477 "stxa %%g1, [%%g0] %0\n\t"
1478 "membar #Sync"
1479 : /* no outputs */
1480 : "i" (ASI_DCU_CONTROL_REG),
1481 "i" (DCU_IC)
1482 : "g1");
1483
1484 if (flush_all)
1485 cheetah_flush_ecache();
1486 else if (flush_line)
1487 cheetah_flush_ecache_line(afar);
1488 }
1489
1490 /* Re-enable error reporting */
1491 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1492 "or %%g1, %1, %%g1\n\t"
1493 "stxa %%g1, [%%g0] %0\n\t"
1494 "membar #Sync"
1495 : /* no outputs */
1496 : "i" (ASI_ESTATE_ERROR_EN),
1497 "i" (ESTATE_ERROR_CEEN)
1498 : "g1");
1499
1500 /* Decide if we can continue after handling this trap and
1501 * logging the error.
1502 */
1503 recoverable = 1;
1504 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1505 recoverable = 0;
1506
1507 /* Re-check AFSR/AFAR */
1508 (void) cheetah_recheck_errors(&local_snapshot);
1509
1510 /* Log errors. */
1511 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1512
1513 if (!recoverable)
1514 panic("Irrecoverable Correctable-ECC error trap.\n");
1515 }
1516
1517 void cheetah_deferred_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1518 {
1519 struct cheetah_err_info local_snapshot, *p;
1520 int recoverable, is_memory;
1521
1522 #ifdef CONFIG_PCI
1523 /* Check for the special PCI poke sequence. */
1524 if (pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
1525 cheetah_flush_icache();
1526 cheetah_flush_dcache();
1527
1528 /* Re-enable I-cache/D-cache */
1529 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1530 "or %%g1, %1, %%g1\n\t"
1531 "stxa %%g1, [%%g0] %0\n\t"
1532 "membar #Sync"
1533 : /* no outputs */
1534 : "i" (ASI_DCU_CONTROL_REG),
1535 "i" (DCU_DC | DCU_IC)
1536 : "g1");
1537
1538 /* Re-enable error reporting */
1539 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1540 "or %%g1, %1, %%g1\n\t"
1541 "stxa %%g1, [%%g0] %0\n\t"
1542 "membar #Sync"
1543 : /* no outputs */
1544 : "i" (ASI_ESTATE_ERROR_EN),
1545 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1546 : "g1");
1547
1548 (void) cheetah_recheck_errors(NULL);
1549
1550 pci_poke_faulted = 1;
1551 regs->tpc += 4;
1552 regs->tnpc = regs->tpc + 4;
1553 return;
1554 }
1555 #endif
1556
1557 p = cheetah_get_error_log(afsr);
1558 if (!p) {
1559 prom_printf("ERROR: Early deferred error afsr[%016lx] afar[%016lx]\n",
1560 afsr, afar);
1561 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1562 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1563 prom_halt();
1564 }
1565
1566 /* Grab snapshot of logged error. */
1567 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1568
1569 /* If the current trap snapshot does not match what the
1570 * trap handler passed along into our args, big trouble.
1571 * In such a case, mark the local copy as invalid.
1572 *
1573 * Else, it matches and we mark the afsr in the non-local
1574 * copy as invalid so we may log new error traps there.
1575 */
1576 if (p->afsr != afsr || p->afar != afar)
1577 local_snapshot.afsr = CHAFSR_INVALID;
1578 else
1579 p->afsr = CHAFSR_INVALID;
1580
1581 is_memory = cheetah_check_main_memory(afar);
1582
1583 {
1584 int flush_all, flush_line;
1585
1586 flush_all = flush_line = 0;
1587 if ((afsr & CHAFSR_EDU) != 0UL) {
1588 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDU)
1589 flush_line = 1;
1590 else
1591 flush_all = 1;
1592 } else if ((afsr & CHAFSR_BERR) != 0UL) {
1593 if ((afsr & cheetah_afsr_errors) == CHAFSR_BERR)
1594 flush_line = 1;
1595 else
1596 flush_all = 1;
1597 }
1598
1599 cheetah_flush_icache();
1600 cheetah_flush_dcache();
1601
1602 /* Re-enable I/D caches */
1603 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1604 "or %%g1, %1, %%g1\n\t"
1605 "stxa %%g1, [%%g0] %0\n\t"
1606 "membar #Sync"
1607 : /* no outputs */
1608 : "i" (ASI_DCU_CONTROL_REG),
1609 "i" (DCU_IC | DCU_DC)
1610 : "g1");
1611
1612 if (flush_all)
1613 cheetah_flush_ecache();
1614 else if (flush_line)
1615 cheetah_flush_ecache_line(afar);
1616 }
1617
1618 /* Re-enable error reporting */
1619 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1620 "or %%g1, %1, %%g1\n\t"
1621 "stxa %%g1, [%%g0] %0\n\t"
1622 "membar #Sync"
1623 : /* no outputs */
1624 : "i" (ASI_ESTATE_ERROR_EN),
1625 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1626 : "g1");
1627
1628 /* Decide if we can continue after handling this trap and
1629 * logging the error.
1630 */
1631 recoverable = 1;
1632 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1633 recoverable = 0;
1634
1635 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1636 * error was logged while we had error reporting traps disabled.
1637 */
1638 if (cheetah_recheck_errors(&local_snapshot)) {
1639 unsigned long new_afsr = local_snapshot.afsr;
1640
1641 /* If we got a new asynchronous error, die... */
1642 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1643 CHAFSR_WDU | CHAFSR_CPU |
1644 CHAFSR_IVU | CHAFSR_UE |
1645 CHAFSR_BERR | CHAFSR_TO))
1646 recoverable = 0;
1647 }
1648
1649 /* Log errors. */
1650 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1651
1652 /* "Recoverable" here means we try to yank the page from ever
1653 * being newly used again. This depends upon a few things:
1654 * 1) Must be main memory, and AFAR must be valid.
1655 * 2) If we trapped from user, OK.
1656 * 3) Else, if we trapped from kernel we must find exception
1657 * table entry (ie. we have to have been accessing user
1658 * space).
1659 *
1660 * If AFAR is not in main memory, or we trapped from kernel
1661 * and cannot find an exception table entry, it is unacceptable
1662 * to try and continue.
1663 */
1664 if (recoverable && is_memory) {
1665 if ((regs->tstate & TSTATE_PRIV) == 0UL) {
1666 /* OK, usermode access. */
1667 recoverable = 1;
1668 } else {
1669 const struct exception_table_entry *entry;
1670
1671 entry = search_exception_tables(regs->tpc);
1672 if (entry) {
1673 /* OK, kernel access to userspace. */
1674 recoverable = 1;
1675
1676 } else {
1677 /* BAD, privileged state is corrupted. */
1678 recoverable = 0;
1679 }
1680
1681 if (recoverable) {
1682 if (pfn_valid(afar >> PAGE_SHIFT))
1683 get_page(pfn_to_page(afar >> PAGE_SHIFT));
1684 else
1685 recoverable = 0;
1686
1687 /* Only perform fixup if we still have a
1688 * recoverable condition.
1689 */
1690 if (recoverable) {
1691 regs->tpc = entry->fixup;
1692 regs->tnpc = regs->tpc + 4;
1693 }
1694 }
1695 }
1696 } else {
1697 recoverable = 0;
1698 }
1699
1700 if (!recoverable)
1701 panic("Irrecoverable deferred error trap.\n");
1702 }
1703
1704 /* Handle a D/I cache parity error trap. TYPE is encoded as:
1705 *
1706 * Bit0: 0=dcache,1=icache
1707 * Bit1: 0=recoverable,1=unrecoverable
1708 *
1709 * The hardware has disabled both the I-cache and D-cache in
1710 * the %dcr register.
1711 */
1712 void cheetah_plus_parity_error(int type, struct pt_regs *regs)
1713 {
1714 if (type & 0x1)
1715 __cheetah_flush_icache();
1716 else
1717 cheetah_plus_zap_dcache_parity();
1718 cheetah_flush_dcache();
1719
1720 /* Re-enable I-cache/D-cache */
1721 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1722 "or %%g1, %1, %%g1\n\t"
1723 "stxa %%g1, [%%g0] %0\n\t"
1724 "membar #Sync"
1725 : /* no outputs */
1726 : "i" (ASI_DCU_CONTROL_REG),
1727 "i" (DCU_DC | DCU_IC)
1728 : "g1");
1729
1730 if (type & 0x2) {
1731 printk(KERN_EMERG "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1732 smp_processor_id(),
1733 (type & 0x1) ? 'I' : 'D',
1734 regs->tpc);
1735 print_symbol(KERN_EMERG "TPC<%s>\n", regs->tpc);
1736 panic("Irrecoverable Cheetah+ parity error.");
1737 }
1738
1739 printk(KERN_WARNING "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1740 smp_processor_id(),
1741 (type & 0x1) ? 'I' : 'D',
1742 regs->tpc);
1743 print_symbol(KERN_WARNING "TPC<%s>\n", regs->tpc);
1744 }
1745
1746 struct sun4v_error_entry {
1747 u64 err_handle;
1748 u64 err_stick;
1749
1750 u32 err_type;
1751 #define SUN4V_ERR_TYPE_UNDEFINED 0
1752 #define SUN4V_ERR_TYPE_UNCORRECTED_RES 1
1753 #define SUN4V_ERR_TYPE_PRECISE_NONRES 2
1754 #define SUN4V_ERR_TYPE_DEFERRED_NONRES 3
1755 #define SUN4V_ERR_TYPE_WARNING_RES 4
1756
1757 u32 err_attrs;
1758 #define SUN4V_ERR_ATTRS_PROCESSOR 0x00000001
1759 #define SUN4V_ERR_ATTRS_MEMORY 0x00000002
1760 #define SUN4V_ERR_ATTRS_PIO 0x00000004
1761 #define SUN4V_ERR_ATTRS_INT_REGISTERS 0x00000008
1762 #define SUN4V_ERR_ATTRS_FPU_REGISTERS 0x00000010
1763 #define SUN4V_ERR_ATTRS_USER_MODE 0x01000000
1764 #define SUN4V_ERR_ATTRS_PRIV_MODE 0x02000000
1765 #define SUN4V_ERR_ATTRS_RES_QUEUE_FULL 0x80000000
1766
1767 u64 err_raddr;
1768 u32 err_size;
1769 u16 err_cpu;
1770 u16 err_pad;
1771 };
1772
1773 static atomic_t sun4v_resum_oflow_cnt = ATOMIC_INIT(0);
1774 static atomic_t sun4v_nonresum_oflow_cnt = ATOMIC_INIT(0);
1775
1776 static const char *sun4v_err_type_to_str(u32 type)
1777 {
1778 switch (type) {
1779 case SUN4V_ERR_TYPE_UNDEFINED:
1780 return "undefined";
1781 case SUN4V_ERR_TYPE_UNCORRECTED_RES:
1782 return "uncorrected resumable";
1783 case SUN4V_ERR_TYPE_PRECISE_NONRES:
1784 return "precise nonresumable";
1785 case SUN4V_ERR_TYPE_DEFERRED_NONRES:
1786 return "deferred nonresumable";
1787 case SUN4V_ERR_TYPE_WARNING_RES:
1788 return "warning resumable";
1789 default:
1790 return "unknown";
1791 };
1792 }
1793
1794 extern void __show_regs(struct pt_regs * regs);
1795
1796 static void sun4v_log_error(struct pt_regs *regs, struct sun4v_error_entry *ent, int cpu, const char *pfx, atomic_t *ocnt)
1797 {
1798 int cnt;
1799
1800 printk("%s: Reporting on cpu %d\n", pfx, cpu);
1801 printk("%s: err_handle[%lx] err_stick[%lx] err_type[%08x:%s]\n",
1802 pfx,
1803 ent->err_handle, ent->err_stick,
1804 ent->err_type,
1805 sun4v_err_type_to_str(ent->err_type));
1806 printk("%s: err_attrs[%08x:%s %s %s %s %s %s %s %s]\n",
1807 pfx,
1808 ent->err_attrs,
1809 ((ent->err_attrs & SUN4V_ERR_ATTRS_PROCESSOR) ?
1810 "processor" : ""),
1811 ((ent->err_attrs & SUN4V_ERR_ATTRS_MEMORY) ?
1812 "memory" : ""),
1813 ((ent->err_attrs & SUN4V_ERR_ATTRS_PIO) ?
1814 "pio" : ""),
1815 ((ent->err_attrs & SUN4V_ERR_ATTRS_INT_REGISTERS) ?
1816 "integer-regs" : ""),
1817 ((ent->err_attrs & SUN4V_ERR_ATTRS_FPU_REGISTERS) ?
1818 "fpu-regs" : ""),
1819 ((ent->err_attrs & SUN4V_ERR_ATTRS_USER_MODE) ?
1820 "user" : ""),
1821 ((ent->err_attrs & SUN4V_ERR_ATTRS_PRIV_MODE) ?
1822 "privileged" : ""),
1823 ((ent->err_attrs & SUN4V_ERR_ATTRS_RES_QUEUE_FULL) ?
1824 "queue-full" : ""));
1825 printk("%s: err_raddr[%016lx] err_size[%u] err_cpu[%u]\n",
1826 pfx,
1827 ent->err_raddr, ent->err_size, ent->err_cpu);
1828
1829 __show_regs(regs);
1830
1831 if ((cnt = atomic_read(ocnt)) != 0) {
1832 atomic_set(ocnt, 0);
1833 wmb();
1834 printk("%s: Queue overflowed %d times.\n",
1835 pfx, cnt);
1836 }
1837 }
1838
1839 /* We run with %pil set to 15 and PSTATE_IE enabled in %pstate.
1840 * Log the event and clear the first word of the entry.
1841 */
1842 void sun4v_resum_error(struct pt_regs *regs, unsigned long offset)
1843 {
1844 struct sun4v_error_entry *ent, local_copy;
1845 struct trap_per_cpu *tb;
1846 unsigned long paddr;
1847 int cpu;
1848
1849 cpu = get_cpu();
1850
1851 tb = &trap_block[cpu];
1852 paddr = tb->resum_kernel_buf_pa + offset;
1853 ent = __va(paddr);
1854
1855 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
1856
1857 /* We have a local copy now, so release the entry. */
1858 ent->err_handle = 0;
1859 wmb();
1860
1861 put_cpu();
1862
1863 if (ent->err_type == SUN4V_ERR_TYPE_WARNING_RES) {
1864 /* If err_type is 0x4, it's a powerdown request. Do
1865 * not do the usual resumable error log because that
1866 * makes it look like some abnormal error.
1867 */
1868 printk(KERN_INFO "Power down request...\n");
1869 kill_cad_pid(SIGINT, 1);
1870 return;
1871 }
1872
1873 sun4v_log_error(regs, &local_copy, cpu,
1874 KERN_ERR "RESUMABLE ERROR",
1875 &sun4v_resum_oflow_cnt);
1876 }
1877
1878 /* If we try to printk() we'll probably make matters worse, by trying
1879 * to retake locks this cpu already holds or causing more errors. So
1880 * just bump a counter, and we'll report these counter bumps above.
1881 */
1882 void sun4v_resum_overflow(struct pt_regs *regs)
1883 {
1884 atomic_inc(&sun4v_resum_oflow_cnt);
1885 }
1886
1887 /* We run with %pil set to 15 and PSTATE_IE enabled in %pstate.
1888 * Log the event, clear the first word of the entry, and die.
1889 */
1890 void sun4v_nonresum_error(struct pt_regs *regs, unsigned long offset)
1891 {
1892 struct sun4v_error_entry *ent, local_copy;
1893 struct trap_per_cpu *tb;
1894 unsigned long paddr;
1895 int cpu;
1896
1897 cpu = get_cpu();
1898
1899 tb = &trap_block[cpu];
1900 paddr = tb->nonresum_kernel_buf_pa + offset;
1901 ent = __va(paddr);
1902
1903 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
1904
1905 /* We have a local copy now, so release the entry. */
1906 ent->err_handle = 0;
1907 wmb();
1908
1909 put_cpu();
1910
1911 #ifdef CONFIG_PCI
1912 /* Check for the special PCI poke sequence. */
1913 if (pci_poke_in_progress && pci_poke_cpu == cpu) {
1914 pci_poke_faulted = 1;
1915 regs->tpc += 4;
1916 regs->tnpc = regs->tpc + 4;
1917 return;
1918 }
1919 #endif
1920
1921 sun4v_log_error(regs, &local_copy, cpu,
1922 KERN_EMERG "NON-RESUMABLE ERROR",
1923 &sun4v_nonresum_oflow_cnt);
1924
1925 panic("Non-resumable error.");
1926 }
1927
1928 /* If we try to printk() we'll probably make matters worse, by trying
1929 * to retake locks this cpu already holds or causing more errors. So
1930 * just bump a counter, and we'll report these counter bumps above.
1931 */
1932 void sun4v_nonresum_overflow(struct pt_regs *regs)
1933 {
1934 /* XXX Actually even this can make not that much sense. Perhaps
1935 * XXX we should just pull the plug and panic directly from here?
1936 */
1937 atomic_inc(&sun4v_nonresum_oflow_cnt);
1938 }
1939
1940 unsigned long sun4v_err_itlb_vaddr;
1941 unsigned long sun4v_err_itlb_ctx;
1942 unsigned long sun4v_err_itlb_pte;
1943 unsigned long sun4v_err_itlb_error;
1944
1945 void sun4v_itlb_error_report(struct pt_regs *regs, int tl)
1946 {
1947 if (tl > 1)
1948 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
1949
1950 printk(KERN_EMERG "SUN4V-ITLB: Error at TPC[%lx], tl %d\n",
1951 regs->tpc, tl);
1952 print_symbol(KERN_EMERG "SUN4V-ITLB: TPC<%s>\n", regs->tpc);
1953 printk(KERN_EMERG "SUN4V-ITLB: vaddr[%lx] ctx[%lx] "
1954 "pte[%lx] error[%lx]\n",
1955 sun4v_err_itlb_vaddr, sun4v_err_itlb_ctx,
1956 sun4v_err_itlb_pte, sun4v_err_itlb_error);
1957
1958 prom_halt();
1959 }
1960
1961 unsigned long sun4v_err_dtlb_vaddr;
1962 unsigned long sun4v_err_dtlb_ctx;
1963 unsigned long sun4v_err_dtlb_pte;
1964 unsigned long sun4v_err_dtlb_error;
1965
1966 void sun4v_dtlb_error_report(struct pt_regs *regs, int tl)
1967 {
1968 if (tl > 1)
1969 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
1970
1971 printk(KERN_EMERG "SUN4V-DTLB: Error at TPC[%lx], tl %d\n",
1972 regs->tpc, tl);
1973 print_symbol(KERN_EMERG "SUN4V-DTLB: TPC<%s>\n", regs->tpc);
1974 printk(KERN_EMERG "SUN4V-DTLB: vaddr[%lx] ctx[%lx] "
1975 "pte[%lx] error[%lx]\n",
1976 sun4v_err_dtlb_vaddr, sun4v_err_dtlb_ctx,
1977 sun4v_err_dtlb_pte, sun4v_err_dtlb_error);
1978
1979 prom_halt();
1980 }
1981
1982 void hypervisor_tlbop_error(unsigned long err, unsigned long op)
1983 {
1984 printk(KERN_CRIT "SUN4V: TLB hv call error %lu for op %lu\n",
1985 err, op);
1986 }
1987
1988 void hypervisor_tlbop_error_xcall(unsigned long err, unsigned long op)
1989 {
1990 printk(KERN_CRIT "SUN4V: XCALL TLB hv call error %lu for op %lu\n",
1991 err, op);
1992 }
1993
1994 void do_fpe_common(struct pt_regs *regs)
1995 {
1996 if (regs->tstate & TSTATE_PRIV) {
1997 regs->tpc = regs->tnpc;
1998 regs->tnpc += 4;
1999 } else {
2000 unsigned long fsr = current_thread_info()->xfsr[0];
2001 siginfo_t info;
2002
2003 if (test_thread_flag(TIF_32BIT)) {
2004 regs->tpc &= 0xffffffff;
2005 regs->tnpc &= 0xffffffff;
2006 }
2007 info.si_signo = SIGFPE;
2008 info.si_errno = 0;
2009 info.si_addr = (void __user *)regs->tpc;
2010 info.si_trapno = 0;
2011 info.si_code = __SI_FAULT;
2012 if ((fsr & 0x1c000) == (1 << 14)) {
2013 if (fsr & 0x10)
2014 info.si_code = FPE_FLTINV;
2015 else if (fsr & 0x08)
2016 info.si_code = FPE_FLTOVF;
2017 else if (fsr & 0x04)
2018 info.si_code = FPE_FLTUND;
2019 else if (fsr & 0x02)
2020 info.si_code = FPE_FLTDIV;
2021 else if (fsr & 0x01)
2022 info.si_code = FPE_FLTRES;
2023 }
2024 force_sig_info(SIGFPE, &info, current);
2025 }
2026 }
2027
2028 void do_fpieee(struct pt_regs *regs)
2029 {
2030 if (notify_die(DIE_TRAP, "fpu exception ieee", regs,
2031 0, 0x24, SIGFPE) == NOTIFY_STOP)
2032 return;
2033
2034 do_fpe_common(regs);
2035 }
2036
2037 extern int do_mathemu(struct pt_regs *, struct fpustate *);
2038
2039 void do_fpother(struct pt_regs *regs)
2040 {
2041 struct fpustate *f = FPUSTATE;
2042 int ret = 0;
2043
2044 if (notify_die(DIE_TRAP, "fpu exception other", regs,
2045 0, 0x25, SIGFPE) == NOTIFY_STOP)
2046 return;
2047
2048 switch ((current_thread_info()->xfsr[0] & 0x1c000)) {
2049 case (2 << 14): /* unfinished_FPop */
2050 case (3 << 14): /* unimplemented_FPop */
2051 ret = do_mathemu(regs, f);
2052 break;
2053 }
2054 if (ret)
2055 return;
2056 do_fpe_common(regs);
2057 }
2058
2059 void do_tof(struct pt_regs *regs)
2060 {
2061 siginfo_t info;
2062
2063 if (notify_die(DIE_TRAP, "tagged arithmetic overflow", regs,
2064 0, 0x26, SIGEMT) == NOTIFY_STOP)
2065 return;
2066
2067 if (regs->tstate & TSTATE_PRIV)
2068 die_if_kernel("Penguin overflow trap from kernel mode", regs);
2069 if (test_thread_flag(TIF_32BIT)) {
2070 regs->tpc &= 0xffffffff;
2071 regs->tnpc &= 0xffffffff;
2072 }
2073 info.si_signo = SIGEMT;
2074 info.si_errno = 0;
2075 info.si_code = EMT_TAGOVF;
2076 info.si_addr = (void __user *)regs->tpc;
2077 info.si_trapno = 0;
2078 force_sig_info(SIGEMT, &info, current);
2079 }
2080
2081 void do_div0(struct pt_regs *regs)
2082 {
2083 siginfo_t info;
2084
2085 if (notify_die(DIE_TRAP, "integer division by zero", regs,
2086 0, 0x28, SIGFPE) == NOTIFY_STOP)
2087 return;
2088
2089 if (regs->tstate & TSTATE_PRIV)
2090 die_if_kernel("TL0: Kernel divide by zero.", regs);
2091 if (test_thread_flag(TIF_32BIT)) {
2092 regs->tpc &= 0xffffffff;
2093 regs->tnpc &= 0xffffffff;
2094 }
2095 info.si_signo = SIGFPE;
2096 info.si_errno = 0;
2097 info.si_code = FPE_INTDIV;
2098 info.si_addr = (void __user *)regs->tpc;
2099 info.si_trapno = 0;
2100 force_sig_info(SIGFPE, &info, current);
2101 }
2102
2103 void instruction_dump (unsigned int *pc)
2104 {
2105 int i;
2106
2107 if ((((unsigned long) pc) & 3))
2108 return;
2109
2110 printk("Instruction DUMP:");
2111 for (i = -3; i < 6; i++)
2112 printk("%c%08x%c",i?' ':'<',pc[i],i?' ':'>');
2113 printk("\n");
2114 }
2115
2116 static void user_instruction_dump (unsigned int __user *pc)
2117 {
2118 int i;
2119 unsigned int buf[9];
2120
2121 if ((((unsigned long) pc) & 3))
2122 return;
2123
2124 if (copy_from_user(buf, pc - 3, sizeof(buf)))
2125 return;
2126
2127 printk("Instruction DUMP:");
2128 for (i = 0; i < 9; i++)
2129 printk("%c%08x%c",i==3?' ':'<',buf[i],i==3?' ':'>');
2130 printk("\n");
2131 }
2132
2133 void show_stack(struct task_struct *tsk, unsigned long *_ksp)
2134 {
2135 unsigned long pc, fp, thread_base, ksp;
2136 void *tp = task_stack_page(tsk);
2137 struct reg_window *rw;
2138 int count = 0;
2139
2140 ksp = (unsigned long) _ksp;
2141
2142 if (tp == current_thread_info())
2143 flushw_all();
2144
2145 fp = ksp + STACK_BIAS;
2146 thread_base = (unsigned long) tp;
2147
2148 printk("Call Trace:");
2149 #ifdef CONFIG_KALLSYMS
2150 printk("\n");
2151 #endif
2152 do {
2153 /* Bogus frame pointer? */
2154 if (fp < (thread_base + sizeof(struct thread_info)) ||
2155 fp >= (thread_base + THREAD_SIZE))
2156 break;
2157 rw = (struct reg_window *)fp;
2158 pc = rw->ins[7];
2159 printk(" [%016lx] ", pc);
2160 print_symbol("%s\n", pc);
2161 fp = rw->ins[6] + STACK_BIAS;
2162 } while (++count < 16);
2163 #ifndef CONFIG_KALLSYMS
2164 printk("\n");
2165 #endif
2166 }
2167
2168 void dump_stack(void)
2169 {
2170 unsigned long *ksp;
2171
2172 __asm__ __volatile__("mov %%fp, %0"
2173 : "=r" (ksp));
2174 show_stack(current, ksp);
2175 }
2176
2177 EXPORT_SYMBOL(dump_stack);
2178
2179 static inline int is_kernel_stack(struct task_struct *task,
2180 struct reg_window *rw)
2181 {
2182 unsigned long rw_addr = (unsigned long) rw;
2183 unsigned long thread_base, thread_end;
2184
2185 if (rw_addr < PAGE_OFFSET) {
2186 if (task != &init_task)
2187 return 0;
2188 }
2189
2190 thread_base = (unsigned long) task_stack_page(task);
2191 thread_end = thread_base + sizeof(union thread_union);
2192 if (rw_addr >= thread_base &&
2193 rw_addr < thread_end &&
2194 !(rw_addr & 0x7UL))
2195 return 1;
2196
2197 return 0;
2198 }
2199
2200 static inline struct reg_window *kernel_stack_up(struct reg_window *rw)
2201 {
2202 unsigned long fp = rw->ins[6];
2203
2204 if (!fp)
2205 return NULL;
2206
2207 return (struct reg_window *) (fp + STACK_BIAS);
2208 }
2209
2210 void die_if_kernel(char *str, struct pt_regs *regs)
2211 {
2212 static int die_counter;
2213 extern void smp_report_regs(void);
2214 int count = 0;
2215
2216 /* Amuse the user. */
2217 printk(
2218 " \\|/ ____ \\|/\n"
2219 " \"@'/ .. \\`@\"\n"
2220 " /_| \\__/ |_\\\n"
2221 " \\__U_/\n");
2222
2223 printk("%s(%d): %s [#%d]\n", current->comm, current->pid, str, ++die_counter);
2224 notify_die(DIE_OOPS, str, regs, 0, 255, SIGSEGV);
2225 __asm__ __volatile__("flushw");
2226 __show_regs(regs);
2227 if (regs->tstate & TSTATE_PRIV) {
2228 struct reg_window *rw = (struct reg_window *)
2229 (regs->u_regs[UREG_FP] + STACK_BIAS);
2230
2231 /* Stop the back trace when we hit userland or we
2232 * find some badly aligned kernel stack.
2233 */
2234 while (rw &&
2235 count++ < 30&&
2236 is_kernel_stack(current, rw)) {
2237 printk("Caller[%016lx]", rw->ins[7]);
2238 print_symbol(": %s", rw->ins[7]);
2239 printk("\n");
2240
2241 rw = kernel_stack_up(rw);
2242 }
2243 instruction_dump ((unsigned int *) regs->tpc);
2244 } else {
2245 if (test_thread_flag(TIF_32BIT)) {
2246 regs->tpc &= 0xffffffff;
2247 regs->tnpc &= 0xffffffff;
2248 }
2249 user_instruction_dump ((unsigned int __user *) regs->tpc);
2250 }
2251 #if 0
2252 #ifdef CONFIG_SMP
2253 smp_report_regs();
2254 #endif
2255 #endif
2256 if (regs->tstate & TSTATE_PRIV)
2257 do_exit(SIGKILL);
2258 do_exit(SIGSEGV);
2259 }
2260
2261 #define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19))
2262 #define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19))
2263
2264 extern int handle_popc(u32 insn, struct pt_regs *regs);
2265 extern int handle_ldf_stq(u32 insn, struct pt_regs *regs);
2266 extern int vis_emul(struct pt_regs *, unsigned int);
2267
2268 void do_illegal_instruction(struct pt_regs *regs)
2269 {
2270 unsigned long pc = regs->tpc;
2271 unsigned long tstate = regs->tstate;
2272 u32 insn;
2273 siginfo_t info;
2274
2275 if (notify_die(DIE_TRAP, "illegal instruction", regs,
2276 0, 0x10, SIGILL) == NOTIFY_STOP)
2277 return;
2278
2279 if (tstate & TSTATE_PRIV)
2280 die_if_kernel("Kernel illegal instruction", regs);
2281 if (test_thread_flag(TIF_32BIT))
2282 pc = (u32)pc;
2283 if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
2284 if ((insn & 0xc1ffc000) == 0x81700000) /* POPC */ {
2285 if (handle_popc(insn, regs))
2286 return;
2287 } else if ((insn & 0xc1580000) == 0xc1100000) /* LDQ/STQ */ {
2288 if (handle_ldf_stq(insn, regs))
2289 return;
2290 } else if (tlb_type == hypervisor) {
2291 if ((insn & VIS_OPCODE_MASK) == VIS_OPCODE_VAL) {
2292 if (!vis_emul(regs, insn))
2293 return;
2294 } else {
2295 struct fpustate *f = FPUSTATE;
2296
2297 /* XXX maybe verify XFSR bits like
2298 * XXX do_fpother() does?
2299 */
2300 if (do_mathemu(regs, f))
2301 return;
2302 }
2303 }
2304 }
2305 info.si_signo = SIGILL;
2306 info.si_errno = 0;
2307 info.si_code = ILL_ILLOPC;
2308 info.si_addr = (void __user *)pc;
2309 info.si_trapno = 0;
2310 force_sig_info(SIGILL, &info, current);
2311 }
2312
2313 extern void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn);
2314
2315 void mem_address_unaligned(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
2316 {
2317 siginfo_t info;
2318
2319 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2320 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2321 return;
2322
2323 if (regs->tstate & TSTATE_PRIV) {
2324 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2325 return;
2326 }
2327 info.si_signo = SIGBUS;
2328 info.si_errno = 0;
2329 info.si_code = BUS_ADRALN;
2330 info.si_addr = (void __user *)sfar;
2331 info.si_trapno = 0;
2332 force_sig_info(SIGBUS, &info, current);
2333 }
2334
2335 void sun4v_do_mna(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
2336 {
2337 siginfo_t info;
2338
2339 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2340 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2341 return;
2342
2343 if (regs->tstate & TSTATE_PRIV) {
2344 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2345 return;
2346 }
2347 info.si_signo = SIGBUS;
2348 info.si_errno = 0;
2349 info.si_code = BUS_ADRALN;
2350 info.si_addr = (void __user *) addr;
2351 info.si_trapno = 0;
2352 force_sig_info(SIGBUS, &info, current);
2353 }
2354
2355 void do_privop(struct pt_regs *regs)
2356 {
2357 siginfo_t info;
2358
2359 if (notify_die(DIE_TRAP, "privileged operation", regs,
2360 0, 0x11, SIGILL) == NOTIFY_STOP)
2361 return;
2362
2363 if (test_thread_flag(TIF_32BIT)) {
2364 regs->tpc &= 0xffffffff;
2365 regs->tnpc &= 0xffffffff;
2366 }
2367 info.si_signo = SIGILL;
2368 info.si_errno = 0;
2369 info.si_code = ILL_PRVOPC;
2370 info.si_addr = (void __user *)regs->tpc;
2371 info.si_trapno = 0;
2372 force_sig_info(SIGILL, &info, current);
2373 }
2374
2375 void do_privact(struct pt_regs *regs)
2376 {
2377 do_privop(regs);
2378 }
2379
2380 /* Trap level 1 stuff or other traps we should never see... */
2381 void do_cee(struct pt_regs *regs)
2382 {
2383 die_if_kernel("TL0: Cache Error Exception", regs);
2384 }
2385
2386 void do_cee_tl1(struct pt_regs *regs)
2387 {
2388 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2389 die_if_kernel("TL1: Cache Error Exception", regs);
2390 }
2391
2392 void do_dae_tl1(struct pt_regs *regs)
2393 {
2394 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2395 die_if_kernel("TL1: Data Access Exception", regs);
2396 }
2397
2398 void do_iae_tl1(struct pt_regs *regs)
2399 {
2400 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2401 die_if_kernel("TL1: Instruction Access Exception", regs);
2402 }
2403
2404 void do_div0_tl1(struct pt_regs *regs)
2405 {
2406 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2407 die_if_kernel("TL1: DIV0 Exception", regs);
2408 }
2409
2410 void do_fpdis_tl1(struct pt_regs *regs)
2411 {
2412 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2413 die_if_kernel("TL1: FPU Disabled", regs);
2414 }
2415
2416 void do_fpieee_tl1(struct pt_regs *regs)
2417 {
2418 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2419 die_if_kernel("TL1: FPU IEEE Exception", regs);
2420 }
2421
2422 void do_fpother_tl1(struct pt_regs *regs)
2423 {
2424 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2425 die_if_kernel("TL1: FPU Other Exception", regs);
2426 }
2427
2428 void do_ill_tl1(struct pt_regs *regs)
2429 {
2430 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2431 die_if_kernel("TL1: Illegal Instruction Exception", regs);
2432 }
2433
2434 void do_irq_tl1(struct pt_regs *regs)
2435 {
2436 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2437 die_if_kernel("TL1: IRQ Exception", regs);
2438 }
2439
2440 void do_lddfmna_tl1(struct pt_regs *regs)
2441 {
2442 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2443 die_if_kernel("TL1: LDDF Exception", regs);
2444 }
2445
2446 void do_stdfmna_tl1(struct pt_regs *regs)
2447 {
2448 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2449 die_if_kernel("TL1: STDF Exception", regs);
2450 }
2451
2452 void do_paw(struct pt_regs *regs)
2453 {
2454 die_if_kernel("TL0: Phys Watchpoint Exception", regs);
2455 }
2456
2457 void do_paw_tl1(struct pt_regs *regs)
2458 {
2459 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2460 die_if_kernel("TL1: Phys Watchpoint Exception", regs);
2461 }
2462
2463 void do_vaw(struct pt_regs *regs)
2464 {
2465 die_if_kernel("TL0: Virt Watchpoint Exception", regs);
2466 }
2467
2468 void do_vaw_tl1(struct pt_regs *regs)
2469 {
2470 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2471 die_if_kernel("TL1: Virt Watchpoint Exception", regs);
2472 }
2473
2474 void do_tof_tl1(struct pt_regs *regs)
2475 {
2476 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2477 die_if_kernel("TL1: Tag Overflow Exception", regs);
2478 }
2479
2480 void do_getpsr(struct pt_regs *regs)
2481 {
2482 regs->u_regs[UREG_I0] = tstate_to_psr(regs->tstate);
2483 regs->tpc = regs->tnpc;
2484 regs->tnpc += 4;
2485 if (test_thread_flag(TIF_32BIT)) {
2486 regs->tpc &= 0xffffffff;
2487 regs->tnpc &= 0xffffffff;
2488 }
2489 }
2490
2491 struct trap_per_cpu trap_block[NR_CPUS];
2492
2493 /* This can get invoked before sched_init() so play it super safe
2494 * and use hard_smp_processor_id().
2495 */
2496 void init_cur_cpu_trap(struct thread_info *t)
2497 {
2498 int cpu = hard_smp_processor_id();
2499 struct trap_per_cpu *p = &trap_block[cpu];
2500
2501 p->thread = t;
2502 p->pgd_paddr = 0;
2503 }
2504
2505 extern void thread_info_offsets_are_bolixed_dave(void);
2506 extern void trap_per_cpu_offsets_are_bolixed_dave(void);
2507 extern void tsb_config_offsets_are_bolixed_dave(void);
2508
2509 /* Only invoked on boot processor. */
2510 void __init trap_init(void)
2511 {
2512 /* Compile time sanity check. */
2513 if (TI_TASK != offsetof(struct thread_info, task) ||
2514 TI_FLAGS != offsetof(struct thread_info, flags) ||
2515 TI_CPU != offsetof(struct thread_info, cpu) ||
2516 TI_FPSAVED != offsetof(struct thread_info, fpsaved) ||
2517 TI_KSP != offsetof(struct thread_info, ksp) ||
2518 TI_FAULT_ADDR != offsetof(struct thread_info, fault_address) ||
2519 TI_KREGS != offsetof(struct thread_info, kregs) ||
2520 TI_UTRAPS != offsetof(struct thread_info, utraps) ||
2521 TI_EXEC_DOMAIN != offsetof(struct thread_info, exec_domain) ||
2522 TI_REG_WINDOW != offsetof(struct thread_info, reg_window) ||
2523 TI_RWIN_SPTRS != offsetof(struct thread_info, rwbuf_stkptrs) ||
2524 TI_GSR != offsetof(struct thread_info, gsr) ||
2525 TI_XFSR != offsetof(struct thread_info, xfsr) ||
2526 TI_USER_CNTD0 != offsetof(struct thread_info, user_cntd0) ||
2527 TI_USER_CNTD1 != offsetof(struct thread_info, user_cntd1) ||
2528 TI_KERN_CNTD0 != offsetof(struct thread_info, kernel_cntd0) ||
2529 TI_KERN_CNTD1 != offsetof(struct thread_info, kernel_cntd1) ||
2530 TI_PCR != offsetof(struct thread_info, pcr_reg) ||
2531 TI_PRE_COUNT != offsetof(struct thread_info, preempt_count) ||
2532 TI_NEW_CHILD != offsetof(struct thread_info, new_child) ||
2533 TI_SYS_NOERROR != offsetof(struct thread_info, syscall_noerror) ||
2534 TI_RESTART_BLOCK != offsetof(struct thread_info, restart_block) ||
2535 TI_KUNA_REGS != offsetof(struct thread_info, kern_una_regs) ||
2536 TI_KUNA_INSN != offsetof(struct thread_info, kern_una_insn) ||
2537 TI_FPREGS != offsetof(struct thread_info, fpregs) ||
2538 (TI_FPREGS & (64 - 1)))
2539 thread_info_offsets_are_bolixed_dave();
2540
2541 if (TRAP_PER_CPU_THREAD != offsetof(struct trap_per_cpu, thread) ||
2542 (TRAP_PER_CPU_PGD_PADDR !=
2543 offsetof(struct trap_per_cpu, pgd_paddr)) ||
2544 (TRAP_PER_CPU_CPU_MONDO_PA !=
2545 offsetof(struct trap_per_cpu, cpu_mondo_pa)) ||
2546 (TRAP_PER_CPU_DEV_MONDO_PA !=
2547 offsetof(struct trap_per_cpu, dev_mondo_pa)) ||
2548 (TRAP_PER_CPU_RESUM_MONDO_PA !=
2549 offsetof(struct trap_per_cpu, resum_mondo_pa)) ||
2550 (TRAP_PER_CPU_RESUM_KBUF_PA !=
2551 offsetof(struct trap_per_cpu, resum_kernel_buf_pa)) ||
2552 (TRAP_PER_CPU_NONRESUM_MONDO_PA !=
2553 offsetof(struct trap_per_cpu, nonresum_mondo_pa)) ||
2554 (TRAP_PER_CPU_NONRESUM_KBUF_PA !=
2555 offsetof(struct trap_per_cpu, nonresum_kernel_buf_pa)) ||
2556 (TRAP_PER_CPU_FAULT_INFO !=
2557 offsetof(struct trap_per_cpu, fault_info)) ||
2558 (TRAP_PER_CPU_CPU_MONDO_BLOCK_PA !=
2559 offsetof(struct trap_per_cpu, cpu_mondo_block_pa)) ||
2560 (TRAP_PER_CPU_CPU_LIST_PA !=
2561 offsetof(struct trap_per_cpu, cpu_list_pa)) ||
2562 (TRAP_PER_CPU_TSB_HUGE !=
2563 offsetof(struct trap_per_cpu, tsb_huge)) ||
2564 (TRAP_PER_CPU_TSB_HUGE_TEMP !=
2565 offsetof(struct trap_per_cpu, tsb_huge_temp)) ||
2566 (TRAP_PER_CPU_IRQ_WORKLIST !=
2567 offsetof(struct trap_per_cpu, irq_worklist)))
2568 trap_per_cpu_offsets_are_bolixed_dave();
2569
2570 if ((TSB_CONFIG_TSB !=
2571 offsetof(struct tsb_config, tsb)) ||
2572 (TSB_CONFIG_RSS_LIMIT !=
2573 offsetof(struct tsb_config, tsb_rss_limit)) ||
2574 (TSB_CONFIG_NENTRIES !=
2575 offsetof(struct tsb_config, tsb_nentries)) ||
2576 (TSB_CONFIG_REG_VAL !=
2577 offsetof(struct tsb_config, tsb_reg_val)) ||
2578 (TSB_CONFIG_MAP_VADDR !=
2579 offsetof(struct tsb_config, tsb_map_vaddr)) ||
2580 (TSB_CONFIG_MAP_PTE !=
2581 offsetof(struct tsb_config, tsb_map_pte)))
2582 tsb_config_offsets_are_bolixed_dave();
2583
2584 /* Attach to the address space of init_task. On SMP we
2585 * do this in smp.c:smp_callin for other cpus.
2586 */
2587 atomic_inc(&init_mm.mm_count);
2588 current->active_mm = &init_mm;
2589 }
Linux kernel - Deliverables
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