projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge master.kernel.org:/pub/scm/linux/kernel/git/jejb/scsi-misc-2.6
[deliverable/linux.git] / arch / sparc64 / kernel / traps.c
1 /* $Id: traps.c,v 1.85 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/kernel/traps.c
3 *
4 * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997,1999,2000 Jakub Jelinek (jakub@redhat.com)
6 */
7
8 /*
9 * I like traps on v9, :))))
10 */
11
12 #include <linux/module.h>
13 #include <linux/sched.h>
14 #include <linux/kernel.h>
15 #include <linux/kallsyms.h>
16 #include <linux/signal.h>
17 #include <linux/smp.h>
18 #include <linux/mm.h>
19 #include <linux/init.h>
20 #include <linux/kdebug.h>
21
22 #include <asm/delay.h>
23 #include <asm/system.h>
24 #include <asm/ptrace.h>
25 #include <asm/oplib.h>
26 #include <asm/page.h>
27 #include <asm/pgtable.h>
28 #include <asm/unistd.h>
29 #include <asm/uaccess.h>
30 #include <asm/fpumacro.h>
31 #include <asm/lsu.h>
32 #include <asm/dcu.h>
33 #include <asm/estate.h>
34 #include <asm/chafsr.h>
35 #include <asm/sfafsr.h>
36 #include <asm/psrcompat.h>
37 #include <asm/processor.h>
38 #include <asm/timer.h>
39 #include <asm/head.h>
40 #ifdef CONFIG_KMOD
41 #include <linux/kmod.h>
42 #endif
43 #include <asm/prom.h>
44
45
46 /* When an irrecoverable trap occurs at tl > 0, the trap entry
47 * code logs the trap state registers at every level in the trap
48 * stack. It is found at (pt_regs + sizeof(pt_regs)) and the layout
49 * is as follows:
50 */
51 struct tl1_traplog {
52 struct {
53 unsigned long tstate;
54 unsigned long tpc;
55 unsigned long tnpc;
56 unsigned long tt;
57 } trapstack[4];
58 unsigned long tl;
59 };
60
61 static void dump_tl1_traplog(struct tl1_traplog *p)
62 {
63 int i, limit;
64
65 printk(KERN_EMERG "TRAPLOG: Error at trap level 0x%lx, "
66 "dumping track stack.\n", p->tl);
67
68 limit = (tlb_type == hypervisor) ? 2 : 4;
69 for (i = 0; i < limit; i++) {
70 printk(KERN_EMERG
71 "TRAPLOG: Trap level %d TSTATE[%016lx] TPC[%016lx] "
72 "TNPC[%016lx] TT[%lx]\n",
73 i + 1,
74 p->trapstack[i].tstate, p->trapstack[i].tpc,
75 p->trapstack[i].tnpc, p->trapstack[i].tt);
76 print_symbol("TRAPLOG: TPC<%s>\n", p->trapstack[i].tpc);
77 }
78 }
79
80 void do_call_debug(struct pt_regs *regs)
81 {
82 notify_die(DIE_CALL, "debug call", regs, 0, 255, SIGINT);
83 }
84
85 void bad_trap(struct pt_regs *regs, long lvl)
86 {
87 char buffer[32];
88 siginfo_t info;
89
90 if (notify_die(DIE_TRAP, "bad trap", regs,
91 0, lvl, SIGTRAP) == NOTIFY_STOP)
92 return;
93
94 if (lvl < 0x100) {
95 sprintf(buffer, "Bad hw trap %lx at tl0\n", lvl);
96 die_if_kernel(buffer, regs);
97 }
98
99 lvl -= 0x100;
100 if (regs->tstate & TSTATE_PRIV) {
101 sprintf(buffer, "Kernel bad sw trap %lx", lvl);
102 die_if_kernel(buffer, regs);
103 }
104 if (test_thread_flag(TIF_32BIT)) {
105 regs->tpc &= 0xffffffff;
106 regs->tnpc &= 0xffffffff;
107 }
108 info.si_signo = SIGILL;
109 info.si_errno = 0;
110 info.si_code = ILL_ILLTRP;
111 info.si_addr = (void __user *)regs->tpc;
112 info.si_trapno = lvl;
113 force_sig_info(SIGILL, &info, current);
114 }
115
116 void bad_trap_tl1(struct pt_regs *regs, long lvl)
117 {
118 char buffer[32];
119
120 if (notify_die(DIE_TRAP_TL1, "bad trap tl1", regs,
121 0, lvl, SIGTRAP) == NOTIFY_STOP)
122 return;
123
124 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
125
126 sprintf (buffer, "Bad trap %lx at tl>0", lvl);
127 die_if_kernel (buffer, regs);
128 }
129
130 #ifdef CONFIG_DEBUG_BUGVERBOSE
131 void do_BUG(const char *file, int line)
132 {
133 bust_spinlocks(1);
134 printk("kernel BUG at %s:%d!\n", file, line);
135 }
136 #endif
137
138 void spitfire_insn_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
139 {
140 siginfo_t info;
141
142 if (notify_die(DIE_TRAP, "instruction access exception", regs,
143 0, 0x8, SIGTRAP) == NOTIFY_STOP)
144 return;
145
146 if (regs->tstate & TSTATE_PRIV) {
147 printk("spitfire_insn_access_exception: SFSR[%016lx] "
148 "SFAR[%016lx], going.\n", sfsr, sfar);
149 die_if_kernel("Iax", regs);
150 }
151 if (test_thread_flag(TIF_32BIT)) {
152 regs->tpc &= 0xffffffff;
153 regs->tnpc &= 0xffffffff;
154 }
155 info.si_signo = SIGSEGV;
156 info.si_errno = 0;
157 info.si_code = SEGV_MAPERR;
158 info.si_addr = (void __user *)regs->tpc;
159 info.si_trapno = 0;
160 force_sig_info(SIGSEGV, &info, current);
161 }
162
163 void spitfire_insn_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
164 {
165 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
166 0, 0x8, SIGTRAP) == NOTIFY_STOP)
167 return;
168
169 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
170 spitfire_insn_access_exception(regs, sfsr, sfar);
171 }
172
173 void sun4v_insn_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
174 {
175 unsigned short type = (type_ctx >> 16);
176 unsigned short ctx = (type_ctx & 0xffff);
177 siginfo_t info;
178
179 if (notify_die(DIE_TRAP, "instruction access exception", regs,
180 0, 0x8, SIGTRAP) == NOTIFY_STOP)
181 return;
182
183 if (regs->tstate & TSTATE_PRIV) {
184 printk("sun4v_insn_access_exception: ADDR[%016lx] "
185 "CTX[%04x] TYPE[%04x], going.\n",
186 addr, ctx, type);
187 die_if_kernel("Iax", regs);
188 }
189
190 if (test_thread_flag(TIF_32BIT)) {
191 regs->tpc &= 0xffffffff;
192 regs->tnpc &= 0xffffffff;
193 }
194 info.si_signo = SIGSEGV;
195 info.si_errno = 0;
196 info.si_code = SEGV_MAPERR;
197 info.si_addr = (void __user *) addr;
198 info.si_trapno = 0;
199 force_sig_info(SIGSEGV, &info, current);
200 }
201
202 void sun4v_insn_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
203 {
204 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
205 0, 0x8, SIGTRAP) == NOTIFY_STOP)
206 return;
207
208 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
209 sun4v_insn_access_exception(regs, addr, type_ctx);
210 }
211
212 void spitfire_data_access_exception(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
213 {
214 siginfo_t info;
215
216 if (notify_die(DIE_TRAP, "data access exception", regs,
217 0, 0x30, SIGTRAP) == NOTIFY_STOP)
218 return;
219
220 if (regs->tstate & TSTATE_PRIV) {
221 /* Test if this comes from uaccess places. */
222 const struct exception_table_entry *entry;
223
224 entry = search_exception_tables(regs->tpc);
225 if (entry) {
226 /* Ouch, somebody is trying VM hole tricks on us... */
227 #ifdef DEBUG_EXCEPTIONS
228 printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
229 printk("EX_TABLE: insn<%016lx> fixup<%016lx>\n",
230 regs->tpc, entry->fixup);
231 #endif
232 regs->tpc = entry->fixup;
233 regs->tnpc = regs->tpc + 4;
234 return;
235 }
236 /* Shit... */
237 printk("spitfire_data_access_exception: SFSR[%016lx] "
238 "SFAR[%016lx], going.\n", sfsr, sfar);
239 die_if_kernel("Dax", regs);
240 }
241
242 info.si_signo = SIGSEGV;
243 info.si_errno = 0;
244 info.si_code = SEGV_MAPERR;
245 info.si_addr = (void __user *)sfar;
246 info.si_trapno = 0;
247 force_sig_info(SIGSEGV, &info, current);
248 }
249
250 void spitfire_data_access_exception_tl1(struct pt_regs *regs, unsigned long sfsr, unsigned long sfar)
251 {
252 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
253 0, 0x30, SIGTRAP) == NOTIFY_STOP)
254 return;
255
256 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
257 spitfire_data_access_exception(regs, sfsr, sfar);
258 }
259
260 void sun4v_data_access_exception(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
261 {
262 unsigned short type = (type_ctx >> 16);
263 unsigned short ctx = (type_ctx & 0xffff);
264 siginfo_t info;
265
266 if (notify_die(DIE_TRAP, "data access exception", regs,
267 0, 0x8, SIGTRAP) == NOTIFY_STOP)
268 return;
269
270 if (regs->tstate & TSTATE_PRIV) {
271 printk("sun4v_data_access_exception: ADDR[%016lx] "
272 "CTX[%04x] TYPE[%04x], going.\n",
273 addr, ctx, type);
274 die_if_kernel("Dax", regs);
275 }
276
277 if (test_thread_flag(TIF_32BIT)) {
278 regs->tpc &= 0xffffffff;
279 regs->tnpc &= 0xffffffff;
280 }
281 info.si_signo = SIGSEGV;
282 info.si_errno = 0;
283 info.si_code = SEGV_MAPERR;
284 info.si_addr = (void __user *) addr;
285 info.si_trapno = 0;
286 force_sig_info(SIGSEGV, &info, current);
287 }
288
289 void sun4v_data_access_exception_tl1(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
290 {
291 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
292 0, 0x8, SIGTRAP) == NOTIFY_STOP)
293 return;
294
295 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
296 sun4v_data_access_exception(regs, addr, type_ctx);
297 }
298
299 #ifdef CONFIG_PCI
300 /* This is really pathetic... */
301 extern volatile int pci_poke_in_progress;
302 extern volatile int pci_poke_cpu;
303 extern volatile int pci_poke_faulted;
304 #endif
305
306 /* When access exceptions happen, we must do this. */
307 static void spitfire_clean_and_reenable_l1_caches(void)
308 {
309 unsigned long va;
310
311 if (tlb_type != spitfire)
312 BUG();
313
314 /* Clean 'em. */
315 for (va = 0; va < (PAGE_SIZE << 1); va += 32) {
316 spitfire_put_icache_tag(va, 0x0);
317 spitfire_put_dcache_tag(va, 0x0);
318 }
319
320 /* Re-enable in LSU. */
321 __asm__ __volatile__("flush %%g6\n\t"
322 "membar #Sync\n\t"
323 "stxa %0, [%%g0] %1\n\t"
324 "membar #Sync"
325 : /* no outputs */
326 : "r" (LSU_CONTROL_IC | LSU_CONTROL_DC |
327 LSU_CONTROL_IM | LSU_CONTROL_DM),
328 "i" (ASI_LSU_CONTROL)
329 : "memory");
330 }
331
332 static void spitfire_enable_estate_errors(void)
333 {
334 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
335 "membar #Sync"
336 : /* no outputs */
337 : "r" (ESTATE_ERR_ALL),
338 "i" (ASI_ESTATE_ERROR_EN));
339 }
340
341 static char ecc_syndrome_table[] = {
342 0x4c, 0x40, 0x41, 0x48, 0x42, 0x48, 0x48, 0x49,
343 0x43, 0x48, 0x48, 0x49, 0x48, 0x49, 0x49, 0x4a,
344 0x44, 0x48, 0x48, 0x20, 0x48, 0x39, 0x4b, 0x48,
345 0x48, 0x25, 0x31, 0x48, 0x28, 0x48, 0x48, 0x2c,
346 0x45, 0x48, 0x48, 0x21, 0x48, 0x3d, 0x04, 0x48,
347 0x48, 0x4b, 0x35, 0x48, 0x2d, 0x48, 0x48, 0x29,
348 0x48, 0x00, 0x01, 0x48, 0x0a, 0x48, 0x48, 0x4b,
349 0x0f, 0x48, 0x48, 0x4b, 0x48, 0x49, 0x49, 0x48,
350 0x46, 0x48, 0x48, 0x2a, 0x48, 0x3b, 0x27, 0x48,
351 0x48, 0x4b, 0x33, 0x48, 0x22, 0x48, 0x48, 0x2e,
352 0x48, 0x19, 0x1d, 0x48, 0x1b, 0x4a, 0x48, 0x4b,
353 0x1f, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
354 0x48, 0x4b, 0x24, 0x48, 0x07, 0x48, 0x48, 0x36,
355 0x4b, 0x48, 0x48, 0x3e, 0x48, 0x30, 0x38, 0x48,
356 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x16, 0x48,
357 0x48, 0x12, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
358 0x47, 0x48, 0x48, 0x2f, 0x48, 0x3f, 0x4b, 0x48,
359 0x48, 0x06, 0x37, 0x48, 0x23, 0x48, 0x48, 0x2b,
360 0x48, 0x05, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x32,
361 0x26, 0x48, 0x48, 0x3a, 0x48, 0x34, 0x3c, 0x48,
362 0x48, 0x11, 0x15, 0x48, 0x13, 0x4a, 0x48, 0x4b,
363 0x17, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
364 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x1e, 0x48,
365 0x48, 0x1a, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
366 0x48, 0x08, 0x0d, 0x48, 0x02, 0x48, 0x48, 0x49,
367 0x03, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x4b, 0x48,
368 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x10, 0x48,
369 0x48, 0x14, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
370 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x18, 0x48,
371 0x48, 0x1c, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
372 0x4a, 0x0c, 0x09, 0x48, 0x0e, 0x48, 0x48, 0x4b,
373 0x0b, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x4b, 0x4a
374 };
375
376 static char *syndrome_unknown = "<Unknown>";
377
378 static void spitfire_log_udb_syndrome(unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long bit)
379 {
380 unsigned short scode;
381 char memmod_str[64], *p;
382
383 if (udbl & bit) {
384 scode = ecc_syndrome_table[udbl & 0xff];
385 if (prom_getunumber(scode, afar,
386 memmod_str, sizeof(memmod_str)) == -1)
387 p = syndrome_unknown;
388 else
389 p = memmod_str;
390 printk(KERN_WARNING "CPU[%d]: UDBL Syndrome[%x] "
391 "Memory Module \"%s\"\n",
392 smp_processor_id(), scode, p);
393 }
394
395 if (udbh & bit) {
396 scode = ecc_syndrome_table[udbh & 0xff];
397 if (prom_getunumber(scode, afar,
398 memmod_str, sizeof(memmod_str)) == -1)
399 p = syndrome_unknown;
400 else
401 p = memmod_str;
402 printk(KERN_WARNING "CPU[%d]: UDBH Syndrome[%x] "
403 "Memory Module \"%s\"\n",
404 smp_processor_id(), scode, p);
405 }
406
407 }
408
409 static void spitfire_cee_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, int tl1, struct pt_regs *regs)
410 {
411
412 printk(KERN_WARNING "CPU[%d]: Correctable ECC Error "
413 "AFSR[%lx] AFAR[%016lx] UDBL[%lx] UDBH[%lx] TL>1[%d]\n",
414 smp_processor_id(), afsr, afar, udbl, udbh, tl1);
415
416 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_CE);
417
418 /* We always log it, even if someone is listening for this
419 * trap.
420 */
421 notify_die(DIE_TRAP, "Correctable ECC Error", regs,
422 0, TRAP_TYPE_CEE, SIGTRAP);
423
424 /* The Correctable ECC Error trap does not disable I/D caches. So
425 * we only have to restore the ESTATE Error Enable register.
426 */
427 spitfire_enable_estate_errors();
428 }
429
430 static void spitfire_ue_log(unsigned long afsr, unsigned long afar, unsigned long udbh, unsigned long udbl, unsigned long tt, int tl1, struct pt_regs *regs)
431 {
432 siginfo_t info;
433
434 printk(KERN_WARNING "CPU[%d]: Uncorrectable Error AFSR[%lx] "
435 "AFAR[%lx] UDBL[%lx] UDBH[%ld] TT[%lx] TL>1[%d]\n",
436 smp_processor_id(), afsr, afar, udbl, udbh, tt, tl1);
437
438 /* XXX add more human friendly logging of the error status
439 * XXX as is implemented for cheetah
440 */
441
442 spitfire_log_udb_syndrome(afar, udbh, udbl, UDBE_UE);
443
444 /* We always log it, even if someone is listening for this
445 * trap.
446 */
447 notify_die(DIE_TRAP, "Uncorrectable Error", regs,
448 0, tt, SIGTRAP);
449
450 if (regs->tstate & TSTATE_PRIV) {
451 if (tl1)
452 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
453 die_if_kernel("UE", regs);
454 }
455
456 /* XXX need more intelligent processing here, such as is implemented
457 * XXX for cheetah errors, in fact if the E-cache still holds the
458 * XXX line with bad parity this will loop
459 */
460
461 spitfire_clean_and_reenable_l1_caches();
462 spitfire_enable_estate_errors();
463
464 if (test_thread_flag(TIF_32BIT)) {
465 regs->tpc &= 0xffffffff;
466 regs->tnpc &= 0xffffffff;
467 }
468 info.si_signo = SIGBUS;
469 info.si_errno = 0;
470 info.si_code = BUS_OBJERR;
471 info.si_addr = (void *)0;
472 info.si_trapno = 0;
473 force_sig_info(SIGBUS, &info, current);
474 }
475
476 void spitfire_access_error(struct pt_regs *regs, unsigned long status_encoded, unsigned long afar)
477 {
478 unsigned long afsr, tt, udbh, udbl;
479 int tl1;
480
481 afsr = (status_encoded & SFSTAT_AFSR_MASK) >> SFSTAT_AFSR_SHIFT;
482 tt = (status_encoded & SFSTAT_TRAP_TYPE) >> SFSTAT_TRAP_TYPE_SHIFT;
483 tl1 = (status_encoded & SFSTAT_TL_GT_ONE) ? 1 : 0;
484 udbl = (status_encoded & SFSTAT_UDBL_MASK) >> SFSTAT_UDBL_SHIFT;
485 udbh = (status_encoded & SFSTAT_UDBH_MASK) >> SFSTAT_UDBH_SHIFT;
486
487 #ifdef CONFIG_PCI
488 if (tt == TRAP_TYPE_DAE &&
489 pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
490 spitfire_clean_and_reenable_l1_caches();
491 spitfire_enable_estate_errors();
492
493 pci_poke_faulted = 1;
494 regs->tnpc = regs->tpc + 4;
495 return;
496 }
497 #endif
498
499 if (afsr & SFAFSR_UE)
500 spitfire_ue_log(afsr, afar, udbh, udbl, tt, tl1, regs);
501
502 if (tt == TRAP_TYPE_CEE) {
503 /* Handle the case where we took a CEE trap, but ACK'd
504 * only the UE state in the UDB error registers.
505 */
506 if (afsr & SFAFSR_UE) {
507 if (udbh & UDBE_CE) {
508 __asm__ __volatile__(
509 "stxa %0, [%1] %2\n\t"
510 "membar #Sync"
511 : /* no outputs */
512 : "r" (udbh & UDBE_CE),
513 "r" (0x0), "i" (ASI_UDB_ERROR_W));
514 }
515 if (udbl & UDBE_CE) {
516 __asm__ __volatile__(
517 "stxa %0, [%1] %2\n\t"
518 "membar #Sync"
519 : /* no outputs */
520 : "r" (udbl & UDBE_CE),
521 "r" (0x18), "i" (ASI_UDB_ERROR_W));
522 }
523 }
524
525 spitfire_cee_log(afsr, afar, udbh, udbl, tl1, regs);
526 }
527 }
528
529 int cheetah_pcache_forced_on;
530
531 void cheetah_enable_pcache(void)
532 {
533 unsigned long dcr;
534
535 printk("CHEETAH: Enabling P-Cache on cpu %d.\n",
536 smp_processor_id());
537
538 __asm__ __volatile__("ldxa [%%g0] %1, %0"
539 : "=r" (dcr)
540 : "i" (ASI_DCU_CONTROL_REG));
541 dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL);
542 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
543 "membar #Sync"
544 : /* no outputs */
545 : "r" (dcr), "i" (ASI_DCU_CONTROL_REG));
546 }
547
548 /* Cheetah error trap handling. */
549 static unsigned long ecache_flush_physbase;
550 static unsigned long ecache_flush_linesize;
551 static unsigned long ecache_flush_size;
552
553 /* WARNING: The error trap handlers in assembly know the precise
554 * layout of the following structure.
555 *
556 * C-level handlers below use this information to log the error
557 * and then determine how to recover (if possible).
558 */
559 struct cheetah_err_info {
560 /*0x00*/u64 afsr;
561 /*0x08*/u64 afar;
562
563 /* D-cache state */
564 /*0x10*/u64 dcache_data[4]; /* The actual data */
565 /*0x30*/u64 dcache_index; /* D-cache index */
566 /*0x38*/u64 dcache_tag; /* D-cache tag/valid */
567 /*0x40*/u64 dcache_utag; /* D-cache microtag */
568 /*0x48*/u64 dcache_stag; /* D-cache snooptag */
569
570 /* I-cache state */
571 /*0x50*/u64 icache_data[8]; /* The actual insns + predecode */
572 /*0x90*/u64 icache_index; /* I-cache index */
573 /*0x98*/u64 icache_tag; /* I-cache phys tag */
574 /*0xa0*/u64 icache_utag; /* I-cache microtag */
575 /*0xa8*/u64 icache_stag; /* I-cache snooptag */
576 /*0xb0*/u64 icache_upper; /* I-cache upper-tag */
577 /*0xb8*/u64 icache_lower; /* I-cache lower-tag */
578
579 /* E-cache state */
580 /*0xc0*/u64 ecache_data[4]; /* 32 bytes from staging registers */
581 /*0xe0*/u64 ecache_index; /* E-cache index */
582 /*0xe8*/u64 ecache_tag; /* E-cache tag/state */
583
584 /*0xf0*/u64 __pad[32 - 30];
585 };
586 #define CHAFSR_INVALID ((u64)-1L)
587
588 /* This table is ordered in priority of errors and matches the
589 * AFAR overwrite policy as well.
590 */
591
592 struct afsr_error_table {
593 unsigned long mask;
594 const char *name;
595 };
596
597 static const char CHAFSR_PERR_msg[] =
598 "System interface protocol error";
599 static const char CHAFSR_IERR_msg[] =
600 "Internal processor error";
601 static const char CHAFSR_ISAP_msg[] =
602 "System request parity error on incoming addresss";
603 static const char CHAFSR_UCU_msg[] =
604 "Uncorrectable E-cache ECC error for ifetch/data";
605 static const char CHAFSR_UCC_msg[] =
606 "SW Correctable E-cache ECC error for ifetch/data";
607 static const char CHAFSR_UE_msg[] =
608 "Uncorrectable system bus data ECC error for read";
609 static const char CHAFSR_EDU_msg[] =
610 "Uncorrectable E-cache ECC error for stmerge/blkld";
611 static const char CHAFSR_EMU_msg[] =
612 "Uncorrectable system bus MTAG error";
613 static const char CHAFSR_WDU_msg[] =
614 "Uncorrectable E-cache ECC error for writeback";
615 static const char CHAFSR_CPU_msg[] =
616 "Uncorrectable ECC error for copyout";
617 static const char CHAFSR_CE_msg[] =
618 "HW corrected system bus data ECC error for read";
619 static const char CHAFSR_EDC_msg[] =
620 "HW corrected E-cache ECC error for stmerge/blkld";
621 static const char CHAFSR_EMC_msg[] =
622 "HW corrected system bus MTAG ECC error";
623 static const char CHAFSR_WDC_msg[] =
624 "HW corrected E-cache ECC error for writeback";
625 static const char CHAFSR_CPC_msg[] =
626 "HW corrected ECC error for copyout";
627 static const char CHAFSR_TO_msg[] =
628 "Unmapped error from system bus";
629 static const char CHAFSR_BERR_msg[] =
630 "Bus error response from system bus";
631 static const char CHAFSR_IVC_msg[] =
632 "HW corrected system bus data ECC error for ivec read";
633 static const char CHAFSR_IVU_msg[] =
634 "Uncorrectable system bus data ECC error for ivec read";
635 static struct afsr_error_table __cheetah_error_table[] = {
636 { CHAFSR_PERR, CHAFSR_PERR_msg },
637 { CHAFSR_IERR, CHAFSR_IERR_msg },
638 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
639 { CHAFSR_UCU, CHAFSR_UCU_msg },
640 { CHAFSR_UCC, CHAFSR_UCC_msg },
641 { CHAFSR_UE, CHAFSR_UE_msg },
642 { CHAFSR_EDU, CHAFSR_EDU_msg },
643 { CHAFSR_EMU, CHAFSR_EMU_msg },
644 { CHAFSR_WDU, CHAFSR_WDU_msg },
645 { CHAFSR_CPU, CHAFSR_CPU_msg },
646 { CHAFSR_CE, CHAFSR_CE_msg },
647 { CHAFSR_EDC, CHAFSR_EDC_msg },
648 { CHAFSR_EMC, CHAFSR_EMC_msg },
649 { CHAFSR_WDC, CHAFSR_WDC_msg },
650 { CHAFSR_CPC, CHAFSR_CPC_msg },
651 { CHAFSR_TO, CHAFSR_TO_msg },
652 { CHAFSR_BERR, CHAFSR_BERR_msg },
653 /* These two do not update the AFAR. */
654 { CHAFSR_IVC, CHAFSR_IVC_msg },
655 { CHAFSR_IVU, CHAFSR_IVU_msg },
656 { 0, NULL },
657 };
658 static const char CHPAFSR_DTO_msg[] =
659 "System bus unmapped error for prefetch/storequeue-read";
660 static const char CHPAFSR_DBERR_msg[] =
661 "System bus error for prefetch/storequeue-read";
662 static const char CHPAFSR_THCE_msg[] =
663 "Hardware corrected E-cache Tag ECC error";
664 static const char CHPAFSR_TSCE_msg[] =
665 "SW handled correctable E-cache Tag ECC error";
666 static const char CHPAFSR_TUE_msg[] =
667 "Uncorrectable E-cache Tag ECC error";
668 static const char CHPAFSR_DUE_msg[] =
669 "System bus uncorrectable data ECC error due to prefetch/store-fill";
670 static struct afsr_error_table __cheetah_plus_error_table[] = {
671 { CHAFSR_PERR, CHAFSR_PERR_msg },
672 { CHAFSR_IERR, CHAFSR_IERR_msg },
673 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
674 { CHAFSR_UCU, CHAFSR_UCU_msg },
675 { CHAFSR_UCC, CHAFSR_UCC_msg },
676 { CHAFSR_UE, CHAFSR_UE_msg },
677 { CHAFSR_EDU, CHAFSR_EDU_msg },
678 { CHAFSR_EMU, CHAFSR_EMU_msg },
679 { CHAFSR_WDU, CHAFSR_WDU_msg },
680 { CHAFSR_CPU, CHAFSR_CPU_msg },
681 { CHAFSR_CE, CHAFSR_CE_msg },
682 { CHAFSR_EDC, CHAFSR_EDC_msg },
683 { CHAFSR_EMC, CHAFSR_EMC_msg },
684 { CHAFSR_WDC, CHAFSR_WDC_msg },
685 { CHAFSR_CPC, CHAFSR_CPC_msg },
686 { CHAFSR_TO, CHAFSR_TO_msg },
687 { CHAFSR_BERR, CHAFSR_BERR_msg },
688 { CHPAFSR_DTO, CHPAFSR_DTO_msg },
689 { CHPAFSR_DBERR, CHPAFSR_DBERR_msg },
690 { CHPAFSR_THCE, CHPAFSR_THCE_msg },
691 { CHPAFSR_TSCE, CHPAFSR_TSCE_msg },
692 { CHPAFSR_TUE, CHPAFSR_TUE_msg },
693 { CHPAFSR_DUE, CHPAFSR_DUE_msg },
694 /* These two do not update the AFAR. */
695 { CHAFSR_IVC, CHAFSR_IVC_msg },
696 { CHAFSR_IVU, CHAFSR_IVU_msg },
697 { 0, NULL },
698 };
699 static const char JPAFSR_JETO_msg[] =
700 "System interface protocol error, hw timeout caused";
701 static const char JPAFSR_SCE_msg[] =
702 "Parity error on system snoop results";
703 static const char JPAFSR_JEIC_msg[] =
704 "System interface protocol error, illegal command detected";
705 static const char JPAFSR_JEIT_msg[] =
706 "System interface protocol error, illegal ADTYPE detected";
707 static const char JPAFSR_OM_msg[] =
708 "Out of range memory error has occurred";
709 static const char JPAFSR_ETP_msg[] =
710 "Parity error on L2 cache tag SRAM";
711 static const char JPAFSR_UMS_msg[] =
712 "Error due to unsupported store";
713 static const char JPAFSR_RUE_msg[] =
714 "Uncorrectable ECC error from remote cache/memory";
715 static const char JPAFSR_RCE_msg[] =
716 "Correctable ECC error from remote cache/memory";
717 static const char JPAFSR_BP_msg[] =
718 "JBUS parity error on returned read data";
719 static const char JPAFSR_WBP_msg[] =
720 "JBUS parity error on data for writeback or block store";
721 static const char JPAFSR_FRC_msg[] =
722 "Foreign read to DRAM incurring correctable ECC error";
723 static const char JPAFSR_FRU_msg[] =
724 "Foreign read to DRAM incurring uncorrectable ECC error";
725 static struct afsr_error_table __jalapeno_error_table[] = {
726 { JPAFSR_JETO, JPAFSR_JETO_msg },
727 { JPAFSR_SCE, JPAFSR_SCE_msg },
728 { JPAFSR_JEIC, JPAFSR_JEIC_msg },
729 { JPAFSR_JEIT, JPAFSR_JEIT_msg },
730 { CHAFSR_PERR, CHAFSR_PERR_msg },
731 { CHAFSR_IERR, CHAFSR_IERR_msg },
732 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
733 { CHAFSR_UCU, CHAFSR_UCU_msg },
734 { CHAFSR_UCC, CHAFSR_UCC_msg },
735 { CHAFSR_UE, CHAFSR_UE_msg },
736 { CHAFSR_EDU, CHAFSR_EDU_msg },
737 { JPAFSR_OM, JPAFSR_OM_msg },
738 { CHAFSR_WDU, CHAFSR_WDU_msg },
739 { CHAFSR_CPU, CHAFSR_CPU_msg },
740 { CHAFSR_CE, CHAFSR_CE_msg },
741 { CHAFSR_EDC, CHAFSR_EDC_msg },
742 { JPAFSR_ETP, JPAFSR_ETP_msg },
743 { CHAFSR_WDC, CHAFSR_WDC_msg },
744 { CHAFSR_CPC, CHAFSR_CPC_msg },
745 { CHAFSR_TO, CHAFSR_TO_msg },
746 { CHAFSR_BERR, CHAFSR_BERR_msg },
747 { JPAFSR_UMS, JPAFSR_UMS_msg },
748 { JPAFSR_RUE, JPAFSR_RUE_msg },
749 { JPAFSR_RCE, JPAFSR_RCE_msg },
750 { JPAFSR_BP, JPAFSR_BP_msg },
751 { JPAFSR_WBP, JPAFSR_WBP_msg },
752 { JPAFSR_FRC, JPAFSR_FRC_msg },
753 { JPAFSR_FRU, JPAFSR_FRU_msg },
754 /* These two do not update the AFAR. */
755 { CHAFSR_IVU, CHAFSR_IVU_msg },
756 { 0, NULL },
757 };
758 static struct afsr_error_table *cheetah_error_table;
759 static unsigned long cheetah_afsr_errors;
760
761 /* This is allocated at boot time based upon the largest hardware
762 * cpu ID in the system. We allocate two entries per cpu, one for
763 * TL==0 logging and one for TL >= 1 logging.
764 */
765 struct cheetah_err_info *cheetah_error_log;
766
767 static __inline__ struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
768 {
769 struct cheetah_err_info *p;
770 int cpu = smp_processor_id();
771
772 if (!cheetah_error_log)
773 return NULL;
774
775 p = cheetah_error_log + (cpu * 2);
776 if ((afsr & CHAFSR_TL1) != 0UL)
777 p++;
778
779 return p;
780 }
781
782 extern unsigned int tl0_icpe[], tl1_icpe[];
783 extern unsigned int tl0_dcpe[], tl1_dcpe[];
784 extern unsigned int tl0_fecc[], tl1_fecc[];
785 extern unsigned int tl0_cee[], tl1_cee[];
786 extern unsigned int tl0_iae[], tl1_iae[];
787 extern unsigned int tl0_dae[], tl1_dae[];
788 extern unsigned int cheetah_plus_icpe_trap_vector[], cheetah_plus_icpe_trap_vector_tl1[];
789 extern unsigned int cheetah_plus_dcpe_trap_vector[], cheetah_plus_dcpe_trap_vector_tl1[];
790 extern unsigned int cheetah_fecc_trap_vector[], cheetah_fecc_trap_vector_tl1[];
791 extern unsigned int cheetah_cee_trap_vector[], cheetah_cee_trap_vector_tl1[];
792 extern unsigned int cheetah_deferred_trap_vector[], cheetah_deferred_trap_vector_tl1[];
793
794 void __init cheetah_ecache_flush_init(void)
795 {
796 unsigned long largest_size, smallest_linesize, order, ver;
797 struct device_node *dp;
798 int i, instance, sz;
799
800 /* Scan all cpu device tree nodes, note two values:
801 * 1) largest E-cache size
802 * 2) smallest E-cache line size
803 */
804 largest_size = 0UL;
805 smallest_linesize = ~0UL;
806
807 instance = 0;
808 while (!cpu_find_by_instance(instance, &dp, NULL)) {
809 unsigned long val;
810
811 val = of_getintprop_default(dp, "ecache-size",
812 (2 * 1024 * 1024));
813 if (val > largest_size)
814 largest_size = val;
815 val = of_getintprop_default(dp, "ecache-line-size", 64);
816 if (val < smallest_linesize)
817 smallest_linesize = val;
818 instance++;
819 }
820
821 if (largest_size == 0UL || smallest_linesize == ~0UL) {
822 prom_printf("cheetah_ecache_flush_init: Cannot probe cpu E-cache "
823 "parameters.\n");
824 prom_halt();
825 }
826
827 ecache_flush_size = (2 * largest_size);
828 ecache_flush_linesize = smallest_linesize;
829
830 ecache_flush_physbase = find_ecache_flush_span(ecache_flush_size);
831
832 if (ecache_flush_physbase == ~0UL) {
833 prom_printf("cheetah_ecache_flush_init: Cannot find %d byte "
834 "contiguous physical memory.\n",
835 ecache_flush_size);
836 prom_halt();
837 }
838
839 /* Now allocate error trap reporting scoreboard. */
840 sz = NR_CPUS * (2 * sizeof(struct cheetah_err_info));
841 for (order = 0; order < MAX_ORDER; order++) {
842 if ((PAGE_SIZE << order) >= sz)
843 break;
844 }
845 cheetah_error_log = (struct cheetah_err_info *)
846 __get_free_pages(GFP_KERNEL, order);
847 if (!cheetah_error_log) {
848 prom_printf("cheetah_ecache_flush_init: Failed to allocate "
849 "error logging scoreboard (%d bytes).\n", sz);
850 prom_halt();
851 }
852 memset(cheetah_error_log, 0, PAGE_SIZE << order);
853
854 /* Mark all AFSRs as invalid so that the trap handler will
855 * log new new information there.
856 */
857 for (i = 0; i < 2 * NR_CPUS; i++)
858 cheetah_error_log[i].afsr = CHAFSR_INVALID;
859
860 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
861 if ((ver >> 32) == __JALAPENO_ID ||
862 (ver >> 32) == __SERRANO_ID) {
863 cheetah_error_table = &__jalapeno_error_table[0];
864 cheetah_afsr_errors = JPAFSR_ERRORS;
865 } else if ((ver >> 32) == 0x003e0015) {
866 cheetah_error_table = &__cheetah_plus_error_table[0];
867 cheetah_afsr_errors = CHPAFSR_ERRORS;
868 } else {
869 cheetah_error_table = &__cheetah_error_table[0];
870 cheetah_afsr_errors = CHAFSR_ERRORS;
871 }
872
873 /* Now patch trap tables. */
874 memcpy(tl0_fecc, cheetah_fecc_trap_vector, (8 * 4));
875 memcpy(tl1_fecc, cheetah_fecc_trap_vector_tl1, (8 * 4));
876 memcpy(tl0_cee, cheetah_cee_trap_vector, (8 * 4));
877 memcpy(tl1_cee, cheetah_cee_trap_vector_tl1, (8 * 4));
878 memcpy(tl0_iae, cheetah_deferred_trap_vector, (8 * 4));
879 memcpy(tl1_iae, cheetah_deferred_trap_vector_tl1, (8 * 4));
880 memcpy(tl0_dae, cheetah_deferred_trap_vector, (8 * 4));
881 memcpy(tl1_dae, cheetah_deferred_trap_vector_tl1, (8 * 4));
882 if (tlb_type == cheetah_plus) {
883 memcpy(tl0_dcpe, cheetah_plus_dcpe_trap_vector, (8 * 4));
884 memcpy(tl1_dcpe, cheetah_plus_dcpe_trap_vector_tl1, (8 * 4));
885 memcpy(tl0_icpe, cheetah_plus_icpe_trap_vector, (8 * 4));
886 memcpy(tl1_icpe, cheetah_plus_icpe_trap_vector_tl1, (8 * 4));
887 }
888 flushi(PAGE_OFFSET);
889 }
890
891 static void cheetah_flush_ecache(void)
892 {
893 unsigned long flush_base = ecache_flush_physbase;
894 unsigned long flush_linesize = ecache_flush_linesize;
895 unsigned long flush_size = ecache_flush_size;
896
897 __asm__ __volatile__("1: subcc %0, %4, %0\n\t"
898 " bne,pt %%xcc, 1b\n\t"
899 " ldxa [%2 + %0] %3, %%g0\n\t"
900 : "=&r" (flush_size)
901 : "0" (flush_size), "r" (flush_base),
902 "i" (ASI_PHYS_USE_EC), "r" (flush_linesize));
903 }
904
905 static void cheetah_flush_ecache_line(unsigned long physaddr)
906 {
907 unsigned long alias;
908
909 physaddr &= ~(8UL - 1UL);
910 physaddr = (ecache_flush_physbase +
911 (physaddr & ((ecache_flush_size>>1UL) - 1UL)));
912 alias = physaddr + (ecache_flush_size >> 1UL);
913 __asm__ __volatile__("ldxa [%0] %2, %%g0\n\t"
914 "ldxa [%1] %2, %%g0\n\t"
915 "membar #Sync"
916 : /* no outputs */
917 : "r" (physaddr), "r" (alias),
918 "i" (ASI_PHYS_USE_EC));
919 }
920
921 /* Unfortunately, the diagnostic access to the I-cache tags we need to
922 * use to clear the thing interferes with I-cache coherency transactions.
923 *
924 * So we must only flush the I-cache when it is disabled.
925 */
926 static void __cheetah_flush_icache(void)
927 {
928 unsigned int icache_size, icache_line_size;
929 unsigned long addr;
930
931 icache_size = local_cpu_data().icache_size;
932 icache_line_size = local_cpu_data().icache_line_size;
933
934 /* Clear the valid bits in all the tags. */
935 for (addr = 0; addr < icache_size; addr += icache_line_size) {
936 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
937 "membar #Sync"
938 : /* no outputs */
939 : "r" (addr | (2 << 3)),
940 "i" (ASI_IC_TAG));
941 }
942 }
943
944 static void cheetah_flush_icache(void)
945 {
946 unsigned long dcu_save;
947
948 /* Save current DCU, disable I-cache. */
949 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
950 "or %0, %2, %%g1\n\t"
951 "stxa %%g1, [%%g0] %1\n\t"
952 "membar #Sync"
953 : "=r" (dcu_save)
954 : "i" (ASI_DCU_CONTROL_REG), "i" (DCU_IC)
955 : "g1");
956
957 __cheetah_flush_icache();
958
959 /* Restore DCU register */
960 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
961 "membar #Sync"
962 : /* no outputs */
963 : "r" (dcu_save), "i" (ASI_DCU_CONTROL_REG));
964 }
965
966 static void cheetah_flush_dcache(void)
967 {
968 unsigned int dcache_size, dcache_line_size;
969 unsigned long addr;
970
971 dcache_size = local_cpu_data().dcache_size;
972 dcache_line_size = local_cpu_data().dcache_line_size;
973
974 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
975 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
976 "membar #Sync"
977 : /* no outputs */
978 : "r" (addr), "i" (ASI_DCACHE_TAG));
979 }
980 }
981
982 /* In order to make the even parity correct we must do two things.
983 * First, we clear DC_data_parity and set DC_utag to an appropriate value.
984 * Next, we clear out all 32-bytes of data for that line. Data of
985 * all-zero + tag parity value of zero == correct parity.
986 */
987 static void cheetah_plus_zap_dcache_parity(void)
988 {
989 unsigned int dcache_size, dcache_line_size;
990 unsigned long addr;
991
992 dcache_size = local_cpu_data().dcache_size;
993 dcache_line_size = local_cpu_data().dcache_line_size;
994
995 for (addr = 0; addr < dcache_size; addr += dcache_line_size) {
996 unsigned long tag = (addr >> 14);
997 unsigned long line;
998
999 __asm__ __volatile__("membar #Sync\n\t"
1000 "stxa %0, [%1] %2\n\t"
1001 "membar #Sync"
1002 : /* no outputs */
1003 : "r" (tag), "r" (addr),
1004 "i" (ASI_DCACHE_UTAG));
1005 for (line = addr; line < addr + dcache_line_size; line += 8)
1006 __asm__ __volatile__("membar #Sync\n\t"
1007 "stxa %%g0, [%0] %1\n\t"
1008 "membar #Sync"
1009 : /* no outputs */
1010 : "r" (line),
1011 "i" (ASI_DCACHE_DATA));
1012 }
1013 }
1014
1015 /* Conversion tables used to frob Cheetah AFSR syndrome values into
1016 * something palatable to the memory controller driver get_unumber
1017 * routine.
1018 */
1019 #define MT0 137
1020 #define MT1 138
1021 #define MT2 139
1022 #define NONE 254
1023 #define MTC0 140
1024 #define MTC1 141
1025 #define MTC2 142
1026 #define MTC3 143
1027 #define C0 128
1028 #define C1 129
1029 #define C2 130
1030 #define C3 131
1031 #define C4 132
1032 #define C5 133
1033 #define C6 134
1034 #define C7 135
1035 #define C8 136
1036 #define M2 144
1037 #define M3 145
1038 #define M4 146
1039 #define M 147
1040 static unsigned char cheetah_ecc_syntab[] = {
1041 /*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
1042 /*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16,
1043 /*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
1044 /*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
1045 /*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6,
1046 /*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
1047 /*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
1048 /*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
1049 /*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5,
1050 /*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M,
1051 /*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
1052 /*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
1053 /*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
1054 /*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
1055 /*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
1056 /*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
1057 /*10*/C8, M, M2, 39, M, 34, 105, M2, M, 30, 104, M, 101, M, M, 4,
1058 /*11*/M, M, 100, M, 83, M, M2, 12, 87, M, M, 57, M2, M, M3, M,
1059 /*12*/M2, 97, 82, M2, 78, M2, M2, 1, 96, M, M, M, M, M, M3, M2,
1060 /*13*/94, M, M2, M3, M2, M, M3, M, M2, M, 79, M, 69, M, M4, M,
1061 /*14*/M2, 93, 92, M, 91, M, M2, 8, 90, M2, M2, M, M, M, M, M4,
1062 /*15*/89, M, M, M3, M2, M3, M3, M, M, M, M3, M2, M3, M2, M, M3,
1063 /*16*/86, M, M2, M3, M2, M, M3, M, M2, M, M3, M, M3, M, M, M3,
1064 /*17*/M, M, M3, M2, M3, M2, M4, M, 60, M, M2, M3, M4, M, M, M2,
1065 /*18*/M2, 88, 85, M2, 84, M, M2, 55, 81, M2, M2, M3, M2, M3, M3, M4,
1066 /*19*/77, M, M, M, M2, M3, M, M, M2, M3, M3, M4, M3, M2, M, M,
1067 /*1a*/74, M, M2, M3, M, M, M3, M, M, M, M3, M, M3, M, M4, M3,
1068 /*1b*/M2, 70, 107, M4, 65, M2, M2, M, 127, M, M, M, M2, M3, M3, M,
1069 /*1c*/80, M2, M2, 72, M, 119, 118, M, M2, 126, 76, M, 125, M, M4, M3,
1070 /*1d*/M2, 115, 124, M, 75, M, M, M3, 61, M, M4, M, M4, M, M, M,
1071 /*1e*/M, 123, 122, M4, 121, M4, M, M3, 117, M2, M2, M3, M4, M3, M, M,
1072 /*1f*/111, M, M, M, M4, M3, M3, M, M, M, M3, M, M3, M2, M, M
1073 };
1074 static unsigned char cheetah_mtag_syntab[] = {
1075 NONE, MTC0,
1076 MTC1, NONE,
1077 MTC2, NONE,
1078 NONE, MT0,
1079 MTC3, NONE,
1080 NONE, MT1,
1081 NONE, MT2,
1082 NONE, NONE
1083 };
1084
1085 /* Return the highest priority error conditon mentioned. */
1086 static __inline__ unsigned long cheetah_get_hipri(unsigned long afsr)
1087 {
1088 unsigned long tmp = 0;
1089 int i;
1090
1091 for (i = 0; cheetah_error_table[i].mask; i++) {
1092 if ((tmp = (afsr & cheetah_error_table[i].mask)) != 0UL)
1093 return tmp;
1094 }
1095 return tmp;
1096 }
1097
1098 static const char *cheetah_get_string(unsigned long bit)
1099 {
1100 int i;
1101
1102 for (i = 0; cheetah_error_table[i].mask; i++) {
1103 if ((bit & cheetah_error_table[i].mask) != 0UL)
1104 return cheetah_error_table[i].name;
1105 }
1106 return "???";
1107 }
1108
1109 extern int chmc_getunumber(int, unsigned long, char *, int);
1110
1111 static void cheetah_log_errors(struct pt_regs *regs, struct cheetah_err_info *info,
1112 unsigned long afsr, unsigned long afar, int recoverable)
1113 {
1114 unsigned long hipri;
1115 char unum[256];
1116
1117 printk("%s" "ERROR(%d): Cheetah error trap taken afsr[%016lx] afar[%016lx] TL1(%d)\n",
1118 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1119 afsr, afar,
1120 (afsr & CHAFSR_TL1) ? 1 : 0);
1121 printk("%s" "ERROR(%d): TPC[%lx] TNPC[%lx] O7[%lx] TSTATE[%lx]\n",
1122 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1123 regs->tpc, regs->tnpc, regs->u_regs[UREG_I7], regs->tstate);
1124 printk("%s" "ERROR(%d): ",
1125 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id());
1126 print_symbol("TPC<%s>\n", regs->tpc);
1127 printk("%s" "ERROR(%d): M_SYND(%lx), E_SYND(%lx)%s%s\n",
1128 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1129 (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT,
1130 (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT,
1131 (afsr & CHAFSR_ME) ? ", Multiple Errors" : "",
1132 (afsr & CHAFSR_PRIV) ? ", Privileged" : "");
1133 hipri = cheetah_get_hipri(afsr);
1134 printk("%s" "ERROR(%d): Highest priority error (%016lx) \"%s\"\n",
1135 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1136 hipri, cheetah_get_string(hipri));
1137
1138 /* Try to get unumber if relevant. */
1139 #define ESYND_ERRORS (CHAFSR_IVC | CHAFSR_IVU | \
1140 CHAFSR_CPC | CHAFSR_CPU | \
1141 CHAFSR_UE | CHAFSR_CE | \
1142 CHAFSR_EDC | CHAFSR_EDU | \
1143 CHAFSR_UCC | CHAFSR_UCU | \
1144 CHAFSR_WDU | CHAFSR_WDC)
1145 #define MSYND_ERRORS (CHAFSR_EMC | CHAFSR_EMU)
1146 if (afsr & ESYND_ERRORS) {
1147 int syndrome;
1148 int ret;
1149
1150 syndrome = (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT;
1151 syndrome = cheetah_ecc_syntab[syndrome];
1152 ret = chmc_getunumber(syndrome, afar, unum, sizeof(unum));
1153 if (ret != -1)
1154 printk("%s" "ERROR(%d): AFAR E-syndrome [%s]\n",
1155 (recoverable ? KERN_WARNING : KERN_CRIT),
1156 smp_processor_id(), unum);
1157 } else if (afsr & MSYND_ERRORS) {
1158 int syndrome;
1159 int ret;
1160
1161 syndrome = (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT;
1162 syndrome = cheetah_mtag_syntab[syndrome];
1163 ret = chmc_getunumber(syndrome, afar, unum, sizeof(unum));
1164 if (ret != -1)
1165 printk("%s" "ERROR(%d): AFAR M-syndrome [%s]\n",
1166 (recoverable ? KERN_WARNING : KERN_CRIT),
1167 smp_processor_id(), unum);
1168 }
1169
1170 /* Now dump the cache snapshots. */
1171 printk("%s" "ERROR(%d): D-cache idx[%x] tag[%016lx] utag[%016lx] stag[%016lx]\n",
1172 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1173 (int) info->dcache_index,
1174 info->dcache_tag,
1175 info->dcache_utag,
1176 info->dcache_stag);
1177 printk("%s" "ERROR(%d): D-cache data0[%016lx] data1[%016lx] data2[%016lx] data3[%016lx]\n",
1178 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1179 info->dcache_data[0],
1180 info->dcache_data[1],
1181 info->dcache_data[2],
1182 info->dcache_data[3]);
1183 printk("%s" "ERROR(%d): I-cache idx[%x] tag[%016lx] utag[%016lx] stag[%016lx] "
1184 "u[%016lx] l[%016lx]\n",
1185 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1186 (int) info->icache_index,
1187 info->icache_tag,
1188 info->icache_utag,
1189 info->icache_stag,
1190 info->icache_upper,
1191 info->icache_lower);
1192 printk("%s" "ERROR(%d): I-cache INSN0[%016lx] INSN1[%016lx] INSN2[%016lx] INSN3[%016lx]\n",
1193 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1194 info->icache_data[0],
1195 info->icache_data[1],
1196 info->icache_data[2],
1197 info->icache_data[3]);
1198 printk("%s" "ERROR(%d): I-cache INSN4[%016lx] INSN5[%016lx] INSN6[%016lx] INSN7[%016lx]\n",
1199 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1200 info->icache_data[4],
1201 info->icache_data[5],
1202 info->icache_data[6],
1203 info->icache_data[7]);
1204 printk("%s" "ERROR(%d): E-cache idx[%x] tag[%016lx]\n",
1205 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1206 (int) info->ecache_index, info->ecache_tag);
1207 printk("%s" "ERROR(%d): E-cache data0[%016lx] data1[%016lx] data2[%016lx] data3[%016lx]\n",
1208 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1209 info->ecache_data[0],
1210 info->ecache_data[1],
1211 info->ecache_data[2],
1212 info->ecache_data[3]);
1213
1214 afsr = (afsr & ~hipri) & cheetah_afsr_errors;
1215 while (afsr != 0UL) {
1216 unsigned long bit = cheetah_get_hipri(afsr);
1217
1218 printk("%s" "ERROR: Multiple-error (%016lx) \"%s\"\n",
1219 (recoverable ? KERN_WARNING : KERN_CRIT),
1220 bit, cheetah_get_string(bit));
1221
1222 afsr &= ~bit;
1223 }
1224
1225 if (!recoverable)
1226 printk(KERN_CRIT "ERROR: This condition is not recoverable.\n");
1227 }
1228
1229 static int cheetah_recheck_errors(struct cheetah_err_info *logp)
1230 {
1231 unsigned long afsr, afar;
1232 int ret = 0;
1233
1234 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1235 : "=r" (afsr)
1236 : "i" (ASI_AFSR));
1237 if ((afsr & cheetah_afsr_errors) != 0) {
1238 if (logp != NULL) {
1239 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1240 : "=r" (afar)
1241 : "i" (ASI_AFAR));
1242 logp->afsr = afsr;
1243 logp->afar = afar;
1244 }
1245 ret = 1;
1246 }
1247 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1248 "membar #Sync\n\t"
1249 : : "r" (afsr), "i" (ASI_AFSR));
1250
1251 return ret;
1252 }
1253
1254 void cheetah_fecc_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1255 {
1256 struct cheetah_err_info local_snapshot, *p;
1257 int recoverable;
1258
1259 /* Flush E-cache */
1260 cheetah_flush_ecache();
1261
1262 p = cheetah_get_error_log(afsr);
1263 if (!p) {
1264 prom_printf("ERROR: Early Fast-ECC error afsr[%016lx] afar[%016lx]\n",
1265 afsr, afar);
1266 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1267 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1268 prom_halt();
1269 }
1270
1271 /* Grab snapshot of logged error. */
1272 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1273
1274 /* If the current trap snapshot does not match what the
1275 * trap handler passed along into our args, big trouble.
1276 * In such a case, mark the local copy as invalid.
1277 *
1278 * Else, it matches and we mark the afsr in the non-local
1279 * copy as invalid so we may log new error traps there.
1280 */
1281 if (p->afsr != afsr || p->afar != afar)
1282 local_snapshot.afsr = CHAFSR_INVALID;
1283 else
1284 p->afsr = CHAFSR_INVALID;
1285
1286 cheetah_flush_icache();
1287 cheetah_flush_dcache();
1288
1289 /* Re-enable I-cache/D-cache */
1290 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1291 "or %%g1, %1, %%g1\n\t"
1292 "stxa %%g1, [%%g0] %0\n\t"
1293 "membar #Sync"
1294 : /* no outputs */
1295 : "i" (ASI_DCU_CONTROL_REG),
1296 "i" (DCU_DC | DCU_IC)
1297 : "g1");
1298
1299 /* Re-enable error reporting */
1300 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1301 "or %%g1, %1, %%g1\n\t"
1302 "stxa %%g1, [%%g0] %0\n\t"
1303 "membar #Sync"
1304 : /* no outputs */
1305 : "i" (ASI_ESTATE_ERROR_EN),
1306 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1307 : "g1");
1308
1309 /* Decide if we can continue after handling this trap and
1310 * logging the error.
1311 */
1312 recoverable = 1;
1313 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1314 recoverable = 0;
1315
1316 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1317 * error was logged while we had error reporting traps disabled.
1318 */
1319 if (cheetah_recheck_errors(&local_snapshot)) {
1320 unsigned long new_afsr = local_snapshot.afsr;
1321
1322 /* If we got a new asynchronous error, die... */
1323 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1324 CHAFSR_WDU | CHAFSR_CPU |
1325 CHAFSR_IVU | CHAFSR_UE |
1326 CHAFSR_BERR | CHAFSR_TO))
1327 recoverable = 0;
1328 }
1329
1330 /* Log errors. */
1331 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1332
1333 if (!recoverable)
1334 panic("Irrecoverable Fast-ECC error trap.\n");
1335
1336 /* Flush E-cache to kick the error trap handlers out. */
1337 cheetah_flush_ecache();
1338 }
1339
1340 /* Try to fix a correctable error by pushing the line out from
1341 * the E-cache. Recheck error reporting registers to see if the
1342 * problem is intermittent.
1343 */
1344 static int cheetah_fix_ce(unsigned long physaddr)
1345 {
1346 unsigned long orig_estate;
1347 unsigned long alias1, alias2;
1348 int ret;
1349
1350 /* Make sure correctable error traps are disabled. */
1351 __asm__ __volatile__("ldxa [%%g0] %2, %0\n\t"
1352 "andn %0, %1, %%g1\n\t"
1353 "stxa %%g1, [%%g0] %2\n\t"
1354 "membar #Sync"
1355 : "=&r" (orig_estate)
1356 : "i" (ESTATE_ERROR_CEEN),
1357 "i" (ASI_ESTATE_ERROR_EN)
1358 : "g1");
1359
1360 /* We calculate alias addresses that will force the
1361 * cache line in question out of the E-cache. Then
1362 * we bring it back in with an atomic instruction so
1363 * that we get it in some modified/exclusive state,
1364 * then we displace it again to try and get proper ECC
1365 * pushed back into the system.
1366 */
1367 physaddr &= ~(8UL - 1UL);
1368 alias1 = (ecache_flush_physbase +
1369 (physaddr & ((ecache_flush_size >> 1) - 1)));
1370 alias2 = alias1 + (ecache_flush_size >> 1);
1371 __asm__ __volatile__("ldxa [%0] %3, %%g0\n\t"
1372 "ldxa [%1] %3, %%g0\n\t"
1373 "casxa [%2] %3, %%g0, %%g0\n\t"
1374 "membar #StoreLoad | #StoreStore\n\t"
1375 "ldxa [%0] %3, %%g0\n\t"
1376 "ldxa [%1] %3, %%g0\n\t"
1377 "membar #Sync"
1378 : /* no outputs */
1379 : "r" (alias1), "r" (alias2),
1380 "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1381
1382 /* Did that trigger another error? */
1383 if (cheetah_recheck_errors(NULL)) {
1384 /* Try one more time. */
1385 __asm__ __volatile__("ldxa [%0] %1, %%g0\n\t"
1386 "membar #Sync"
1387 : : "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1388 if (cheetah_recheck_errors(NULL))
1389 ret = 2;
1390 else
1391 ret = 1;
1392 } else {
1393 /* No new error, intermittent problem. */
1394 ret = 0;
1395 }
1396
1397 /* Restore error enables. */
1398 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1399 "membar #Sync"
1400 : : "r" (orig_estate), "i" (ASI_ESTATE_ERROR_EN));
1401
1402 return ret;
1403 }
1404
1405 /* Return non-zero if PADDR is a valid physical memory address. */
1406 static int cheetah_check_main_memory(unsigned long paddr)
1407 {
1408 unsigned long vaddr = PAGE_OFFSET + paddr;
1409
1410 if (vaddr > (unsigned long) high_memory)
1411 return 0;
1412
1413 return kern_addr_valid(vaddr);
1414 }
1415
1416 void cheetah_cee_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1417 {
1418 struct cheetah_err_info local_snapshot, *p;
1419 int recoverable, is_memory;
1420
1421 p = cheetah_get_error_log(afsr);
1422 if (!p) {
1423 prom_printf("ERROR: Early CEE error afsr[%016lx] afar[%016lx]\n",
1424 afsr, afar);
1425 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1426 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1427 prom_halt();
1428 }
1429
1430 /* Grab snapshot of logged error. */
1431 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1432
1433 /* If the current trap snapshot does not match what the
1434 * trap handler passed along into our args, big trouble.
1435 * In such a case, mark the local copy as invalid.
1436 *
1437 * Else, it matches and we mark the afsr in the non-local
1438 * copy as invalid so we may log new error traps there.
1439 */
1440 if (p->afsr != afsr || p->afar != afar)
1441 local_snapshot.afsr = CHAFSR_INVALID;
1442 else
1443 p->afsr = CHAFSR_INVALID;
1444
1445 is_memory = cheetah_check_main_memory(afar);
1446
1447 if (is_memory && (afsr & CHAFSR_CE) != 0UL) {
1448 /* XXX Might want to log the results of this operation
1449 * XXX somewhere... -DaveM
1450 */
1451 cheetah_fix_ce(afar);
1452 }
1453
1454 {
1455 int flush_all, flush_line;
1456
1457 flush_all = flush_line = 0;
1458 if ((afsr & CHAFSR_EDC) != 0UL) {
1459 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDC)
1460 flush_line = 1;
1461 else
1462 flush_all = 1;
1463 } else if ((afsr & CHAFSR_CPC) != 0UL) {
1464 if ((afsr & cheetah_afsr_errors) == CHAFSR_CPC)
1465 flush_line = 1;
1466 else
1467 flush_all = 1;
1468 }
1469
1470 /* Trap handler only disabled I-cache, flush it. */
1471 cheetah_flush_icache();
1472
1473 /* Re-enable I-cache */
1474 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1475 "or %%g1, %1, %%g1\n\t"
1476 "stxa %%g1, [%%g0] %0\n\t"
1477 "membar #Sync"
1478 : /* no outputs */
1479 : "i" (ASI_DCU_CONTROL_REG),
1480 "i" (DCU_IC)
1481 : "g1");
1482
1483 if (flush_all)
1484 cheetah_flush_ecache();
1485 else if (flush_line)
1486 cheetah_flush_ecache_line(afar);
1487 }
1488
1489 /* Re-enable error reporting */
1490 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1491 "or %%g1, %1, %%g1\n\t"
1492 "stxa %%g1, [%%g0] %0\n\t"
1493 "membar #Sync"
1494 : /* no outputs */
1495 : "i" (ASI_ESTATE_ERROR_EN),
1496 "i" (ESTATE_ERROR_CEEN)
1497 : "g1");
1498
1499 /* Decide if we can continue after handling this trap and
1500 * logging the error.
1501 */
1502 recoverable = 1;
1503 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1504 recoverable = 0;
1505
1506 /* Re-check AFSR/AFAR */
1507 (void) cheetah_recheck_errors(&local_snapshot);
1508
1509 /* Log errors. */
1510 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1511
1512 if (!recoverable)
1513 panic("Irrecoverable Correctable-ECC error trap.\n");
1514 }
1515
1516 void cheetah_deferred_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1517 {
1518 struct cheetah_err_info local_snapshot, *p;
1519 int recoverable, is_memory;
1520
1521 #ifdef CONFIG_PCI
1522 /* Check for the special PCI poke sequence. */
1523 if (pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
1524 cheetah_flush_icache();
1525 cheetah_flush_dcache();
1526
1527 /* Re-enable I-cache/D-cache */
1528 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1529 "or %%g1, %1, %%g1\n\t"
1530 "stxa %%g1, [%%g0] %0\n\t"
1531 "membar #Sync"
1532 : /* no outputs */
1533 : "i" (ASI_DCU_CONTROL_REG),
1534 "i" (DCU_DC | DCU_IC)
1535 : "g1");
1536
1537 /* Re-enable error reporting */
1538 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1539 "or %%g1, %1, %%g1\n\t"
1540 "stxa %%g1, [%%g0] %0\n\t"
1541 "membar #Sync"
1542 : /* no outputs */
1543 : "i" (ASI_ESTATE_ERROR_EN),
1544 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1545 : "g1");
1546
1547 (void) cheetah_recheck_errors(NULL);
1548
1549 pci_poke_faulted = 1;
1550 regs->tpc += 4;
1551 regs->tnpc = regs->tpc + 4;
1552 return;
1553 }
1554 #endif
1555
1556 p = cheetah_get_error_log(afsr);
1557 if (!p) {
1558 prom_printf("ERROR: Early deferred error afsr[%016lx] afar[%016lx]\n",
1559 afsr, afar);
1560 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1561 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1562 prom_halt();
1563 }
1564
1565 /* Grab snapshot of logged error. */
1566 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1567
1568 /* If the current trap snapshot does not match what the
1569 * trap handler passed along into our args, big trouble.
1570 * In such a case, mark the local copy as invalid.
1571 *
1572 * Else, it matches and we mark the afsr in the non-local
1573 * copy as invalid so we may log new error traps there.
1574 */
1575 if (p->afsr != afsr || p->afar != afar)
1576 local_snapshot.afsr = CHAFSR_INVALID;
1577 else
1578 p->afsr = CHAFSR_INVALID;
1579
1580 is_memory = cheetah_check_main_memory(afar);
1581
1582 {
1583 int flush_all, flush_line;
1584
1585 flush_all = flush_line = 0;
1586 if ((afsr & CHAFSR_EDU) != 0UL) {
1587 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDU)
1588 flush_line = 1;
1589 else
1590 flush_all = 1;
1591 } else if ((afsr & CHAFSR_BERR) != 0UL) {
1592 if ((afsr & cheetah_afsr_errors) == CHAFSR_BERR)
1593 flush_line = 1;
1594 else
1595 flush_all = 1;
1596 }
1597
1598 cheetah_flush_icache();
1599 cheetah_flush_dcache();
1600
1601 /* Re-enable I/D caches */
1602 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1603 "or %%g1, %1, %%g1\n\t"
1604 "stxa %%g1, [%%g0] %0\n\t"
1605 "membar #Sync"
1606 : /* no outputs */
1607 : "i" (ASI_DCU_CONTROL_REG),
1608 "i" (DCU_IC | DCU_DC)
1609 : "g1");
1610
1611 if (flush_all)
1612 cheetah_flush_ecache();
1613 else if (flush_line)
1614 cheetah_flush_ecache_line(afar);
1615 }
1616
1617 /* Re-enable error reporting */
1618 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1619 "or %%g1, %1, %%g1\n\t"
1620 "stxa %%g1, [%%g0] %0\n\t"
1621 "membar #Sync"
1622 : /* no outputs */
1623 : "i" (ASI_ESTATE_ERROR_EN),
1624 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1625 : "g1");
1626
1627 /* Decide if we can continue after handling this trap and
1628 * logging the error.
1629 */
1630 recoverable = 1;
1631 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1632 recoverable = 0;
1633
1634 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1635 * error was logged while we had error reporting traps disabled.
1636 */
1637 if (cheetah_recheck_errors(&local_snapshot)) {
1638 unsigned long new_afsr = local_snapshot.afsr;
1639
1640 /* If we got a new asynchronous error, die... */
1641 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1642 CHAFSR_WDU | CHAFSR_CPU |
1643 CHAFSR_IVU | CHAFSR_UE |
1644 CHAFSR_BERR | CHAFSR_TO))
1645 recoverable = 0;
1646 }
1647
1648 /* Log errors. */
1649 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1650
1651 /* "Recoverable" here means we try to yank the page from ever
1652 * being newly used again. This depends upon a few things:
1653 * 1) Must be main memory, and AFAR must be valid.
1654 * 2) If we trapped from user, OK.
1655 * 3) Else, if we trapped from kernel we must find exception
1656 * table entry (ie. we have to have been accessing user
1657 * space).
1658 *
1659 * If AFAR is not in main memory, or we trapped from kernel
1660 * and cannot find an exception table entry, it is unacceptable
1661 * to try and continue.
1662 */
1663 if (recoverable && is_memory) {
1664 if ((regs->tstate & TSTATE_PRIV) == 0UL) {
1665 /* OK, usermode access. */
1666 recoverable = 1;
1667 } else {
1668 const struct exception_table_entry *entry;
1669
1670 entry = search_exception_tables(regs->tpc);
1671 if (entry) {
1672 /* OK, kernel access to userspace. */
1673 recoverable = 1;
1674
1675 } else {
1676 /* BAD, privileged state is corrupted. */
1677 recoverable = 0;
1678 }
1679
1680 if (recoverable) {
1681 if (pfn_valid(afar >> PAGE_SHIFT))
1682 get_page(pfn_to_page(afar >> PAGE_SHIFT));
1683 else
1684 recoverable = 0;
1685
1686 /* Only perform fixup if we still have a
1687 * recoverable condition.
1688 */
1689 if (recoverable) {
1690 regs->tpc = entry->fixup;
1691 regs->tnpc = regs->tpc + 4;
1692 }
1693 }
1694 }
1695 } else {
1696 recoverable = 0;
1697 }
1698
1699 if (!recoverable)
1700 panic("Irrecoverable deferred error trap.\n");
1701 }
1702
1703 /* Handle a D/I cache parity error trap. TYPE is encoded as:
1704 *
1705 * Bit0: 0=dcache,1=icache
1706 * Bit1: 0=recoverable,1=unrecoverable
1707 *
1708 * The hardware has disabled both the I-cache and D-cache in
1709 * the %dcr register.
1710 */
1711 void cheetah_plus_parity_error(int type, struct pt_regs *regs)
1712 {
1713 if (type & 0x1)
1714 __cheetah_flush_icache();
1715 else
1716 cheetah_plus_zap_dcache_parity();
1717 cheetah_flush_dcache();
1718
1719 /* Re-enable I-cache/D-cache */
1720 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1721 "or %%g1, %1, %%g1\n\t"
1722 "stxa %%g1, [%%g0] %0\n\t"
1723 "membar #Sync"
1724 : /* no outputs */
1725 : "i" (ASI_DCU_CONTROL_REG),
1726 "i" (DCU_DC | DCU_IC)
1727 : "g1");
1728
1729 if (type & 0x2) {
1730 printk(KERN_EMERG "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1731 smp_processor_id(),
1732 (type & 0x1) ? 'I' : 'D',
1733 regs->tpc);
1734 print_symbol(KERN_EMERG "TPC<%s>\n", regs->tpc);
1735 panic("Irrecoverable Cheetah+ parity error.");
1736 }
1737
1738 printk(KERN_WARNING "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1739 smp_processor_id(),
1740 (type & 0x1) ? 'I' : 'D',
1741 regs->tpc);
1742 print_symbol(KERN_WARNING "TPC<%s>\n", regs->tpc);
1743 }
1744
1745 struct sun4v_error_entry {
1746 u64 err_handle;
1747 u64 err_stick;
1748
1749 u32 err_type;
1750 #define SUN4V_ERR_TYPE_UNDEFINED 0
1751 #define SUN4V_ERR_TYPE_UNCORRECTED_RES 1
1752 #define SUN4V_ERR_TYPE_PRECISE_NONRES 2
1753 #define SUN4V_ERR_TYPE_DEFERRED_NONRES 3
1754 #define SUN4V_ERR_TYPE_WARNING_RES 4
1755
1756 u32 err_attrs;
1757 #define SUN4V_ERR_ATTRS_PROCESSOR 0x00000001
1758 #define SUN4V_ERR_ATTRS_MEMORY 0x00000002
1759 #define SUN4V_ERR_ATTRS_PIO 0x00000004
1760 #define SUN4V_ERR_ATTRS_INT_REGISTERS 0x00000008
1761 #define SUN4V_ERR_ATTRS_FPU_REGISTERS 0x00000010
1762 #define SUN4V_ERR_ATTRS_USER_MODE 0x01000000
1763 #define SUN4V_ERR_ATTRS_PRIV_MODE 0x02000000
1764 #define SUN4V_ERR_ATTRS_RES_QUEUE_FULL 0x80000000
1765
1766 u64 err_raddr;
1767 u32 err_size;
1768 u16 err_cpu;
1769 u16 err_pad;
1770 };
1771
1772 static atomic_t sun4v_resum_oflow_cnt = ATOMIC_INIT(0);
1773 static atomic_t sun4v_nonresum_oflow_cnt = ATOMIC_INIT(0);
1774
1775 static const char *sun4v_err_type_to_str(u32 type)
1776 {
1777 switch (type) {
1778 case SUN4V_ERR_TYPE_UNDEFINED:
1779 return "undefined";
1780 case SUN4V_ERR_TYPE_UNCORRECTED_RES:
1781 return "uncorrected resumable";
1782 case SUN4V_ERR_TYPE_PRECISE_NONRES:
1783 return "precise nonresumable";
1784 case SUN4V_ERR_TYPE_DEFERRED_NONRES:
1785 return "deferred nonresumable";
1786 case SUN4V_ERR_TYPE_WARNING_RES:
1787 return "warning resumable";
1788 default:
1789 return "unknown";
1790 };
1791 }
1792
1793 extern void __show_regs(struct pt_regs * regs);
1794
1795 static void sun4v_log_error(struct pt_regs *regs, struct sun4v_error_entry *ent, int cpu, const char *pfx, atomic_t *ocnt)
1796 {
1797 int cnt;
1798
1799 printk("%s: Reporting on cpu %d\n", pfx, cpu);
1800 printk("%s: err_handle[%lx] err_stick[%lx] err_type[%08x:%s]\n",
1801 pfx,
1802 ent->err_handle, ent->err_stick,
1803 ent->err_type,
1804 sun4v_err_type_to_str(ent->err_type));
1805 printk("%s: err_attrs[%08x:%s %s %s %s %s %s %s %s]\n",
1806 pfx,
1807 ent->err_attrs,
1808 ((ent->err_attrs & SUN4V_ERR_ATTRS_PROCESSOR) ?
1809 "processor" : ""),
1810 ((ent->err_attrs & SUN4V_ERR_ATTRS_MEMORY) ?
1811 "memory" : ""),
1812 ((ent->err_attrs & SUN4V_ERR_ATTRS_PIO) ?
1813 "pio" : ""),
1814 ((ent->err_attrs & SUN4V_ERR_ATTRS_INT_REGISTERS) ?
1815 "integer-regs" : ""),
1816 ((ent->err_attrs & SUN4V_ERR_ATTRS_FPU_REGISTERS) ?
1817 "fpu-regs" : ""),
1818 ((ent->err_attrs & SUN4V_ERR_ATTRS_USER_MODE) ?
1819 "user" : ""),
1820 ((ent->err_attrs & SUN4V_ERR_ATTRS_PRIV_MODE) ?
1821 "privileged" : ""),
1822 ((ent->err_attrs & SUN4V_ERR_ATTRS_RES_QUEUE_FULL) ?
1823 "queue-full" : ""));
1824 printk("%s: err_raddr[%016lx] err_size[%u] err_cpu[%u]\n",
1825 pfx,
1826 ent->err_raddr, ent->err_size, ent->err_cpu);
1827
1828 __show_regs(regs);
1829
1830 if ((cnt = atomic_read(ocnt)) != 0) {
1831 atomic_set(ocnt, 0);
1832 wmb();
1833 printk("%s: Queue overflowed %d times.\n",
1834 pfx, cnt);
1835 }
1836 }
1837
1838 /* We run with %pil set to 15 and PSTATE_IE enabled in %pstate.
1839 * Log the event and clear the first word of the entry.
1840 */
1841 void sun4v_resum_error(struct pt_regs *regs, unsigned long offset)
1842 {
1843 struct sun4v_error_entry *ent, local_copy;
1844 struct trap_per_cpu *tb;
1845 unsigned long paddr;
1846 int cpu;
1847
1848 cpu = get_cpu();
1849
1850 tb = &trap_block[cpu];
1851 paddr = tb->resum_kernel_buf_pa + offset;
1852 ent = __va(paddr);
1853
1854 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
1855
1856 /* We have a local copy now, so release the entry. */
1857 ent->err_handle = 0;
1858 wmb();
1859
1860 put_cpu();
1861
1862 if (ent->err_type == SUN4V_ERR_TYPE_WARNING_RES) {
1863 /* If err_type is 0x4, it's a powerdown request. Do
1864 * not do the usual resumable error log because that
1865 * makes it look like some abnormal error.
1866 */
1867 printk(KERN_INFO "Power down request...\n");
1868 kill_cad_pid(SIGINT, 1);
1869 return;
1870 }
1871
1872 sun4v_log_error(regs, &local_copy, cpu,
1873 KERN_ERR "RESUMABLE ERROR",
1874 &sun4v_resum_oflow_cnt);
1875 }
1876
1877 /* If we try to printk() we'll probably make matters worse, by trying
1878 * to retake locks this cpu already holds or causing more errors. So
1879 * just bump a counter, and we'll report these counter bumps above.
1880 */
1881 void sun4v_resum_overflow(struct pt_regs *regs)
1882 {
1883 atomic_inc(&sun4v_resum_oflow_cnt);
1884 }
1885
1886 /* We run with %pil set to 15 and PSTATE_IE enabled in %pstate.
1887 * Log the event, clear the first word of the entry, and die.
1888 */
1889 void sun4v_nonresum_error(struct pt_regs *regs, unsigned long offset)
1890 {
1891 struct sun4v_error_entry *ent, local_copy;
1892 struct trap_per_cpu *tb;
1893 unsigned long paddr;
1894 int cpu;
1895
1896 cpu = get_cpu();
1897
1898 tb = &trap_block[cpu];
1899 paddr = tb->nonresum_kernel_buf_pa + offset;
1900 ent = __va(paddr);
1901
1902 memcpy(&local_copy, ent, sizeof(struct sun4v_error_entry));
1903
1904 /* We have a local copy now, so release the entry. */
1905 ent->err_handle = 0;
1906 wmb();
1907
1908 put_cpu();
1909
1910 #ifdef CONFIG_PCI
1911 /* Check for the special PCI poke sequence. */
1912 if (pci_poke_in_progress && pci_poke_cpu == cpu) {
1913 pci_poke_faulted = 1;
1914 regs->tpc += 4;
1915 regs->tnpc = regs->tpc + 4;
1916 return;
1917 }
1918 #endif
1919
1920 sun4v_log_error(regs, &local_copy, cpu,
1921 KERN_EMERG "NON-RESUMABLE ERROR",
1922 &sun4v_nonresum_oflow_cnt);
1923
1924 panic("Non-resumable error.");
1925 }
1926
1927 /* If we try to printk() we'll probably make matters worse, by trying
1928 * to retake locks this cpu already holds or causing more errors. So
1929 * just bump a counter, and we'll report these counter bumps above.
1930 */
1931 void sun4v_nonresum_overflow(struct pt_regs *regs)
1932 {
1933 /* XXX Actually even this can make not that much sense. Perhaps
1934 * XXX we should just pull the plug and panic directly from here?
1935 */
1936 atomic_inc(&sun4v_nonresum_oflow_cnt);
1937 }
1938
1939 unsigned long sun4v_err_itlb_vaddr;
1940 unsigned long sun4v_err_itlb_ctx;
1941 unsigned long sun4v_err_itlb_pte;
1942 unsigned long sun4v_err_itlb_error;
1943
1944 void sun4v_itlb_error_report(struct pt_regs *regs, int tl)
1945 {
1946 if (tl > 1)
1947 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
1948
1949 printk(KERN_EMERG "SUN4V-ITLB: Error at TPC[%lx], tl %d\n",
1950 regs->tpc, tl);
1951 print_symbol(KERN_EMERG "SUN4V-ITLB: TPC<%s>\n", regs->tpc);
1952 printk(KERN_EMERG "SUN4V-ITLB: vaddr[%lx] ctx[%lx] "
1953 "pte[%lx] error[%lx]\n",
1954 sun4v_err_itlb_vaddr, sun4v_err_itlb_ctx,
1955 sun4v_err_itlb_pte, sun4v_err_itlb_error);
1956
1957 prom_halt();
1958 }
1959
1960 unsigned long sun4v_err_dtlb_vaddr;
1961 unsigned long sun4v_err_dtlb_ctx;
1962 unsigned long sun4v_err_dtlb_pte;
1963 unsigned long sun4v_err_dtlb_error;
1964
1965 void sun4v_dtlb_error_report(struct pt_regs *regs, int tl)
1966 {
1967 if (tl > 1)
1968 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
1969
1970 printk(KERN_EMERG "SUN4V-DTLB: Error at TPC[%lx], tl %d\n",
1971 regs->tpc, tl);
1972 print_symbol(KERN_EMERG "SUN4V-DTLB: TPC<%s>\n", regs->tpc);
1973 printk(KERN_EMERG "SUN4V-DTLB: vaddr[%lx] ctx[%lx] "
1974 "pte[%lx] error[%lx]\n",
1975 sun4v_err_dtlb_vaddr, sun4v_err_dtlb_ctx,
1976 sun4v_err_dtlb_pte, sun4v_err_dtlb_error);
1977
1978 prom_halt();
1979 }
1980
1981 void hypervisor_tlbop_error(unsigned long err, unsigned long op)
1982 {
1983 printk(KERN_CRIT "SUN4V: TLB hv call error %lu for op %lu\n",
1984 err, op);
1985 }
1986
1987 void hypervisor_tlbop_error_xcall(unsigned long err, unsigned long op)
1988 {
1989 printk(KERN_CRIT "SUN4V: XCALL TLB hv call error %lu for op %lu\n",
1990 err, op);
1991 }
1992
1993 void do_fpe_common(struct pt_regs *regs)
1994 {
1995 if (regs->tstate & TSTATE_PRIV) {
1996 regs->tpc = regs->tnpc;
1997 regs->tnpc += 4;
1998 } else {
1999 unsigned long fsr = current_thread_info()->xfsr[0];
2000 siginfo_t info;
2001
2002 if (test_thread_flag(TIF_32BIT)) {
2003 regs->tpc &= 0xffffffff;
2004 regs->tnpc &= 0xffffffff;
2005 }
2006 info.si_signo = SIGFPE;
2007 info.si_errno = 0;
2008 info.si_addr = (void __user *)regs->tpc;
2009 info.si_trapno = 0;
2010 info.si_code = __SI_FAULT;
2011 if ((fsr & 0x1c000) == (1 << 14)) {
2012 if (fsr & 0x10)
2013 info.si_code = FPE_FLTINV;
2014 else if (fsr & 0x08)
2015 info.si_code = FPE_FLTOVF;
2016 else if (fsr & 0x04)
2017 info.si_code = FPE_FLTUND;
2018 else if (fsr & 0x02)
2019 info.si_code = FPE_FLTDIV;
2020 else if (fsr & 0x01)
2021 info.si_code = FPE_FLTRES;
2022 }
2023 force_sig_info(SIGFPE, &info, current);
2024 }
2025 }
2026
2027 void do_fpieee(struct pt_regs *regs)
2028 {
2029 if (notify_die(DIE_TRAP, "fpu exception ieee", regs,
2030 0, 0x24, SIGFPE) == NOTIFY_STOP)
2031 return;
2032
2033 do_fpe_common(regs);
2034 }
2035
2036 extern int do_mathemu(struct pt_regs *, struct fpustate *);
2037
2038 void do_fpother(struct pt_regs *regs)
2039 {
2040 struct fpustate *f = FPUSTATE;
2041 int ret = 0;
2042
2043 if (notify_die(DIE_TRAP, "fpu exception other", regs,
2044 0, 0x25, SIGFPE) == NOTIFY_STOP)
2045 return;
2046
2047 switch ((current_thread_info()->xfsr[0] & 0x1c000)) {
2048 case (2 << 14): /* unfinished_FPop */
2049 case (3 << 14): /* unimplemented_FPop */
2050 ret = do_mathemu(regs, f);
2051 break;
2052 }
2053 if (ret)
2054 return;
2055 do_fpe_common(regs);
2056 }
2057
2058 void do_tof(struct pt_regs *regs)
2059 {
2060 siginfo_t info;
2061
2062 if (notify_die(DIE_TRAP, "tagged arithmetic overflow", regs,
2063 0, 0x26, SIGEMT) == NOTIFY_STOP)
2064 return;
2065
2066 if (regs->tstate & TSTATE_PRIV)
2067 die_if_kernel("Penguin overflow trap from kernel mode", regs);
2068 if (test_thread_flag(TIF_32BIT)) {
2069 regs->tpc &= 0xffffffff;
2070 regs->tnpc &= 0xffffffff;
2071 }
2072 info.si_signo = SIGEMT;
2073 info.si_errno = 0;
2074 info.si_code = EMT_TAGOVF;
2075 info.si_addr = (void __user *)regs->tpc;
2076 info.si_trapno = 0;
2077 force_sig_info(SIGEMT, &info, current);
2078 }
2079
2080 void do_div0(struct pt_regs *regs)
2081 {
2082 siginfo_t info;
2083
2084 if (notify_die(DIE_TRAP, "integer division by zero", regs,
2085 0, 0x28, SIGFPE) == NOTIFY_STOP)
2086 return;
2087
2088 if (regs->tstate & TSTATE_PRIV)
2089 die_if_kernel("TL0: Kernel divide by zero.", regs);
2090 if (test_thread_flag(TIF_32BIT)) {
2091 regs->tpc &= 0xffffffff;
2092 regs->tnpc &= 0xffffffff;
2093 }
2094 info.si_signo = SIGFPE;
2095 info.si_errno = 0;
2096 info.si_code = FPE_INTDIV;
2097 info.si_addr = (void __user *)regs->tpc;
2098 info.si_trapno = 0;
2099 force_sig_info(SIGFPE, &info, current);
2100 }
2101
2102 void instruction_dump (unsigned int *pc)
2103 {
2104 int i;
2105
2106 if ((((unsigned long) pc) & 3))
2107 return;
2108
2109 printk("Instruction DUMP:");
2110 for (i = -3; i < 6; i++)
2111 printk("%c%08x%c",i?' ':'<',pc[i],i?' ':'>');
2112 printk("\n");
2113 }
2114
2115 static void user_instruction_dump (unsigned int __user *pc)
2116 {
2117 int i;
2118 unsigned int buf[9];
2119
2120 if ((((unsigned long) pc) & 3))
2121 return;
2122
2123 if (copy_from_user(buf, pc - 3, sizeof(buf)))
2124 return;
2125
2126 printk("Instruction DUMP:");
2127 for (i = 0; i < 9; i++)
2128 printk("%c%08x%c",i==3?' ':'<',buf[i],i==3?' ':'>');
2129 printk("\n");
2130 }
2131
2132 void show_stack(struct task_struct *tsk, unsigned long *_ksp)
2133 {
2134 unsigned long pc, fp, thread_base, ksp;
2135 void *tp = task_stack_page(tsk);
2136 struct reg_window *rw;
2137 int count = 0;
2138
2139 ksp = (unsigned long) _ksp;
2140
2141 if (tp == current_thread_info())
2142 flushw_all();
2143
2144 fp = ksp + STACK_BIAS;
2145 thread_base = (unsigned long) tp;
2146
2147 printk("Call Trace:");
2148 #ifdef CONFIG_KALLSYMS
2149 printk("\n");
2150 #endif
2151 do {
2152 /* Bogus frame pointer? */
2153 if (fp < (thread_base + sizeof(struct thread_info)) ||
2154 fp >= (thread_base + THREAD_SIZE))
2155 break;
2156 rw = (struct reg_window *)fp;
2157 pc = rw->ins[7];
2158 printk(" [%016lx] ", pc);
2159 print_symbol("%s\n", pc);
2160 fp = rw->ins[6] + STACK_BIAS;
2161 } while (++count < 16);
2162 #ifndef CONFIG_KALLSYMS
2163 printk("\n");
2164 #endif
2165 }
2166
2167 void dump_stack(void)
2168 {
2169 unsigned long *ksp;
2170
2171 __asm__ __volatile__("mov %%fp, %0"
2172 : "=r" (ksp));
2173 show_stack(current, ksp);
2174 }
2175
2176 EXPORT_SYMBOL(dump_stack);
2177
2178 static inline int is_kernel_stack(struct task_struct *task,
2179 struct reg_window *rw)
2180 {
2181 unsigned long rw_addr = (unsigned long) rw;
2182 unsigned long thread_base, thread_end;
2183
2184 if (rw_addr < PAGE_OFFSET) {
2185 if (task != &init_task)
2186 return 0;
2187 }
2188
2189 thread_base = (unsigned long) task_stack_page(task);
2190 thread_end = thread_base + sizeof(union thread_union);
2191 if (rw_addr >= thread_base &&
2192 rw_addr < thread_end &&
2193 !(rw_addr & 0x7UL))
2194 return 1;
2195
2196 return 0;
2197 }
2198
2199 static inline struct reg_window *kernel_stack_up(struct reg_window *rw)
2200 {
2201 unsigned long fp = rw->ins[6];
2202
2203 if (!fp)
2204 return NULL;
2205
2206 return (struct reg_window *) (fp + STACK_BIAS);
2207 }
2208
2209 void die_if_kernel(char *str, struct pt_regs *regs)
2210 {
2211 static int die_counter;
2212 extern void smp_report_regs(void);
2213 int count = 0;
2214
2215 /* Amuse the user. */
2216 printk(
2217 " \\|/ ____ \\|/\n"
2218 " \"@'/ .. \\`@\"\n"
2219 " /_| \\__/ |_\\\n"
2220 " \\__U_/\n");
2221
2222 printk("%s(%d): %s [#%d]\n", current->comm, current->pid, str, ++die_counter);
2223 notify_die(DIE_OOPS, str, regs, 0, 255, SIGSEGV);
2224 __asm__ __volatile__("flushw");
2225 __show_regs(regs);
2226 if (regs->tstate & TSTATE_PRIV) {
2227 struct reg_window *rw = (struct reg_window *)
2228 (regs->u_regs[UREG_FP] + STACK_BIAS);
2229
2230 /* Stop the back trace when we hit userland or we
2231 * find some badly aligned kernel stack.
2232 */
2233 while (rw &&
2234 count++ < 30&&
2235 is_kernel_stack(current, rw)) {
2236 printk("Caller[%016lx]", rw->ins[7]);
2237 print_symbol(": %s", rw->ins[7]);
2238 printk("\n");
2239
2240 rw = kernel_stack_up(rw);
2241 }
2242 instruction_dump ((unsigned int *) regs->tpc);
2243 } else {
2244 if (test_thread_flag(TIF_32BIT)) {
2245 regs->tpc &= 0xffffffff;
2246 regs->tnpc &= 0xffffffff;
2247 }
2248 user_instruction_dump ((unsigned int __user *) regs->tpc);
2249 }
2250 #if 0
2251 #ifdef CONFIG_SMP
2252 smp_report_regs();
2253 #endif
2254 #endif
2255 if (regs->tstate & TSTATE_PRIV)
2256 do_exit(SIGKILL);
2257 do_exit(SIGSEGV);
2258 }
2259
2260 #define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19))
2261 #define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19))
2262
2263 extern int handle_popc(u32 insn, struct pt_regs *regs);
2264 extern int handle_ldf_stq(u32 insn, struct pt_regs *regs);
2265 extern int vis_emul(struct pt_regs *, unsigned int);
2266
2267 void do_illegal_instruction(struct pt_regs *regs)
2268 {
2269 unsigned long pc = regs->tpc;
2270 unsigned long tstate = regs->tstate;
2271 u32 insn;
2272 siginfo_t info;
2273
2274 if (notify_die(DIE_TRAP, "illegal instruction", regs,
2275 0, 0x10, SIGILL) == NOTIFY_STOP)
2276 return;
2277
2278 if (tstate & TSTATE_PRIV)
2279 die_if_kernel("Kernel illegal instruction", regs);
2280 if (test_thread_flag(TIF_32BIT))
2281 pc = (u32)pc;
2282 if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
2283 if ((insn & 0xc1ffc000) == 0x81700000) /* POPC */ {
2284 if (handle_popc(insn, regs))
2285 return;
2286 } else if ((insn & 0xc1580000) == 0xc1100000) /* LDQ/STQ */ {
2287 if (handle_ldf_stq(insn, regs))
2288 return;
2289 } else if (tlb_type == hypervisor) {
2290 if ((insn & VIS_OPCODE_MASK) == VIS_OPCODE_VAL) {
2291 if (!vis_emul(regs, insn))
2292 return;
2293 } else {
2294 struct fpustate *f = FPUSTATE;
2295
2296 /* XXX maybe verify XFSR bits like
2297 * XXX do_fpother() does?
2298 */
2299 if (do_mathemu(regs, f))
2300 return;
2301 }
2302 }
2303 }
2304 info.si_signo = SIGILL;
2305 info.si_errno = 0;
2306 info.si_code = ILL_ILLOPC;
2307 info.si_addr = (void __user *)pc;
2308 info.si_trapno = 0;
2309 force_sig_info(SIGILL, &info, current);
2310 }
2311
2312 extern void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn);
2313
2314 void mem_address_unaligned(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
2315 {
2316 siginfo_t info;
2317
2318 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2319 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2320 return;
2321
2322 if (regs->tstate & TSTATE_PRIV) {
2323 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2324 return;
2325 }
2326 info.si_signo = SIGBUS;
2327 info.si_errno = 0;
2328 info.si_code = BUS_ADRALN;
2329 info.si_addr = (void __user *)sfar;
2330 info.si_trapno = 0;
2331 force_sig_info(SIGBUS, &info, current);
2332 }
2333
2334 void sun4v_do_mna(struct pt_regs *regs, unsigned long addr, unsigned long type_ctx)
2335 {
2336 siginfo_t info;
2337
2338 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
2339 0, 0x34, SIGSEGV) == NOTIFY_STOP)
2340 return;
2341
2342 if (regs->tstate & TSTATE_PRIV) {
2343 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc));
2344 return;
2345 }
2346 info.si_signo = SIGBUS;
2347 info.si_errno = 0;
2348 info.si_code = BUS_ADRALN;
2349 info.si_addr = (void __user *) addr;
2350 info.si_trapno = 0;
2351 force_sig_info(SIGBUS, &info, current);
2352 }
2353
2354 void do_privop(struct pt_regs *regs)
2355 {
2356 siginfo_t info;
2357
2358 if (notify_die(DIE_TRAP, "privileged operation", regs,
2359 0, 0x11, SIGILL) == NOTIFY_STOP)
2360 return;
2361
2362 if (test_thread_flag(TIF_32BIT)) {
2363 regs->tpc &= 0xffffffff;
2364 regs->tnpc &= 0xffffffff;
2365 }
2366 info.si_signo = SIGILL;
2367 info.si_errno = 0;
2368 info.si_code = ILL_PRVOPC;
2369 info.si_addr = (void __user *)regs->tpc;
2370 info.si_trapno = 0;
2371 force_sig_info(SIGILL, &info, current);
2372 }
2373
2374 void do_privact(struct pt_regs *regs)
2375 {
2376 do_privop(regs);
2377 }
2378
2379 /* Trap level 1 stuff or other traps we should never see... */
2380 void do_cee(struct pt_regs *regs)
2381 {
2382 die_if_kernel("TL0: Cache Error Exception", regs);
2383 }
2384
2385 void do_cee_tl1(struct pt_regs *regs)
2386 {
2387 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2388 die_if_kernel("TL1: Cache Error Exception", regs);
2389 }
2390
2391 void do_dae_tl1(struct pt_regs *regs)
2392 {
2393 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2394 die_if_kernel("TL1: Data Access Exception", regs);
2395 }
2396
2397 void do_iae_tl1(struct pt_regs *regs)
2398 {
2399 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2400 die_if_kernel("TL1: Instruction Access Exception", regs);
2401 }
2402
2403 void do_div0_tl1(struct pt_regs *regs)
2404 {
2405 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2406 die_if_kernel("TL1: DIV0 Exception", regs);
2407 }
2408
2409 void do_fpdis_tl1(struct pt_regs *regs)
2410 {
2411 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2412 die_if_kernel("TL1: FPU Disabled", regs);
2413 }
2414
2415 void do_fpieee_tl1(struct pt_regs *regs)
2416 {
2417 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2418 die_if_kernel("TL1: FPU IEEE Exception", regs);
2419 }
2420
2421 void do_fpother_tl1(struct pt_regs *regs)
2422 {
2423 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2424 die_if_kernel("TL1: FPU Other Exception", regs);
2425 }
2426
2427 void do_ill_tl1(struct pt_regs *regs)
2428 {
2429 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2430 die_if_kernel("TL1: Illegal Instruction Exception", regs);
2431 }
2432
2433 void do_irq_tl1(struct pt_regs *regs)
2434 {
2435 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2436 die_if_kernel("TL1: IRQ Exception", regs);
2437 }
2438
2439 void do_lddfmna_tl1(struct pt_regs *regs)
2440 {
2441 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2442 die_if_kernel("TL1: LDDF Exception", regs);
2443 }
2444
2445 void do_stdfmna_tl1(struct pt_regs *regs)
2446 {
2447 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2448 die_if_kernel("TL1: STDF Exception", regs);
2449 }
2450
2451 void do_paw(struct pt_regs *regs)
2452 {
2453 die_if_kernel("TL0: Phys Watchpoint Exception", regs);
2454 }
2455
2456 void do_paw_tl1(struct pt_regs *regs)
2457 {
2458 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2459 die_if_kernel("TL1: Phys Watchpoint Exception", regs);
2460 }
2461
2462 void do_vaw(struct pt_regs *regs)
2463 {
2464 die_if_kernel("TL0: Virt Watchpoint Exception", regs);
2465 }
2466
2467 void do_vaw_tl1(struct pt_regs *regs)
2468 {
2469 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2470 die_if_kernel("TL1: Virt Watchpoint Exception", regs);
2471 }
2472
2473 void do_tof_tl1(struct pt_regs *regs)
2474 {
2475 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2476 die_if_kernel("TL1: Tag Overflow Exception", regs);
2477 }
2478
2479 void do_getpsr(struct pt_regs *regs)
2480 {
2481 regs->u_regs[UREG_I0] = tstate_to_psr(regs->tstate);
2482 regs->tpc = regs->tnpc;
2483 regs->tnpc += 4;
2484 if (test_thread_flag(TIF_32BIT)) {
2485 regs->tpc &= 0xffffffff;
2486 regs->tnpc &= 0xffffffff;
2487 }
2488 }
2489
2490 struct trap_per_cpu trap_block[NR_CPUS];
2491
2492 /* This can get invoked before sched_init() so play it super safe
2493 * and use hard_smp_processor_id().
2494 */
2495 void init_cur_cpu_trap(struct thread_info *t)
2496 {
2497 int cpu = hard_smp_processor_id();
2498 struct trap_per_cpu *p = &trap_block[cpu];
2499
2500 p->thread = t;
2501 p->pgd_paddr = 0;
2502 }
2503
2504 extern void thread_info_offsets_are_bolixed_dave(void);
2505 extern void trap_per_cpu_offsets_are_bolixed_dave(void);
2506 extern void tsb_config_offsets_are_bolixed_dave(void);
2507
2508 /* Only invoked on boot processor. */
2509 void __init trap_init(void)
2510 {
2511 /* Compile time sanity check. */
2512 if (TI_TASK != offsetof(struct thread_info, task) ||
2513 TI_FLAGS != offsetof(struct thread_info, flags) ||
2514 TI_CPU != offsetof(struct thread_info, cpu) ||
2515 TI_FPSAVED != offsetof(struct thread_info, fpsaved) ||
2516 TI_KSP != offsetof(struct thread_info, ksp) ||
2517 TI_FAULT_ADDR != offsetof(struct thread_info, fault_address) ||
2518 TI_KREGS != offsetof(struct thread_info, kregs) ||
2519 TI_UTRAPS != offsetof(struct thread_info, utraps) ||
2520 TI_EXEC_DOMAIN != offsetof(struct thread_info, exec_domain) ||
2521 TI_REG_WINDOW != offsetof(struct thread_info, reg_window) ||
2522 TI_RWIN_SPTRS != offsetof(struct thread_info, rwbuf_stkptrs) ||
2523 TI_GSR != offsetof(struct thread_info, gsr) ||
2524 TI_XFSR != offsetof(struct thread_info, xfsr) ||
2525 TI_USER_CNTD0 != offsetof(struct thread_info, user_cntd0) ||
2526 TI_USER_CNTD1 != offsetof(struct thread_info, user_cntd1) ||
2527 TI_KERN_CNTD0 != offsetof(struct thread_info, kernel_cntd0) ||
2528 TI_KERN_CNTD1 != offsetof(struct thread_info, kernel_cntd1) ||
2529 TI_PCR != offsetof(struct thread_info, pcr_reg) ||
2530 TI_PRE_COUNT != offsetof(struct thread_info, preempt_count) ||
2531 TI_NEW_CHILD != offsetof(struct thread_info, new_child) ||
2532 TI_SYS_NOERROR != offsetof(struct thread_info, syscall_noerror) ||
2533 TI_RESTART_BLOCK != offsetof(struct thread_info, restart_block) ||
2534 TI_KUNA_REGS != offsetof(struct thread_info, kern_una_regs) ||
2535 TI_KUNA_INSN != offsetof(struct thread_info, kern_una_insn) ||
2536 TI_FPREGS != offsetof(struct thread_info, fpregs) ||
2537 (TI_FPREGS & (64 - 1)))
2538 thread_info_offsets_are_bolixed_dave();
2539
2540 if (TRAP_PER_CPU_THREAD != offsetof(struct trap_per_cpu, thread) ||
2541 (TRAP_PER_CPU_PGD_PADDR !=
2542 offsetof(struct trap_per_cpu, pgd_paddr)) ||
2543 (TRAP_PER_CPU_CPU_MONDO_PA !=
2544 offsetof(struct trap_per_cpu, cpu_mondo_pa)) ||
2545 (TRAP_PER_CPU_DEV_MONDO_PA !=
2546 offsetof(struct trap_per_cpu, dev_mondo_pa)) ||
2547 (TRAP_PER_CPU_RESUM_MONDO_PA !=
2548 offsetof(struct trap_per_cpu, resum_mondo_pa)) ||
2549 (TRAP_PER_CPU_RESUM_KBUF_PA !=
2550 offsetof(struct trap_per_cpu, resum_kernel_buf_pa)) ||
2551 (TRAP_PER_CPU_NONRESUM_MONDO_PA !=
2552 offsetof(struct trap_per_cpu, nonresum_mondo_pa)) ||
2553 (TRAP_PER_CPU_NONRESUM_KBUF_PA !=
2554 offsetof(struct trap_per_cpu, nonresum_kernel_buf_pa)) ||
2555 (TRAP_PER_CPU_FAULT_INFO !=
2556 offsetof(struct trap_per_cpu, fault_info)) ||
2557 (TRAP_PER_CPU_CPU_MONDO_BLOCK_PA !=
2558 offsetof(struct trap_per_cpu, cpu_mondo_block_pa)) ||
2559 (TRAP_PER_CPU_CPU_LIST_PA !=
2560 offsetof(struct trap_per_cpu, cpu_list_pa)) ||
2561 (TRAP_PER_CPU_TSB_HUGE !=
2562 offsetof(struct trap_per_cpu, tsb_huge)) ||
2563 (TRAP_PER_CPU_TSB_HUGE_TEMP !=
2564 offsetof(struct trap_per_cpu, tsb_huge_temp)) ||
2565 (TRAP_PER_CPU_IRQ_WORKLIST !=
2566 offsetof(struct trap_per_cpu, irq_worklist)))
2567 trap_per_cpu_offsets_are_bolixed_dave();
2568
2569 if ((TSB_CONFIG_TSB !=
2570 offsetof(struct tsb_config, tsb)) ||
2571 (TSB_CONFIG_RSS_LIMIT !=
2572 offsetof(struct tsb_config, tsb_rss_limit)) ||
2573 (TSB_CONFIG_NENTRIES !=
2574 offsetof(struct tsb_config, tsb_nentries)) ||
2575 (TSB_CONFIG_REG_VAL !=
2576 offsetof(struct tsb_config, tsb_reg_val)) ||
2577 (TSB_CONFIG_MAP_VADDR !=
2578 offsetof(struct tsb_config, tsb_map_vaddr)) ||
2579 (TSB_CONFIG_MAP_PTE !=
2580 offsetof(struct tsb_config, tsb_map_pte)))
2581 tsb_config_offsets_are_bolixed_dave();
2582
2583 /* Attach to the address space of init_task. On SMP we
2584 * do this in smp.c:smp_callin for other cpus.
2585 */
2586 atomic_inc(&init_mm.mm_count);
2587 current->active_mm = &init_mm;
2588 }
Linux kernel - Deliverables
This page took 0.297503 seconds and 6 git commands to generate.