arch/sparc64/lib/VISsave.S

   1 /*
   2  * VISsave.S: Code for saving FPU register state for
   3  *            VIS routines. One should not call this directly,
   4  *            but use macros provided in <asm/visasm.h>.
   5  *
   6  * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
   7  */
   8
   9 #include <asm/asi.h>
  10 #include <asm/page.h>
  11 #include <asm/ptrace.h>
  12 #include <asm/visasm.h>
  13 #include <asm/thread_info.h>
  14
  15         .text
  16         .globl          VISenter, VISenterhalf
  17
  18         /* On entry: %o5=current FPRS value, %g7 is callers address */
  19         /* May clobber %o5, %g1, %g2, %g3, %g7, %icc, %xcc */
  20
  21         /* Nothing special need be done here to handle pre-emption, this
  22          * FPU save/restore mechanism is already preemption safe.
  23          */
  24
  25         .align          32
  26 VISenter:
  27         ldub            [%g6 + TI_FPDEPTH], %g1
  28         brnz,a,pn       %g1, 1f
  29          cmp            %g1, 1
  30         stb             %g0, [%g6 + TI_FPSAVED]
  31         stx             %fsr, [%g6 + TI_XFSR]
  32 9:      jmpl            %g7 + %g0, %g0
  33          nop
  34 1:      bne,pn          %icc, 2f
  35
  36          srl            %g1, 1, %g1
  37 vis1:   ldub            [%g6 + TI_FPSAVED], %g3
  38         stx             %fsr, [%g6 + TI_XFSR]
  39         or              %g3, %o5, %g3
  40         stb             %g3, [%g6 + TI_FPSAVED]
  41         rd              %gsr, %g3
  42         clr             %g1
  43         ba,pt           %xcc, 3f
  44
  45          stx            %g3, [%g6 + TI_GSR]
  46 2:      add             %g6, %g1, %g3
  47         cmp             %o5, FPRS_DU
  48         be,pn           %icc, 6f
  49          sll            %g1, 3, %g1
  50         stb             %o5, [%g3 + TI_FPSAVED]
  51         rd              %gsr, %g2
  52         add             %g6, %g1, %g3
  53         stx             %g2, [%g3 + TI_GSR]
  54
  55         add             %g6, %g1, %g2
  56         stx             %fsr, [%g2 + TI_XFSR]
  57         sll             %g1, 5, %g1
  58 3:      andcc           %o5, FPRS_DL|FPRS_DU, %g0
  59         be,pn           %icc, 9b
  60          add            %g6, TI_FPREGS, %g2
  61         andcc           %o5, FPRS_DL, %g0
  62
  63         be,pn           %icc, 4f
  64          add            %g6, TI_FPREGS+0x40, %g3
  65         membar          #Sync
  66         stda            %f0, [%g2 + %g1] ASI_BLK_P
  67         stda            %f16, [%g3 + %g1] ASI_BLK_P
  68         membar          #Sync
  69         andcc           %o5, FPRS_DU, %g0
  70         be,pn           %icc, 5f
  71 4:       add            %g1, 128, %g1
  72         membar          #Sync
  73         stda            %f32, [%g2 + %g1] ASI_BLK_P
  74
  75         stda            %f48, [%g3 + %g1] ASI_BLK_P
  76 5:      membar          #Sync
  77         ba,pt           %xcc, 80f
  78          nop
  79
  80         .align          32
  81 80:     jmpl            %g7 + %g0, %g0
  82          nop
  83
  84 6:      ldub            [%g3 + TI_FPSAVED], %o5
  85         or              %o5, FPRS_DU, %o5
  86         add             %g6, TI_FPREGS+0x80, %g2
  87         stb             %o5, [%g3 + TI_FPSAVED]
  88
  89         sll             %g1, 5, %g1
  90         add             %g6, TI_FPREGS+0xc0, %g3
  91         wr              %g0, FPRS_FEF, %fprs
  92         membar          #Sync
  93         stda            %f32, [%g2 + %g1] ASI_BLK_P
  94         stda            %f48, [%g3 + %g1] ASI_BLK_P
  95         membar          #Sync
  96         ba,pt           %xcc, 80f
  97          nop
  98
  99         .align          32
 100 80:     jmpl            %g7 + %g0, %g0
 101          nop
 102
 103         .align          32
 104 VISenterhalf:
 105         ldub            [%g6 + TI_FPDEPTH], %g1
 106         brnz,a,pn       %g1, 1f
 107          cmp            %g1, 1
 108         stb             %g0, [%g6 + TI_FPSAVED]
 109         stx             %fsr, [%g6 + TI_XFSR]
 110         clr             %o5
 111         jmpl            %g7 + %g0, %g0
 112          wr             %g0, FPRS_FEF, %fprs
 113
 114 1:      bne,pn          %icc, 2f
 115          srl            %g1, 1, %g1
 116         ba,pt           %xcc, vis1
 117          sub            %g7, 8, %g7
 118 2:      addcc           %g6, %g1, %g3
 119         sll             %g1, 3, %g1
 120         andn            %o5, FPRS_DU, %g2
 121         stb             %g2, [%g3 + TI_FPSAVED]
 122
 123         rd              %gsr, %g2
 124         add             %g6, %g1, %g3
 125         stx             %g2, [%g3 + TI_GSR]
 126         add             %g6, %g1, %g2
 127         stx             %fsr, [%g2 + TI_XFSR]
 128         sll             %g1, 5, %g1
 129 3:      andcc           %o5, FPRS_DL, %g0
 130         be,pn           %icc, 4f
 131          add            %g6, TI_FPREGS, %g2
 132
 133         add             %g6, TI_FPREGS+0x40, %g3
 134         membar          #Sync
 135         stda            %f0, [%g2 + %g1] ASI_BLK_P
 136         stda            %f16, [%g3 + %g1] ASI_BLK_P
 137         membar          #Sync
 138         ba,pt           %xcc, 4f
 139          nop
 140
 141         .align          32
 142 4:      and             %o5, FPRS_DU, %o5
 143         jmpl            %g7 + %g0, %g0
 144          wr             %o5, FPRS_FEF, %fprs