2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
27 #include <linux/device.h>
30 #include <asm/stacktrace.h>
33 #include <asm/alternative.h>
34 #include <asm/mmu_context.h>
35 #include <asm/tlbflush.h>
36 #include <asm/timer.h>
40 #include "perf_event.h"
42 struct x86_pmu x86_pmu __read_mostly
;
44 DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
48 struct static_key rdpmc_always_available
= STATIC_KEY_INIT_FALSE
;
50 u64 __read_mostly hw_cache_event_ids
51 [PERF_COUNT_HW_CACHE_MAX
]
52 [PERF_COUNT_HW_CACHE_OP_MAX
]
53 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
54 u64 __read_mostly hw_cache_extra_regs
55 [PERF_COUNT_HW_CACHE_MAX
]
56 [PERF_COUNT_HW_CACHE_OP_MAX
]
57 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
60 * Propagate event elapsed time into the generic event.
61 * Can only be executed on the CPU where the event is active.
62 * Returns the delta events processed.
64 u64
x86_perf_event_update(struct perf_event
*event
)
66 struct hw_perf_event
*hwc
= &event
->hw
;
67 int shift
= 64 - x86_pmu
.cntval_bits
;
68 u64 prev_raw_count
, new_raw_count
;
72 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
76 * Careful: an NMI might modify the previous event value.
78 * Our tactic to handle this is to first atomically read and
79 * exchange a new raw count - then add that new-prev delta
80 * count to the generic event atomically:
83 prev_raw_count
= local64_read(&hwc
->prev_count
);
84 rdpmcl(hwc
->event_base_rdpmc
, new_raw_count
);
86 if (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
87 new_raw_count
) != prev_raw_count
)
91 * Now we have the new raw value and have updated the prev
92 * timestamp already. We can now calculate the elapsed delta
93 * (event-)time and add that to the generic event.
95 * Careful, not all hw sign-extends above the physical width
98 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
101 local64_add(delta
, &event
->count
);
102 local64_sub(delta
, &hwc
->period_left
);
104 return new_raw_count
;
108 * Find and validate any extra registers to set up.
110 static int x86_pmu_extra_regs(u64 config
, struct perf_event
*event
)
112 struct hw_perf_event_extra
*reg
;
113 struct extra_reg
*er
;
115 reg
= &event
->hw
.extra_reg
;
117 if (!x86_pmu
.extra_regs
)
120 for (er
= x86_pmu
.extra_regs
; er
->msr
; er
++) {
121 if (er
->event
!= (config
& er
->config_mask
))
123 if (event
->attr
.config1
& ~er
->valid_mask
)
125 /* Check if the extra msrs can be safely accessed*/
126 if (!er
->extra_msr_access
)
130 reg
->config
= event
->attr
.config1
;
137 static atomic_t active_events
;
138 static atomic_t pmc_refcount
;
139 static DEFINE_MUTEX(pmc_reserve_mutex
);
141 #ifdef CONFIG_X86_LOCAL_APIC
143 static bool reserve_pmc_hardware(void)
147 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
148 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i
)))
152 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
153 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i
)))
160 for (i
--; i
>= 0; i
--)
161 release_evntsel_nmi(x86_pmu_config_addr(i
));
163 i
= x86_pmu
.num_counters
;
166 for (i
--; i
>= 0; i
--)
167 release_perfctr_nmi(x86_pmu_event_addr(i
));
172 static void release_pmc_hardware(void)
176 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
177 release_perfctr_nmi(x86_pmu_event_addr(i
));
178 release_evntsel_nmi(x86_pmu_config_addr(i
));
184 static bool reserve_pmc_hardware(void) { return true; }
185 static void release_pmc_hardware(void) {}
189 static bool check_hw_exists(void)
191 u64 val
, val_fail
, val_new
= ~0;
192 int i
, reg
, reg_fail
, ret
= 0;
197 * Check to see if the BIOS enabled any of the counters, if so
200 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
201 reg
= x86_pmu_config_addr(i
);
202 ret
= rdmsrl_safe(reg
, &val
);
205 if (val
& ARCH_PERFMON_EVENTSEL_ENABLE
) {
214 if (x86_pmu
.num_counters_fixed
) {
215 reg
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
216 ret
= rdmsrl_safe(reg
, &val
);
219 for (i
= 0; i
< x86_pmu
.num_counters_fixed
; i
++) {
220 if (val
& (0x03 << i
*4)) {
229 * If all the counters are enabled, the below test will always
230 * fail. The tools will also become useless in this scenario.
231 * Just fail and disable the hardware counters.
234 if (reg_safe
== -1) {
240 * Read the current value, change it and read it back to see if it
241 * matches, this is needed to detect certain hardware emulators
242 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
244 reg
= x86_pmu_event_addr(reg_safe
);
245 if (rdmsrl_safe(reg
, &val
))
248 ret
= wrmsrl_safe(reg
, val
);
249 ret
|= rdmsrl_safe(reg
, &val_new
);
250 if (ret
|| val
!= val_new
)
254 * We still allow the PMU driver to operate:
257 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
258 pr_err(FW_BUG
"the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
265 pr_cont("Broken PMU hardware detected, using software events only.\n");
266 pr_info("%sFailed to access perfctr msr (MSR %x is %Lx)\n",
267 boot_cpu_has(X86_FEATURE_HYPERVISOR
) ? KERN_INFO
: KERN_ERR
,
273 static void hw_perf_event_destroy(struct perf_event
*event
)
275 x86_release_hardware();
276 atomic_dec(&active_events
);
279 void hw_perf_lbr_event_destroy(struct perf_event
*event
)
281 hw_perf_event_destroy(event
);
283 /* undo the lbr/bts event accounting */
284 x86_del_exclusive(x86_lbr_exclusive_lbr
);
287 static inline int x86_pmu_initialized(void)
289 return x86_pmu
.handle_irq
!= NULL
;
293 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event
*event
)
295 struct perf_event_attr
*attr
= &event
->attr
;
296 unsigned int cache_type
, cache_op
, cache_result
;
299 config
= attr
->config
;
301 cache_type
= (config
>> 0) & 0xff;
302 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
305 cache_op
= (config
>> 8) & 0xff;
306 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
309 cache_result
= (config
>> 16) & 0xff;
310 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
313 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
322 attr
->config1
= hw_cache_extra_regs
[cache_type
][cache_op
][cache_result
];
323 return x86_pmu_extra_regs(val
, event
);
326 int x86_reserve_hardware(void)
330 if (!atomic_inc_not_zero(&pmc_refcount
)) {
331 mutex_lock(&pmc_reserve_mutex
);
332 if (atomic_read(&pmc_refcount
) == 0) {
333 if (!reserve_pmc_hardware())
336 reserve_ds_buffers();
339 atomic_inc(&pmc_refcount
);
340 mutex_unlock(&pmc_reserve_mutex
);
346 void x86_release_hardware(void)
348 if (atomic_dec_and_mutex_lock(&pmc_refcount
, &pmc_reserve_mutex
)) {
349 release_pmc_hardware();
350 release_ds_buffers();
351 mutex_unlock(&pmc_reserve_mutex
);
356 * Check if we can create event of a certain type (that no conflicting events
359 int x86_add_exclusive(unsigned int what
)
363 if (!atomic_inc_not_zero(&x86_pmu
.lbr_exclusive
[what
])) {
364 mutex_lock(&pmc_reserve_mutex
);
365 for (i
= 0; i
< ARRAY_SIZE(x86_pmu
.lbr_exclusive
); i
++) {
366 if (i
!= what
&& atomic_read(&x86_pmu
.lbr_exclusive
[i
]))
369 atomic_inc(&x86_pmu
.lbr_exclusive
[what
]);
370 mutex_unlock(&pmc_reserve_mutex
);
373 atomic_inc(&active_events
);
377 mutex_unlock(&pmc_reserve_mutex
);
381 void x86_del_exclusive(unsigned int what
)
383 atomic_dec(&x86_pmu
.lbr_exclusive
[what
]);
384 atomic_dec(&active_events
);
387 int x86_setup_perfctr(struct perf_event
*event
)
389 struct perf_event_attr
*attr
= &event
->attr
;
390 struct hw_perf_event
*hwc
= &event
->hw
;
393 if (!is_sampling_event(event
)) {
394 hwc
->sample_period
= x86_pmu
.max_period
;
395 hwc
->last_period
= hwc
->sample_period
;
396 local64_set(&hwc
->period_left
, hwc
->sample_period
);
399 if (attr
->type
== PERF_TYPE_RAW
)
400 return x86_pmu_extra_regs(event
->attr
.config
, event
);
402 if (attr
->type
== PERF_TYPE_HW_CACHE
)
403 return set_ext_hw_attr(hwc
, event
);
405 if (attr
->config
>= x86_pmu
.max_events
)
411 config
= x86_pmu
.event_map(attr
->config
);
422 if (attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
&&
423 !attr
->freq
&& hwc
->sample_period
== 1) {
424 /* BTS is not supported by this architecture. */
425 if (!x86_pmu
.bts_active
)
428 /* BTS is currently only allowed for user-mode. */
429 if (!attr
->exclude_kernel
)
432 /* disallow bts if conflicting events are present */
433 if (x86_add_exclusive(x86_lbr_exclusive_lbr
))
436 event
->destroy
= hw_perf_lbr_event_destroy
;
439 hwc
->config
|= config
;
445 * check that branch_sample_type is compatible with
446 * settings needed for precise_ip > 1 which implies
447 * using the LBR to capture ALL taken branches at the
448 * priv levels of the measurement
450 static inline int precise_br_compat(struct perf_event
*event
)
452 u64 m
= event
->attr
.branch_sample_type
;
455 /* must capture all branches */
456 if (!(m
& PERF_SAMPLE_BRANCH_ANY
))
459 m
&= PERF_SAMPLE_BRANCH_KERNEL
| PERF_SAMPLE_BRANCH_USER
;
461 if (!event
->attr
.exclude_user
)
462 b
|= PERF_SAMPLE_BRANCH_USER
;
464 if (!event
->attr
.exclude_kernel
)
465 b
|= PERF_SAMPLE_BRANCH_KERNEL
;
468 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
474 int x86_pmu_hw_config(struct perf_event
*event
)
476 if (event
->attr
.precise_ip
) {
479 /* Support for constant skid */
480 if (x86_pmu
.pebs_active
&& !x86_pmu
.pebs_broken
) {
483 /* Support for IP fixup */
484 if (x86_pmu
.lbr_nr
|| x86_pmu
.intel_cap
.pebs_format
>= 2)
487 if (x86_pmu
.pebs_prec_dist
)
491 if (event
->attr
.precise_ip
> precise
)
495 * check that PEBS LBR correction does not conflict with
496 * whatever the user is asking with attr->branch_sample_type
498 if (event
->attr
.precise_ip
> 1 && x86_pmu
.intel_cap
.pebs_format
< 2) {
499 u64
*br_type
= &event
->attr
.branch_sample_type
;
501 if (has_branch_stack(event
)) {
502 if (!precise_br_compat(event
))
505 /* branch_sample_type is compatible */
509 * user did not specify branch_sample_type
511 * For PEBS fixups, we capture all
512 * the branches at the priv level of the
515 *br_type
= PERF_SAMPLE_BRANCH_ANY
;
517 if (!event
->attr
.exclude_user
)
518 *br_type
|= PERF_SAMPLE_BRANCH_USER
;
520 if (!event
->attr
.exclude_kernel
)
521 *br_type
|= PERF_SAMPLE_BRANCH_KERNEL
;
525 if (event
->attr
.branch_sample_type
& PERF_SAMPLE_BRANCH_CALL_STACK
)
526 event
->attach_state
|= PERF_ATTACH_TASK_DATA
;
530 * (keep 'enabled' bit clear for now)
532 event
->hw
.config
= ARCH_PERFMON_EVENTSEL_INT
;
535 * Count user and OS events unless requested not to
537 if (!event
->attr
.exclude_user
)
538 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_USR
;
539 if (!event
->attr
.exclude_kernel
)
540 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_OS
;
542 if (event
->attr
.type
== PERF_TYPE_RAW
)
543 event
->hw
.config
|= event
->attr
.config
& X86_RAW_EVENT_MASK
;
545 if (event
->attr
.sample_period
&& x86_pmu
.limit_period
) {
546 if (x86_pmu
.limit_period(event
, event
->attr
.sample_period
) >
547 event
->attr
.sample_period
)
551 return x86_setup_perfctr(event
);
555 * Setup the hardware configuration for a given attr_type
557 static int __x86_pmu_event_init(struct perf_event
*event
)
561 if (!x86_pmu_initialized())
564 err
= x86_reserve_hardware();
568 atomic_inc(&active_events
);
569 event
->destroy
= hw_perf_event_destroy
;
572 event
->hw
.last_cpu
= -1;
573 event
->hw
.last_tag
= ~0ULL;
576 event
->hw
.extra_reg
.idx
= EXTRA_REG_NONE
;
577 event
->hw
.branch_reg
.idx
= EXTRA_REG_NONE
;
579 return x86_pmu
.hw_config(event
);
582 void x86_pmu_disable_all(void)
584 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
587 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
590 if (!test_bit(idx
, cpuc
->active_mask
))
592 rdmsrl(x86_pmu_config_addr(idx
), val
);
593 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
595 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
596 wrmsrl(x86_pmu_config_addr(idx
), val
);
601 * There may be PMI landing after enabled=0. The PMI hitting could be before or
604 * If PMI hits before disable_all, the PMU will be disabled in the NMI handler.
605 * It will not be re-enabled in the NMI handler again, because enabled=0. After
606 * handling the NMI, disable_all will be called, which will not change the
607 * state either. If PMI hits after disable_all, the PMU is already disabled
608 * before entering NMI handler. The NMI handler will not change the state
611 * So either situation is harmless.
613 static void x86_pmu_disable(struct pmu
*pmu
)
615 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
617 if (!x86_pmu_initialized())
627 x86_pmu
.disable_all();
630 void x86_pmu_enable_all(int added
)
632 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
635 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
636 struct hw_perf_event
*hwc
= &cpuc
->events
[idx
]->hw
;
638 if (!test_bit(idx
, cpuc
->active_mask
))
641 __x86_pmu_enable_event(hwc
, ARCH_PERFMON_EVENTSEL_ENABLE
);
645 static struct pmu pmu
;
647 static inline int is_x86_event(struct perf_event
*event
)
649 return event
->pmu
== &pmu
;
653 * Event scheduler state:
655 * Assign events iterating over all events and counters, beginning
656 * with events with least weights first. Keep the current iterator
657 * state in struct sched_state.
661 int event
; /* event index */
662 int counter
; /* counter index */
663 int unassigned
; /* number of events to be assigned left */
664 int nr_gp
; /* number of GP counters used */
665 unsigned long used
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
668 /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
669 #define SCHED_STATES_MAX 2
676 struct event_constraint
**constraints
;
677 struct sched_state state
;
678 struct sched_state saved
[SCHED_STATES_MAX
];
682 * Initialize interator that runs through all events and counters.
684 static void perf_sched_init(struct perf_sched
*sched
, struct event_constraint
**constraints
,
685 int num
, int wmin
, int wmax
, int gpmax
)
689 memset(sched
, 0, sizeof(*sched
));
690 sched
->max_events
= num
;
691 sched
->max_weight
= wmax
;
692 sched
->max_gp
= gpmax
;
693 sched
->constraints
= constraints
;
695 for (idx
= 0; idx
< num
; idx
++) {
696 if (constraints
[idx
]->weight
== wmin
)
700 sched
->state
.event
= idx
; /* start with min weight */
701 sched
->state
.weight
= wmin
;
702 sched
->state
.unassigned
= num
;
705 static void perf_sched_save_state(struct perf_sched
*sched
)
707 if (WARN_ON_ONCE(sched
->saved_states
>= SCHED_STATES_MAX
))
710 sched
->saved
[sched
->saved_states
] = sched
->state
;
711 sched
->saved_states
++;
714 static bool perf_sched_restore_state(struct perf_sched
*sched
)
716 if (!sched
->saved_states
)
719 sched
->saved_states
--;
720 sched
->state
= sched
->saved
[sched
->saved_states
];
722 /* continue with next counter: */
723 clear_bit(sched
->state
.counter
++, sched
->state
.used
);
729 * Select a counter for the current event to schedule. Return true on
732 static bool __perf_sched_find_counter(struct perf_sched
*sched
)
734 struct event_constraint
*c
;
737 if (!sched
->state
.unassigned
)
740 if (sched
->state
.event
>= sched
->max_events
)
743 c
= sched
->constraints
[sched
->state
.event
];
744 /* Prefer fixed purpose counters */
745 if (c
->idxmsk64
& (~0ULL << INTEL_PMC_IDX_FIXED
)) {
746 idx
= INTEL_PMC_IDX_FIXED
;
747 for_each_set_bit_from(idx
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
748 if (!__test_and_set_bit(idx
, sched
->state
.used
))
753 /* Grab the first unused counter starting with idx */
754 idx
= sched
->state
.counter
;
755 for_each_set_bit_from(idx
, c
->idxmsk
, INTEL_PMC_IDX_FIXED
) {
756 if (!__test_and_set_bit(idx
, sched
->state
.used
)) {
757 if (sched
->state
.nr_gp
++ >= sched
->max_gp
)
767 sched
->state
.counter
= idx
;
770 perf_sched_save_state(sched
);
775 static bool perf_sched_find_counter(struct perf_sched
*sched
)
777 while (!__perf_sched_find_counter(sched
)) {
778 if (!perf_sched_restore_state(sched
))
786 * Go through all unassigned events and find the next one to schedule.
787 * Take events with the least weight first. Return true on success.
789 static bool perf_sched_next_event(struct perf_sched
*sched
)
791 struct event_constraint
*c
;
793 if (!sched
->state
.unassigned
|| !--sched
->state
.unassigned
)
798 sched
->state
.event
++;
799 if (sched
->state
.event
>= sched
->max_events
) {
801 sched
->state
.event
= 0;
802 sched
->state
.weight
++;
803 if (sched
->state
.weight
> sched
->max_weight
)
806 c
= sched
->constraints
[sched
->state
.event
];
807 } while (c
->weight
!= sched
->state
.weight
);
809 sched
->state
.counter
= 0; /* start with first counter */
815 * Assign a counter for each event.
817 int perf_assign_events(struct event_constraint
**constraints
, int n
,
818 int wmin
, int wmax
, int gpmax
, int *assign
)
820 struct perf_sched sched
;
822 perf_sched_init(&sched
, constraints
, n
, wmin
, wmax
, gpmax
);
825 if (!perf_sched_find_counter(&sched
))
828 assign
[sched
.state
.event
] = sched
.state
.counter
;
829 } while (perf_sched_next_event(&sched
));
831 return sched
.state
.unassigned
;
833 EXPORT_SYMBOL_GPL(perf_assign_events
);
835 int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
837 struct event_constraint
*c
;
838 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
839 struct perf_event
*e
;
840 int i
, wmin
, wmax
, unsched
= 0;
841 struct hw_perf_event
*hwc
;
843 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
845 if (x86_pmu
.start_scheduling
)
846 x86_pmu
.start_scheduling(cpuc
);
848 for (i
= 0, wmin
= X86_PMC_IDX_MAX
, wmax
= 0; i
< n
; i
++) {
849 cpuc
->event_constraint
[i
] = NULL
;
850 c
= x86_pmu
.get_event_constraints(cpuc
, i
, cpuc
->event_list
[i
]);
851 cpuc
->event_constraint
[i
] = c
;
853 wmin
= min(wmin
, c
->weight
);
854 wmax
= max(wmax
, c
->weight
);
858 * fastpath, try to reuse previous register
860 for (i
= 0; i
< n
; i
++) {
861 hwc
= &cpuc
->event_list
[i
]->hw
;
862 c
= cpuc
->event_constraint
[i
];
868 /* constraint still honored */
869 if (!test_bit(hwc
->idx
, c
->idxmsk
))
872 /* not already used */
873 if (test_bit(hwc
->idx
, used_mask
))
876 __set_bit(hwc
->idx
, used_mask
);
878 assign
[i
] = hwc
->idx
;
883 int gpmax
= x86_pmu
.num_counters
;
886 * Do not allow scheduling of more than half the available
889 * This helps avoid counter starvation of sibling thread by
890 * ensuring at most half the counters cannot be in exclusive
891 * mode. There is no designated counters for the limits. Any
892 * N/2 counters can be used. This helps with events with
893 * specific counter constraints.
895 if (is_ht_workaround_enabled() && !cpuc
->is_fake
&&
896 READ_ONCE(cpuc
->excl_cntrs
->exclusive_present
))
899 unsched
= perf_assign_events(cpuc
->event_constraint
, n
, wmin
,
900 wmax
, gpmax
, assign
);
904 * In case of success (unsched = 0), mark events as committed,
905 * so we do not put_constraint() in case new events are added
906 * and fail to be scheduled
908 * We invoke the lower level commit callback to lock the resource
910 * We do not need to do all of this in case we are called to
911 * validate an event group (assign == NULL)
913 if (!unsched
&& assign
) {
914 for (i
= 0; i
< n
; i
++) {
915 e
= cpuc
->event_list
[i
];
916 e
->hw
.flags
|= PERF_X86_EVENT_COMMITTED
;
917 if (x86_pmu
.commit_scheduling
)
918 x86_pmu
.commit_scheduling(cpuc
, i
, assign
[i
]);
921 for (i
= 0; i
< n
; i
++) {
922 e
= cpuc
->event_list
[i
];
924 * do not put_constraint() on comitted events,
925 * because they are good to go
927 if ((e
->hw
.flags
& PERF_X86_EVENT_COMMITTED
))
931 * release events that failed scheduling
933 if (x86_pmu
.put_event_constraints
)
934 x86_pmu
.put_event_constraints(cpuc
, e
);
938 if (x86_pmu
.stop_scheduling
)
939 x86_pmu
.stop_scheduling(cpuc
);
941 return unsched
? -EINVAL
: 0;
945 * dogrp: true if must collect siblings events (group)
946 * returns total number of events and error code
948 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
950 struct perf_event
*event
;
953 max_count
= x86_pmu
.num_counters
+ x86_pmu
.num_counters_fixed
;
955 /* current number of events already accepted */
958 if (is_x86_event(leader
)) {
961 cpuc
->event_list
[n
] = leader
;
967 list_for_each_entry(event
, &leader
->sibling_list
, group_entry
) {
968 if (!is_x86_event(event
) ||
969 event
->state
<= PERF_EVENT_STATE_OFF
)
975 cpuc
->event_list
[n
] = event
;
981 static inline void x86_assign_hw_event(struct perf_event
*event
,
982 struct cpu_hw_events
*cpuc
, int i
)
984 struct hw_perf_event
*hwc
= &event
->hw
;
986 hwc
->idx
= cpuc
->assign
[i
];
987 hwc
->last_cpu
= smp_processor_id();
988 hwc
->last_tag
= ++cpuc
->tags
[i
];
990 if (hwc
->idx
== INTEL_PMC_IDX_FIXED_BTS
) {
991 hwc
->config_base
= 0;
993 } else if (hwc
->idx
>= INTEL_PMC_IDX_FIXED
) {
994 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
995 hwc
->event_base
= MSR_ARCH_PERFMON_FIXED_CTR0
+ (hwc
->idx
- INTEL_PMC_IDX_FIXED
);
996 hwc
->event_base_rdpmc
= (hwc
->idx
- INTEL_PMC_IDX_FIXED
) | 1<<30;
998 hwc
->config_base
= x86_pmu_config_addr(hwc
->idx
);
999 hwc
->event_base
= x86_pmu_event_addr(hwc
->idx
);
1000 hwc
->event_base_rdpmc
= x86_pmu_rdpmc_index(hwc
->idx
);
1004 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
1005 struct cpu_hw_events
*cpuc
,
1008 return hwc
->idx
== cpuc
->assign
[i
] &&
1009 hwc
->last_cpu
== smp_processor_id() &&
1010 hwc
->last_tag
== cpuc
->tags
[i
];
1013 static void x86_pmu_start(struct perf_event
*event
, int flags
);
1015 static void x86_pmu_enable(struct pmu
*pmu
)
1017 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1018 struct perf_event
*event
;
1019 struct hw_perf_event
*hwc
;
1020 int i
, added
= cpuc
->n_added
;
1022 if (!x86_pmu_initialized())
1028 if (cpuc
->n_added
) {
1029 int n_running
= cpuc
->n_events
- cpuc
->n_added
;
1031 * apply assignment obtained either from
1032 * hw_perf_group_sched_in() or x86_pmu_enable()
1034 * step1: save events moving to new counters
1036 for (i
= 0; i
< n_running
; i
++) {
1037 event
= cpuc
->event_list
[i
];
1041 * we can avoid reprogramming counter if:
1042 * - assigned same counter as last time
1043 * - running on same CPU as last time
1044 * - no other event has used the counter since
1046 if (hwc
->idx
== -1 ||
1047 match_prev_assignment(hwc
, cpuc
, i
))
1051 * Ensure we don't accidentally enable a stopped
1052 * counter simply because we rescheduled.
1054 if (hwc
->state
& PERF_HES_STOPPED
)
1055 hwc
->state
|= PERF_HES_ARCH
;
1057 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1061 * step2: reprogram moved events into new counters
1063 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1064 event
= cpuc
->event_list
[i
];
1067 if (!match_prev_assignment(hwc
, cpuc
, i
))
1068 x86_assign_hw_event(event
, cpuc
, i
);
1069 else if (i
< n_running
)
1072 if (hwc
->state
& PERF_HES_ARCH
)
1075 x86_pmu_start(event
, PERF_EF_RELOAD
);
1078 perf_events_lapic_init();
1084 x86_pmu
.enable_all(added
);
1087 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
1090 * Set the next IRQ period, based on the hwc->period_left value.
1091 * To be called with the event disabled in hw:
1093 int x86_perf_event_set_period(struct perf_event
*event
)
1095 struct hw_perf_event
*hwc
= &event
->hw
;
1096 s64 left
= local64_read(&hwc
->period_left
);
1097 s64 period
= hwc
->sample_period
;
1098 int ret
= 0, idx
= hwc
->idx
;
1100 if (idx
== INTEL_PMC_IDX_FIXED_BTS
)
1104 * If we are way outside a reasonable range then just skip forward:
1106 if (unlikely(left
<= -period
)) {
1108 local64_set(&hwc
->period_left
, left
);
1109 hwc
->last_period
= period
;
1113 if (unlikely(left
<= 0)) {
1115 local64_set(&hwc
->period_left
, left
);
1116 hwc
->last_period
= period
;
1120 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1122 if (unlikely(left
< 2))
1125 if (left
> x86_pmu
.max_period
)
1126 left
= x86_pmu
.max_period
;
1128 if (x86_pmu
.limit_period
)
1129 left
= x86_pmu
.limit_period(event
, left
);
1131 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
1133 if (!(hwc
->flags
& PERF_X86_EVENT_AUTO_RELOAD
) ||
1134 local64_read(&hwc
->prev_count
) != (u64
)-left
) {
1136 * The hw event starts counting from this event offset,
1137 * mark it to be able to extra future deltas:
1139 local64_set(&hwc
->prev_count
, (u64
)-left
);
1141 wrmsrl(hwc
->event_base
, (u64
)(-left
) & x86_pmu
.cntval_mask
);
1145 * Due to erratum on certan cpu we need
1146 * a second write to be sure the register
1147 * is updated properly
1149 if (x86_pmu
.perfctr_second_write
) {
1150 wrmsrl(hwc
->event_base
,
1151 (u64
)(-left
) & x86_pmu
.cntval_mask
);
1154 perf_event_update_userpage(event
);
1159 void x86_pmu_enable_event(struct perf_event
*event
)
1161 if (__this_cpu_read(cpu_hw_events
.enabled
))
1162 __x86_pmu_enable_event(&event
->hw
,
1163 ARCH_PERFMON_EVENTSEL_ENABLE
);
1167 * Add a single event to the PMU.
1169 * The event is added to the group of enabled events
1170 * but only if it can be scehduled with existing events.
1172 static int x86_pmu_add(struct perf_event
*event
, int flags
)
1174 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1175 struct hw_perf_event
*hwc
;
1176 int assign
[X86_PMC_IDX_MAX
];
1181 n0
= cpuc
->n_events
;
1182 ret
= n
= collect_events(cpuc
, event
, false);
1186 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
1187 if (!(flags
& PERF_EF_START
))
1188 hwc
->state
|= PERF_HES_ARCH
;
1191 * If group events scheduling transaction was started,
1192 * skip the schedulability test here, it will be performed
1193 * at commit time (->commit_txn) as a whole.
1195 if (cpuc
->txn_flags
& PERF_PMU_TXN_ADD
)
1198 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1202 * copy new assignment, now we know it is possible
1203 * will be used by hw_perf_enable()
1205 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1209 * Commit the collect_events() state. See x86_pmu_del() and
1213 cpuc
->n_added
+= n
- n0
;
1214 cpuc
->n_txn
+= n
- n0
;
1221 static void x86_pmu_start(struct perf_event
*event
, int flags
)
1223 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1224 int idx
= event
->hw
.idx
;
1226 if (WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_STOPPED
)))
1229 if (WARN_ON_ONCE(idx
== -1))
1232 if (flags
& PERF_EF_RELOAD
) {
1233 WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_UPTODATE
));
1234 x86_perf_event_set_period(event
);
1237 event
->hw
.state
= 0;
1239 cpuc
->events
[idx
] = event
;
1240 __set_bit(idx
, cpuc
->active_mask
);
1241 __set_bit(idx
, cpuc
->running
);
1242 x86_pmu
.enable(event
);
1243 perf_event_update_userpage(event
);
1246 void perf_event_print_debug(void)
1248 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1250 struct cpu_hw_events
*cpuc
;
1251 unsigned long flags
;
1254 if (!x86_pmu
.num_counters
)
1257 local_irq_save(flags
);
1259 cpu
= smp_processor_id();
1260 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1262 if (x86_pmu
.version
>= 2) {
1263 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1264 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1265 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1266 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1269 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1270 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1271 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1272 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1273 if (x86_pmu
.pebs_constraints
) {
1274 rdmsrl(MSR_IA32_PEBS_ENABLE
, pebs
);
1275 pr_info("CPU#%d: pebs: %016llx\n", cpu
, pebs
);
1277 if (x86_pmu
.lbr_nr
) {
1278 rdmsrl(MSR_IA32_DEBUGCTLMSR
, debugctl
);
1279 pr_info("CPU#%d: debugctl: %016llx\n", cpu
, debugctl
);
1282 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1284 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1285 rdmsrl(x86_pmu_config_addr(idx
), pmc_ctrl
);
1286 rdmsrl(x86_pmu_event_addr(idx
), pmc_count
);
1288 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1290 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1291 cpu
, idx
, pmc_ctrl
);
1292 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1293 cpu
, idx
, pmc_count
);
1294 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1295 cpu
, idx
, prev_left
);
1297 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1298 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1300 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1301 cpu
, idx
, pmc_count
);
1303 local_irq_restore(flags
);
1306 void x86_pmu_stop(struct perf_event
*event
, int flags
)
1308 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1309 struct hw_perf_event
*hwc
= &event
->hw
;
1311 if (__test_and_clear_bit(hwc
->idx
, cpuc
->active_mask
)) {
1312 x86_pmu
.disable(event
);
1313 cpuc
->events
[hwc
->idx
] = NULL
;
1314 WARN_ON_ONCE(hwc
->state
& PERF_HES_STOPPED
);
1315 hwc
->state
|= PERF_HES_STOPPED
;
1318 if ((flags
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
1320 * Drain the remaining delta count out of a event
1321 * that we are disabling:
1323 x86_perf_event_update(event
);
1324 hwc
->state
|= PERF_HES_UPTODATE
;
1328 static void x86_pmu_del(struct perf_event
*event
, int flags
)
1330 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1334 * event is descheduled
1336 event
->hw
.flags
&= ~PERF_X86_EVENT_COMMITTED
;
1339 * If we're called during a txn, we don't need to do anything.
1340 * The events never got scheduled and ->cancel_txn will truncate
1343 * XXX assumes any ->del() called during a TXN will only be on
1344 * an event added during that same TXN.
1346 if (cpuc
->txn_flags
& PERF_PMU_TXN_ADD
)
1350 * Not a TXN, therefore cleanup properly.
1352 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1354 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1355 if (event
== cpuc
->event_list
[i
])
1359 if (WARN_ON_ONCE(i
== cpuc
->n_events
)) /* called ->del() without ->add() ? */
1362 /* If we have a newly added event; make sure to decrease n_added. */
1363 if (i
>= cpuc
->n_events
- cpuc
->n_added
)
1366 if (x86_pmu
.put_event_constraints
)
1367 x86_pmu
.put_event_constraints(cpuc
, event
);
1369 /* Delete the array entry. */
1370 while (++i
< cpuc
->n_events
) {
1371 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1372 cpuc
->event_constraint
[i
-1] = cpuc
->event_constraint
[i
];
1376 perf_event_update_userpage(event
);
1379 int x86_pmu_handle_irq(struct pt_regs
*regs
)
1381 struct perf_sample_data data
;
1382 struct cpu_hw_events
*cpuc
;
1383 struct perf_event
*event
;
1384 int idx
, handled
= 0;
1387 cpuc
= this_cpu_ptr(&cpu_hw_events
);
1390 * Some chipsets need to unmask the LVTPC in a particular spot
1391 * inside the nmi handler. As a result, the unmasking was pushed
1392 * into all the nmi handlers.
1394 * This generic handler doesn't seem to have any issues where the
1395 * unmasking occurs so it was left at the top.
1397 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1399 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1400 if (!test_bit(idx
, cpuc
->active_mask
)) {
1402 * Though we deactivated the counter some cpus
1403 * might still deliver spurious interrupts still
1404 * in flight. Catch them:
1406 if (__test_and_clear_bit(idx
, cpuc
->running
))
1411 event
= cpuc
->events
[idx
];
1413 val
= x86_perf_event_update(event
);
1414 if (val
& (1ULL << (x86_pmu
.cntval_bits
- 1)))
1421 perf_sample_data_init(&data
, 0, event
->hw
.last_period
);
1423 if (!x86_perf_event_set_period(event
))
1426 if (perf_event_overflow(event
, &data
, regs
))
1427 x86_pmu_stop(event
, 0);
1431 inc_irq_stat(apic_perf_irqs
);
1436 void perf_events_lapic_init(void)
1438 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1442 * Always use NMI for PMU
1444 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1448 perf_event_nmi_handler(unsigned int cmd
, struct pt_regs
*regs
)
1455 * All PMUs/events that share this PMI handler should make sure to
1456 * increment active_events for their events.
1458 if (!atomic_read(&active_events
))
1461 start_clock
= sched_clock();
1462 ret
= x86_pmu
.handle_irq(regs
);
1463 finish_clock
= sched_clock();
1465 perf_sample_event_took(finish_clock
- start_clock
);
1469 NOKPROBE_SYMBOL(perf_event_nmi_handler
);
1471 struct event_constraint emptyconstraint
;
1472 struct event_constraint unconstrained
;
1475 x86_pmu_notifier(struct notifier_block
*self
, unsigned long action
, void *hcpu
)
1477 unsigned int cpu
= (long)hcpu
;
1478 struct cpu_hw_events
*cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1479 int i
, ret
= NOTIFY_OK
;
1481 switch (action
& ~CPU_TASKS_FROZEN
) {
1482 case CPU_UP_PREPARE
:
1483 for (i
= 0 ; i
< X86_PERF_KFREE_MAX
; i
++)
1484 cpuc
->kfree_on_online
[i
] = NULL
;
1485 if (x86_pmu
.cpu_prepare
)
1486 ret
= x86_pmu
.cpu_prepare(cpu
);
1490 if (x86_pmu
.cpu_starting
)
1491 x86_pmu
.cpu_starting(cpu
);
1495 for (i
= 0 ; i
< X86_PERF_KFREE_MAX
; i
++) {
1496 kfree(cpuc
->kfree_on_online
[i
]);
1497 cpuc
->kfree_on_online
[i
] = NULL
;
1502 if (x86_pmu
.cpu_dying
)
1503 x86_pmu
.cpu_dying(cpu
);
1506 case CPU_UP_CANCELED
:
1508 if (x86_pmu
.cpu_dead
)
1509 x86_pmu
.cpu_dead(cpu
);
1519 static void __init
pmu_check_apic(void)
1525 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1526 pr_info("no hardware sampling interrupt available.\n");
1529 * If we have a PMU initialized but no APIC
1530 * interrupts, we cannot sample hardware
1531 * events (user-space has to fall back and
1532 * sample via a hrtimer based software event):
1534 pmu
.capabilities
|= PERF_PMU_CAP_NO_INTERRUPT
;
1538 static struct attribute_group x86_pmu_format_group
= {
1544 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1545 * out of events_attr attributes.
1547 static void __init
filter_events(struct attribute
**attrs
)
1549 struct device_attribute
*d
;
1550 struct perf_pmu_events_attr
*pmu_attr
;
1554 for (i
= 0; attrs
[i
]; i
++) {
1555 d
= (struct device_attribute
*)attrs
[i
];
1556 pmu_attr
= container_of(d
, struct perf_pmu_events_attr
, attr
);
1558 if (pmu_attr
->event_str
)
1560 if (x86_pmu
.event_map(i
+ offset
))
1563 for (j
= i
; attrs
[j
]; j
++)
1564 attrs
[j
] = attrs
[j
+ 1];
1566 /* Check the shifted attr. */
1570 * event_map() is index based, the attrs array is organized
1571 * by increasing event index. If we shift the events, then
1572 * we need to compensate for the event_map(), otherwise
1573 * we are looking up the wrong event in the map
1579 /* Merge two pointer arrays */
1580 __init
struct attribute
**merge_attr(struct attribute
**a
, struct attribute
**b
)
1582 struct attribute
**new;
1585 for (j
= 0; a
[j
]; j
++)
1587 for (i
= 0; b
[i
]; i
++)
1591 new = kmalloc(sizeof(struct attribute
*) * j
, GFP_KERNEL
);
1596 for (i
= 0; a
[i
]; i
++)
1598 for (i
= 0; b
[i
]; i
++)
1605 ssize_t
events_sysfs_show(struct device
*dev
, struct device_attribute
*attr
, char *page
)
1607 struct perf_pmu_events_attr
*pmu_attr
= \
1608 container_of(attr
, struct perf_pmu_events_attr
, attr
);
1609 u64 config
= x86_pmu
.event_map(pmu_attr
->id
);
1611 /* string trumps id */
1612 if (pmu_attr
->event_str
)
1613 return sprintf(page
, "%s", pmu_attr
->event_str
);
1615 return x86_pmu
.events_sysfs_show(page
, config
);
1617 EXPORT_SYMBOL_GPL(events_sysfs_show
);
1619 EVENT_ATTR(cpu
-cycles
, CPU_CYCLES
);
1620 EVENT_ATTR(instructions
, INSTRUCTIONS
);
1621 EVENT_ATTR(cache
-references
, CACHE_REFERENCES
);
1622 EVENT_ATTR(cache
-misses
, CACHE_MISSES
);
1623 EVENT_ATTR(branch
-instructions
, BRANCH_INSTRUCTIONS
);
1624 EVENT_ATTR(branch
-misses
, BRANCH_MISSES
);
1625 EVENT_ATTR(bus
-cycles
, BUS_CYCLES
);
1626 EVENT_ATTR(stalled
-cycles
-frontend
, STALLED_CYCLES_FRONTEND
);
1627 EVENT_ATTR(stalled
-cycles
-backend
, STALLED_CYCLES_BACKEND
);
1628 EVENT_ATTR(ref
-cycles
, REF_CPU_CYCLES
);
1630 static struct attribute
*empty_attrs
;
1632 static struct attribute
*events_attr
[] = {
1633 EVENT_PTR(CPU_CYCLES
),
1634 EVENT_PTR(INSTRUCTIONS
),
1635 EVENT_PTR(CACHE_REFERENCES
),
1636 EVENT_PTR(CACHE_MISSES
),
1637 EVENT_PTR(BRANCH_INSTRUCTIONS
),
1638 EVENT_PTR(BRANCH_MISSES
),
1639 EVENT_PTR(BUS_CYCLES
),
1640 EVENT_PTR(STALLED_CYCLES_FRONTEND
),
1641 EVENT_PTR(STALLED_CYCLES_BACKEND
),
1642 EVENT_PTR(REF_CPU_CYCLES
),
1646 static struct attribute_group x86_pmu_events_group
= {
1648 .attrs
= events_attr
,
1651 ssize_t
x86_event_sysfs_show(char *page
, u64 config
, u64 event
)
1653 u64 umask
= (config
& ARCH_PERFMON_EVENTSEL_UMASK
) >> 8;
1654 u64 cmask
= (config
& ARCH_PERFMON_EVENTSEL_CMASK
) >> 24;
1655 bool edge
= (config
& ARCH_PERFMON_EVENTSEL_EDGE
);
1656 bool pc
= (config
& ARCH_PERFMON_EVENTSEL_PIN_CONTROL
);
1657 bool any
= (config
& ARCH_PERFMON_EVENTSEL_ANY
);
1658 bool inv
= (config
& ARCH_PERFMON_EVENTSEL_INV
);
1662 * We have whole page size to spend and just little data
1663 * to write, so we can safely use sprintf.
1665 ret
= sprintf(page
, "event=0x%02llx", event
);
1668 ret
+= sprintf(page
+ ret
, ",umask=0x%02llx", umask
);
1671 ret
+= sprintf(page
+ ret
, ",edge");
1674 ret
+= sprintf(page
+ ret
, ",pc");
1677 ret
+= sprintf(page
+ ret
, ",any");
1680 ret
+= sprintf(page
+ ret
, ",inv");
1683 ret
+= sprintf(page
+ ret
, ",cmask=0x%02llx", cmask
);
1685 ret
+= sprintf(page
+ ret
, "\n");
1690 static int __init
init_hw_perf_events(void)
1692 struct x86_pmu_quirk
*quirk
;
1695 pr_info("Performance Events: ");
1697 switch (boot_cpu_data
.x86_vendor
) {
1698 case X86_VENDOR_INTEL
:
1699 err
= intel_pmu_init();
1701 case X86_VENDOR_AMD
:
1702 err
= amd_pmu_init();
1708 pr_cont("no PMU driver, software events only.\n");
1714 /* sanity check that the hardware exists or is emulated */
1715 if (!check_hw_exists())
1718 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1720 x86_pmu
.attr_rdpmc
= 1; /* enable userspace RDPMC usage by default */
1722 for (quirk
= x86_pmu
.quirks
; quirk
; quirk
= quirk
->next
)
1725 if (!x86_pmu
.intel_ctrl
)
1726 x86_pmu
.intel_ctrl
= (1 << x86_pmu
.num_counters
) - 1;
1728 perf_events_lapic_init();
1729 register_nmi_handler(NMI_LOCAL
, perf_event_nmi_handler
, 0, "PMI");
1731 unconstrained
= (struct event_constraint
)
1732 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_counters
) - 1,
1733 0, x86_pmu
.num_counters
, 0, 0);
1735 x86_pmu_format_group
.attrs
= x86_pmu
.format_attrs
;
1737 if (x86_pmu
.event_attrs
)
1738 x86_pmu_events_group
.attrs
= x86_pmu
.event_attrs
;
1740 if (!x86_pmu
.events_sysfs_show
)
1741 x86_pmu_events_group
.attrs
= &empty_attrs
;
1743 filter_events(x86_pmu_events_group
.attrs
);
1745 if (x86_pmu
.cpu_events
) {
1746 struct attribute
**tmp
;
1748 tmp
= merge_attr(x86_pmu_events_group
.attrs
, x86_pmu
.cpu_events
);
1750 x86_pmu_events_group
.attrs
= tmp
;
1753 pr_info("... version: %d\n", x86_pmu
.version
);
1754 pr_info("... bit width: %d\n", x86_pmu
.cntval_bits
);
1755 pr_info("... generic registers: %d\n", x86_pmu
.num_counters
);
1756 pr_info("... value mask: %016Lx\n", x86_pmu
.cntval_mask
);
1757 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1758 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_counters_fixed
);
1759 pr_info("... event mask: %016Lx\n", x86_pmu
.intel_ctrl
);
1761 perf_pmu_register(&pmu
, "cpu", PERF_TYPE_RAW
);
1762 perf_cpu_notifier(x86_pmu_notifier
);
1766 early_initcall(init_hw_perf_events
);
1768 static inline void x86_pmu_read(struct perf_event
*event
)
1770 x86_perf_event_update(event
);
1774 * Start group events scheduling transaction
1775 * Set the flag to make pmu::enable() not perform the
1776 * schedulability test, it will be performed at commit time
1778 * We only support PERF_PMU_TXN_ADD transactions. Save the
1779 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1782 static void x86_pmu_start_txn(struct pmu
*pmu
, unsigned int txn_flags
)
1784 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1786 WARN_ON_ONCE(cpuc
->txn_flags
); /* txn already in flight */
1788 cpuc
->txn_flags
= txn_flags
;
1789 if (txn_flags
& ~PERF_PMU_TXN_ADD
)
1792 perf_pmu_disable(pmu
);
1793 __this_cpu_write(cpu_hw_events
.n_txn
, 0);
1797 * Stop group events scheduling transaction
1798 * Clear the flag and pmu::enable() will perform the
1799 * schedulability test.
1801 static void x86_pmu_cancel_txn(struct pmu
*pmu
)
1803 unsigned int txn_flags
;
1804 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1806 WARN_ON_ONCE(!cpuc
->txn_flags
); /* no txn in flight */
1808 txn_flags
= cpuc
->txn_flags
;
1809 cpuc
->txn_flags
= 0;
1810 if (txn_flags
& ~PERF_PMU_TXN_ADD
)
1814 * Truncate collected array by the number of events added in this
1815 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
1817 __this_cpu_sub(cpu_hw_events
.n_added
, __this_cpu_read(cpu_hw_events
.n_txn
));
1818 __this_cpu_sub(cpu_hw_events
.n_events
, __this_cpu_read(cpu_hw_events
.n_txn
));
1819 perf_pmu_enable(pmu
);
1823 * Commit group events scheduling transaction
1824 * Perform the group schedulability test as a whole
1825 * Return 0 if success
1827 * Does not cancel the transaction on failure; expects the caller to do this.
1829 static int x86_pmu_commit_txn(struct pmu
*pmu
)
1831 struct cpu_hw_events
*cpuc
= this_cpu_ptr(&cpu_hw_events
);
1832 int assign
[X86_PMC_IDX_MAX
];
1835 WARN_ON_ONCE(!cpuc
->txn_flags
); /* no txn in flight */
1837 if (cpuc
->txn_flags
& ~PERF_PMU_TXN_ADD
) {
1838 cpuc
->txn_flags
= 0;
1844 if (!x86_pmu_initialized())
1847 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1852 * copy new assignment, now we know it is possible
1853 * will be used by hw_perf_enable()
1855 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1857 cpuc
->txn_flags
= 0;
1858 perf_pmu_enable(pmu
);
1862 * a fake_cpuc is used to validate event groups. Due to
1863 * the extra reg logic, we need to also allocate a fake
1864 * per_core and per_cpu structure. Otherwise, group events
1865 * using extra reg may conflict without the kernel being
1866 * able to catch this when the last event gets added to
1869 static void free_fake_cpuc(struct cpu_hw_events
*cpuc
)
1871 kfree(cpuc
->shared_regs
);
1875 static struct cpu_hw_events
*allocate_fake_cpuc(void)
1877 struct cpu_hw_events
*cpuc
;
1878 int cpu
= raw_smp_processor_id();
1880 cpuc
= kzalloc(sizeof(*cpuc
), GFP_KERNEL
);
1882 return ERR_PTR(-ENOMEM
);
1884 /* only needed, if we have extra_regs */
1885 if (x86_pmu
.extra_regs
) {
1886 cpuc
->shared_regs
= allocate_shared_regs(cpu
);
1887 if (!cpuc
->shared_regs
)
1893 free_fake_cpuc(cpuc
);
1894 return ERR_PTR(-ENOMEM
);
1898 * validate that we can schedule this event
1900 static int validate_event(struct perf_event
*event
)
1902 struct cpu_hw_events
*fake_cpuc
;
1903 struct event_constraint
*c
;
1906 fake_cpuc
= allocate_fake_cpuc();
1907 if (IS_ERR(fake_cpuc
))
1908 return PTR_ERR(fake_cpuc
);
1910 c
= x86_pmu
.get_event_constraints(fake_cpuc
, -1, event
);
1912 if (!c
|| !c
->weight
)
1915 if (x86_pmu
.put_event_constraints
)
1916 x86_pmu
.put_event_constraints(fake_cpuc
, event
);
1918 free_fake_cpuc(fake_cpuc
);
1924 * validate a single event group
1926 * validation include:
1927 * - check events are compatible which each other
1928 * - events do not compete for the same counter
1929 * - number of events <= number of counters
1931 * validation ensures the group can be loaded onto the
1932 * PMU if it was the only group available.
1934 static int validate_group(struct perf_event
*event
)
1936 struct perf_event
*leader
= event
->group_leader
;
1937 struct cpu_hw_events
*fake_cpuc
;
1938 int ret
= -EINVAL
, n
;
1940 fake_cpuc
= allocate_fake_cpuc();
1941 if (IS_ERR(fake_cpuc
))
1942 return PTR_ERR(fake_cpuc
);
1944 * the event is not yet connected with its
1945 * siblings therefore we must first collect
1946 * existing siblings, then add the new event
1947 * before we can simulate the scheduling
1949 n
= collect_events(fake_cpuc
, leader
, true);
1953 fake_cpuc
->n_events
= n
;
1954 n
= collect_events(fake_cpuc
, event
, false);
1958 fake_cpuc
->n_events
= n
;
1960 ret
= x86_pmu
.schedule_events(fake_cpuc
, n
, NULL
);
1963 free_fake_cpuc(fake_cpuc
);
1967 static int x86_pmu_event_init(struct perf_event
*event
)
1972 switch (event
->attr
.type
) {
1974 case PERF_TYPE_HARDWARE
:
1975 case PERF_TYPE_HW_CACHE
:
1982 err
= __x86_pmu_event_init(event
);
1985 * we temporarily connect event to its pmu
1986 * such that validate_group() can classify
1987 * it as an x86 event using is_x86_event()
1992 if (event
->group_leader
!= event
)
1993 err
= validate_group(event
);
1995 err
= validate_event(event
);
2001 event
->destroy(event
);
2004 if (ACCESS_ONCE(x86_pmu
.attr_rdpmc
))
2005 event
->hw
.flags
|= PERF_X86_EVENT_RDPMC_ALLOWED
;
2010 static void refresh_pce(void *ignored
)
2013 load_mm_cr4(current
->mm
);
2016 static void x86_pmu_event_mapped(struct perf_event
*event
)
2018 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2021 if (atomic_inc_return(¤t
->mm
->context
.perf_rdpmc_allowed
) == 1)
2022 on_each_cpu_mask(mm_cpumask(current
->mm
), refresh_pce
, NULL
, 1);
2025 static void x86_pmu_event_unmapped(struct perf_event
*event
)
2030 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2033 if (atomic_dec_and_test(¤t
->mm
->context
.perf_rdpmc_allowed
))
2034 on_each_cpu_mask(mm_cpumask(current
->mm
), refresh_pce
, NULL
, 1);
2037 static int x86_pmu_event_idx(struct perf_event
*event
)
2039 int idx
= event
->hw
.idx
;
2041 if (!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
))
2044 if (x86_pmu
.num_counters_fixed
&& idx
>= INTEL_PMC_IDX_FIXED
) {
2045 idx
-= INTEL_PMC_IDX_FIXED
;
2052 static ssize_t
get_attr_rdpmc(struct device
*cdev
,
2053 struct device_attribute
*attr
,
2056 return snprintf(buf
, 40, "%d\n", x86_pmu
.attr_rdpmc
);
2059 static ssize_t
set_attr_rdpmc(struct device
*cdev
,
2060 struct device_attribute
*attr
,
2061 const char *buf
, size_t count
)
2066 ret
= kstrtoul(buf
, 0, &val
);
2073 if (x86_pmu
.attr_rdpmc_broken
)
2076 if ((val
== 2) != (x86_pmu
.attr_rdpmc
== 2)) {
2078 * Changing into or out of always available, aka
2079 * perf-event-bypassing mode. This path is extremely slow,
2080 * but only root can trigger it, so it's okay.
2083 static_key_slow_inc(&rdpmc_always_available
);
2085 static_key_slow_dec(&rdpmc_always_available
);
2086 on_each_cpu(refresh_pce
, NULL
, 1);
2089 x86_pmu
.attr_rdpmc
= val
;
2094 static DEVICE_ATTR(rdpmc
, S_IRUSR
| S_IWUSR
, get_attr_rdpmc
, set_attr_rdpmc
);
2096 static struct attribute
*x86_pmu_attrs
[] = {
2097 &dev_attr_rdpmc
.attr
,
2101 static struct attribute_group x86_pmu_attr_group
= {
2102 .attrs
= x86_pmu_attrs
,
2105 static const struct attribute_group
*x86_pmu_attr_groups
[] = {
2106 &x86_pmu_attr_group
,
2107 &x86_pmu_format_group
,
2108 &x86_pmu_events_group
,
2112 static void x86_pmu_sched_task(struct perf_event_context
*ctx
, bool sched_in
)
2114 if (x86_pmu
.sched_task
)
2115 x86_pmu
.sched_task(ctx
, sched_in
);
2118 void perf_check_microcode(void)
2120 if (x86_pmu
.check_microcode
)
2121 x86_pmu
.check_microcode();
2123 EXPORT_SYMBOL_GPL(perf_check_microcode
);
2125 static struct pmu pmu
= {
2126 .pmu_enable
= x86_pmu_enable
,
2127 .pmu_disable
= x86_pmu_disable
,
2129 .attr_groups
= x86_pmu_attr_groups
,
2131 .event_init
= x86_pmu_event_init
,
2133 .event_mapped
= x86_pmu_event_mapped
,
2134 .event_unmapped
= x86_pmu_event_unmapped
,
2138 .start
= x86_pmu_start
,
2139 .stop
= x86_pmu_stop
,
2140 .read
= x86_pmu_read
,
2142 .start_txn
= x86_pmu_start_txn
,
2143 .cancel_txn
= x86_pmu_cancel_txn
,
2144 .commit_txn
= x86_pmu_commit_txn
,
2146 .event_idx
= x86_pmu_event_idx
,
2147 .sched_task
= x86_pmu_sched_task
,
2148 .task_ctx_size
= sizeof(struct x86_perf_task_context
),
2151 void arch_perf_update_userpage(struct perf_event
*event
,
2152 struct perf_event_mmap_page
*userpg
, u64 now
)
2154 struct cyc2ns_data
*data
;
2156 userpg
->cap_user_time
= 0;
2157 userpg
->cap_user_time_zero
= 0;
2158 userpg
->cap_user_rdpmc
=
2159 !!(event
->hw
.flags
& PERF_X86_EVENT_RDPMC_ALLOWED
);
2160 userpg
->pmc_width
= x86_pmu
.cntval_bits
;
2162 if (!sched_clock_stable())
2165 data
= cyc2ns_read_begin();
2168 * Internal timekeeping for enabled/running/stopped times
2169 * is always in the local_clock domain.
2171 userpg
->cap_user_time
= 1;
2172 userpg
->time_mult
= data
->cyc2ns_mul
;
2173 userpg
->time_shift
= data
->cyc2ns_shift
;
2174 userpg
->time_offset
= data
->cyc2ns_offset
- now
;
2177 * cap_user_time_zero doesn't make sense when we're using a different
2178 * time base for the records.
2180 if (event
->clock
== &local_clock
) {
2181 userpg
->cap_user_time_zero
= 1;
2182 userpg
->time_zero
= data
->cyc2ns_offset
;
2185 cyc2ns_read_end(data
);
2192 static int backtrace_stack(void *data
, char *name
)
2197 static int backtrace_address(void *data
, unsigned long addr
, int reliable
)
2199 struct perf_callchain_entry
*entry
= data
;
2201 return perf_callchain_store(entry
, addr
);
2204 static const struct stacktrace_ops backtrace_ops
= {
2205 .stack
= backtrace_stack
,
2206 .address
= backtrace_address
,
2207 .walk_stack
= print_context_stack_bp
,
2211 perf_callchain_kernel(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
2213 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2214 /* TODO: We don't support guest os callchain now */
2218 perf_callchain_store(entry
, regs
->ip
);
2220 dump_trace(NULL
, regs
, NULL
, 0, &backtrace_ops
, entry
);
2224 valid_user_frame(const void __user
*fp
, unsigned long size
)
2226 return (__range_not_ok(fp
, size
, TASK_SIZE
) == 0);
2229 static unsigned long get_segment_base(unsigned int segment
)
2231 struct desc_struct
*desc
;
2232 int idx
= segment
>> 3;
2234 if ((segment
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2235 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2236 struct ldt_struct
*ldt
;
2238 if (idx
> LDT_ENTRIES
)
2241 /* IRQs are off, so this synchronizes with smp_store_release */
2242 ldt
= lockless_dereference(current
->active_mm
->context
.ldt
);
2243 if (!ldt
|| idx
> ldt
->size
)
2246 desc
= &ldt
->entries
[idx
];
2251 if (idx
> GDT_ENTRIES
)
2254 desc
= raw_cpu_ptr(gdt_page
.gdt
) + idx
;
2257 return get_desc_base(desc
);
2260 #ifdef CONFIG_IA32_EMULATION
2262 #include <asm/compat.h>
2265 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
2267 /* 32-bit process in 64-bit kernel. */
2268 unsigned long ss_base
, cs_base
;
2269 struct stack_frame_ia32 frame
;
2270 const void __user
*fp
;
2272 if (!test_thread_flag(TIF_IA32
))
2275 cs_base
= get_segment_base(regs
->cs
);
2276 ss_base
= get_segment_base(regs
->ss
);
2278 fp
= compat_ptr(ss_base
+ regs
->bp
);
2279 pagefault_disable();
2280 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
2281 unsigned long bytes
;
2282 frame
.next_frame
= 0;
2283 frame
.return_address
= 0;
2285 if (!access_ok(VERIFY_READ
, fp
, 8))
2288 bytes
= __copy_from_user_nmi(&frame
.next_frame
, fp
, 4);
2291 bytes
= __copy_from_user_nmi(&frame
.return_address
, fp
+4, 4);
2295 if (!valid_user_frame(fp
, sizeof(frame
)))
2298 perf_callchain_store(entry
, cs_base
+ frame
.return_address
);
2299 fp
= compat_ptr(ss_base
+ frame
.next_frame
);
2306 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
2313 perf_callchain_user(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
2315 struct stack_frame frame
;
2316 const void __user
*fp
;
2318 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2319 /* TODO: We don't support guest os callchain now */
2324 * We don't know what to do with VM86 stacks.. ignore them for now.
2326 if (regs
->flags
& (X86_VM_MASK
| PERF_EFLAGS_VM
))
2329 fp
= (void __user
*)regs
->bp
;
2331 perf_callchain_store(entry
, regs
->ip
);
2336 if (perf_callchain_user32(regs
, entry
))
2339 pagefault_disable();
2340 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
2341 unsigned long bytes
;
2342 frame
.next_frame
= NULL
;
2343 frame
.return_address
= 0;
2345 if (!access_ok(VERIFY_READ
, fp
, 16))
2348 bytes
= __copy_from_user_nmi(&frame
.next_frame
, fp
, 8);
2351 bytes
= __copy_from_user_nmi(&frame
.return_address
, fp
+8, 8);
2355 if (!valid_user_frame(fp
, sizeof(frame
)))
2358 perf_callchain_store(entry
, frame
.return_address
);
2359 fp
= (void __user
*)frame
.next_frame
;
2365 * Deal with code segment offsets for the various execution modes:
2367 * VM86 - the good olde 16 bit days, where the linear address is
2368 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2370 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2371 * to figure out what the 32bit base address is.
2373 * X32 - has TIF_X32 set, but is running in x86_64
2375 * X86_64 - CS,DS,SS,ES are all zero based.
2377 static unsigned long code_segment_base(struct pt_regs
*regs
)
2380 * For IA32 we look at the GDT/LDT segment base to convert the
2381 * effective IP to a linear address.
2384 #ifdef CONFIG_X86_32
2386 * If we are in VM86 mode, add the segment offset to convert to a
2389 if (regs
->flags
& X86_VM_MASK
)
2390 return 0x10 * regs
->cs
;
2392 if (user_mode(regs
) && regs
->cs
!= __USER_CS
)
2393 return get_segment_base(regs
->cs
);
2395 if (user_mode(regs
) && !user_64bit_mode(regs
) &&
2396 regs
->cs
!= __USER32_CS
)
2397 return get_segment_base(regs
->cs
);
2402 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
2404 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest())
2405 return perf_guest_cbs
->get_guest_ip();
2407 return regs
->ip
+ code_segment_base(regs
);
2410 unsigned long perf_misc_flags(struct pt_regs
*regs
)
2414 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
2415 if (perf_guest_cbs
->is_user_mode())
2416 misc
|= PERF_RECORD_MISC_GUEST_USER
;
2418 misc
|= PERF_RECORD_MISC_GUEST_KERNEL
;
2420 if (user_mode(regs
))
2421 misc
|= PERF_RECORD_MISC_USER
;
2423 misc
|= PERF_RECORD_MISC_KERNEL
;
2426 if (regs
->flags
& PERF_EFLAGS_EXACT
)
2427 misc
|= PERF_RECORD_MISC_EXACT_IP
;
2432 void perf_get_x86_pmu_capability(struct x86_pmu_capability
*cap
)
2434 cap
->version
= x86_pmu
.version
;
2435 cap
->num_counters_gp
= x86_pmu
.num_counters
;
2436 cap
->num_counters_fixed
= x86_pmu
.num_counters_fixed
;
2437 cap
->bit_width_gp
= x86_pmu
.cntval_bits
;
2438 cap
->bit_width_fixed
= x86_pmu
.cntval_bits
;
2439 cap
->events_mask
= (unsigned int)x86_pmu
.events_maskl
;
2440 cap
->events_mask_len
= x86_pmu
.events_mask_len
;
2442 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability
);