arch/x86/include/asm/apic.h

   1 #ifndef _ASM_X86_APIC_H
   2 #define _ASM_X86_APIC_H
   3
   4 #include <linux/cpumask.h>
   5 #include <linux/delay.h>
   6 #include <linux/pm.h>
   7
   8 #include <asm/alternative.h>
   9 #include <asm/cpufeature.h>
  10 #include <asm/processor.h>
  11 #include <asm/apicdef.h>
  12 #include <asm/atomic.h>
  13 #include <asm/fixmap.h>
  14 #include <asm/mpspec.h>
  15 #include <asm/system.h>
  16 #include <asm/msr.h>
  17
  18 #define ARCH_APICTIMER_STOPS_ON_C3      1
  19
  20 /*
  21  * Debugging macros
  22  */
  23 #define APIC_QUIET   0
  24 #define APIC_VERBOSE 1
  25 #define APIC_DEBUG   2
  26
  27 /*
  28  * Define the default level of output to be very little
  29  * This can be turned up by using apic=verbose for more
  30  * information and apic=debug for _lots_ of information.
  31  * apic_verbosity is defined in apic.c
  32  */
  33 #define apic_printk(v, s, a...) do {       \
  34                 if ((v) <= apic_verbosity) \
  35                         printk(s, ##a);    \
  36         } while (0)
  37
  38
  39 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
  40 extern void generic_apic_probe(void);
  41 #else
  42 static inline void generic_apic_probe(void)
  43 {
  44 }
  45 #endif
  46
  47 #ifdef CONFIG_X86_LOCAL_APIC
  48
  49 extern unsigned int apic_verbosity;
  50 extern int local_apic_timer_c2_ok;
  51
  52 extern int disable_apic;
  53
  54 #ifdef CONFIG_SMP
  55 extern void __inquire_remote_apic(int apicid);
  56 #else /* CONFIG_SMP */
  57 static inline void __inquire_remote_apic(int apicid)
  58 {
  59 }
  60 #endif /* CONFIG_SMP */
  61
  62 static inline void default_inquire_remote_apic(int apicid)
  63 {
  64         if (apic_verbosity >= APIC_DEBUG)
  65                 __inquire_remote_apic(apicid);
  66 }
  67
  68 /*
  69  * Basic functions accessing APICs.
  70  */
  71 #ifdef CONFIG_PARAVIRT
  72 #include <asm/paravirt.h>
  73 #else
  74 #define setup_boot_clock setup_boot_APIC_clock
  75 #define setup_secondary_clock setup_secondary_APIC_clock
  76 #endif
  77
  78 #ifdef CONFIG_X86_VSMP
  79 extern int is_vsmp_box(void);
  80 #else
  81 static inline int is_vsmp_box(void)
  82 {
  83         return 0;
  84 }
  85 #endif
  86 extern void xapic_wait_icr_idle(void);
  87 extern u32 safe_xapic_wait_icr_idle(void);
  88 extern void xapic_icr_write(u32, u32);
  89 extern int setup_profiling_timer(unsigned int);
  90
  91 static inline void native_apic_mem_write(u32 reg, u32 v)
  92 {
  93         volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
  94
  95         alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
  96                        ASM_OUTPUT2("=r" (v), "=m" (*addr)),
  97                        ASM_OUTPUT2("0" (v), "m" (*addr)));
  98 }
  99
 100 static inline u32 native_apic_mem_read(u32 reg)
 101 {
 102         return *((volatile u32 *)(APIC_BASE + reg));
 103 }
 104
 105 extern void native_apic_wait_icr_idle(void);
 106 extern u32 native_safe_apic_wait_icr_idle(void);
 107 extern void native_apic_icr_write(u32 low, u32 id);
 108 extern u64 native_apic_icr_read(void);
 109
 110 #ifdef CONFIG_X86_X2APIC
 111 static inline void native_apic_msr_write(u32 reg, u32 v)
 112 {
 113         if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
 114             reg == APIC_LVR)
 115                 return;
 116
 117         wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
 118 }
 119
 120 static inline u32 native_apic_msr_read(u32 reg)
 121 {
 122         u32 low, high;
 123
 124         if (reg == APIC_DFR)
 125                 return -1;
 126
 127         rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
 128         return low;
 129 }
 130
 131 static inline void native_x2apic_wait_icr_idle(void)
 132 {
 133         /* no need to wait for icr idle in x2apic */
 134         return;
 135 }
 136
 137 static inline u32 native_safe_x2apic_wait_icr_idle(void)
 138 {
 139         /* no need to wait for icr idle in x2apic */
 140         return 0;
 141 }
 142
 143 static inline void native_x2apic_icr_write(u32 low, u32 id)
 144 {
 145         wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
 146 }
 147
 148 static inline u64 native_x2apic_icr_read(void)
 149 {
 150         unsigned long val;
 151
 152         rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
 153         return val;
 154 }
 155
 156 extern int x2apic, x2apic_phys;
 157 extern void check_x2apic(void);
 158 extern void enable_x2apic(void);
 159 extern void enable_IR_x2apic(void);
 160 extern void x2apic_icr_write(u32 low, u32 id);
 161 static inline int x2apic_enabled(void)
 162 {
 163         int msr, msr2;
 164
 165         if (!cpu_has_x2apic)
 166                 return 0;
 167
 168         rdmsr(MSR_IA32_APICBASE, msr, msr2);
 169         if (msr & X2APIC_ENABLE)
 170                 return 1;
 171         return 0;
 172 }
 173 #else
 174 static inline void check_x2apic(void)
 175 {
 176 }
 177 static inline void enable_x2apic(void)
 178 {
 179 }
 180 static inline void enable_IR_x2apic(void)
 181 {
 182 }
 183 static inline int x2apic_enabled(void)
 184 {
 185         return 0;
 186 }
 187
 188 #define x2apic  0
 189
 190 #endif
 191
 192 extern int get_physical_broadcast(void);
 193
 194 #ifdef CONFIG_X86_X2APIC
 195 static inline void ack_x2APIC_irq(void)
 196 {
 197         /* Docs say use 0 for future compatibility */
 198         native_apic_msr_write(APIC_EOI, 0);
 199 }
 200 #endif
 201
 202 extern int lapic_get_maxlvt(void);
 203 extern void clear_local_APIC(void);
 204 extern void connect_bsp_APIC(void);
 205 extern void disconnect_bsp_APIC(int virt_wire_setup);
 206 extern void disable_local_APIC(void);
 207 extern void lapic_shutdown(void);
 208 extern int verify_local_APIC(void);
 209 extern void cache_APIC_registers(void);
 210 extern void sync_Arb_IDs(void);
 211 extern void init_bsp_APIC(void);
 212 extern void setup_local_APIC(void);
 213 extern void end_local_APIC_setup(void);
 214 extern void init_apic_mappings(void);
 215 extern void setup_boot_APIC_clock(void);
 216 extern void setup_secondary_APIC_clock(void);
 217 extern int APIC_init_uniprocessor(void);
 218 extern void enable_NMI_through_LVT0(void);
 219
 220 /*
 221  * On 32bit this is mach-xxx local
 222  */
 223 #ifdef CONFIG_X86_64
 224 extern void early_init_lapic_mapping(void);
 225 extern int apic_is_clustered_box(void);
 226 #else
 227 static inline int apic_is_clustered_box(void)
 228 {
 229         return 0;
 230 }
 231 #endif
 232
 233 extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
 234 extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
 235
 236
 237 #else /* !CONFIG_X86_LOCAL_APIC */
 238 static inline void lapic_shutdown(void) { }
 239 #define local_apic_timer_c2_ok          1
 240 static inline void init_apic_mappings(void) { }
 241 static inline void disable_local_APIC(void) { }
 242
 243 #endif /* !CONFIG_X86_LOCAL_APIC */
 244
 245 #ifdef CONFIG_X86_64
 246 #define SET_APIC_ID(x)          (apic->set_apic_id(x))
 247 #else
 248
 249 #endif
 250
 251 /*
 252  * Copyright 2004 James Cleverdon, IBM.
 253  * Subject to the GNU Public License, v.2
 254  *
 255  * Generic APIC sub-arch data struct.
 256  *
 257  * Hacked for x86-64 by James Cleverdon from i386 architecture code by
 258  * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
 259  * James Cleverdon.
 260  */
 261 struct apic {
 262         char *name;
 263
 264         int (*probe)(void);
 265         int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
 266         int (*apic_id_registered)(void);
 267
 268         u32 irq_delivery_mode;
 269         u32 irq_dest_mode;
 270
 271         const struct cpumask *(*target_cpus)(void);
 272
 273         int disable_esr;
 274
 275         int dest_logical;
 276         unsigned long (*check_apicid_used)(physid_mask_t bitmap, int apicid);
 277         unsigned long (*check_apicid_present)(int apicid);
 278
 279         void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
 280         void (*init_apic_ldr)(void);
 281
 282         physid_mask_t (*ioapic_phys_id_map)(physid_mask_t map);
 283
 284         void (*setup_apic_routing)(void);
 285         int (*multi_timer_check)(int apic, int irq);
 286         int (*apicid_to_node)(int logical_apicid);
 287         int (*cpu_to_logical_apicid)(int cpu);
 288         int (*cpu_present_to_apicid)(int mps_cpu);
 289         physid_mask_t (*apicid_to_cpu_present)(int phys_apicid);
 290         void (*setup_portio_remap)(void);
 291         int (*check_phys_apicid_present)(int boot_cpu_physical_apicid);
 292         void (*enable_apic_mode)(void);
 293         int (*phys_pkg_id)(int cpuid_apic, int index_msb);
 294
 295         /*
 296          * When one of the next two hooks returns 1 the apic
 297          * is switched to this. Essentially they are additional
 298          * probe functions:
 299          */
 300         int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
 301
 302         unsigned int (*get_apic_id)(unsigned long x);
 303         unsigned long (*set_apic_id)(unsigned int id);
 304         unsigned long apic_id_mask;
 305
 306         unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask);
 307         unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
 308                                                const struct cpumask *andmask);
 309
 310         /* ipi */
 311         void (*send_IPI_mask)(const struct cpumask *mask, int vector);
 312         void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
 313                                          int vector);
 314         void (*send_IPI_allbutself)(int vector);
 315         void (*send_IPI_all)(int vector);
 316         void (*send_IPI_self)(int vector);
 317
 318         /* wakeup_secondary_cpu */
 319         int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
 320
 321         int trampoline_phys_low;
 322         int trampoline_phys_high;
 323
 324         void (*wait_for_init_deassert)(atomic_t *deassert);
 325         void (*smp_callin_clear_local_apic)(void);
 326         void (*inquire_remote_apic)(int apicid);
 327
 328         /* apic ops */
 329         u32 (*read)(u32 reg);
 330         void (*write)(u32 reg, u32 v);
 331         u64 (*icr_read)(void);
 332         void (*icr_write)(u32 low, u32 high);
 333         void (*wait_icr_idle)(void);
 334         u32 (*safe_wait_icr_idle)(void);
 335 };
 336
 337 /*
 338  * Pointer to the local APIC driver in use on this system (there's
 339  * always just one such driver in use - the kernel decides via an
 340  * early probing process which one it picks - and then sticks to it):
 341  */
 342 extern struct apic *apic;
 343
 344 /*
 345  * APIC functionality to boot other CPUs - only used on SMP:
 346  */
 347 #ifdef CONFIG_SMP
 348 extern atomic_t init_deasserted;
 349 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
 350 #endif
 351
 352 static inline u32 apic_read(u32 reg)
 353 {
 354         return apic->read(reg);
 355 }
 356
 357 static inline void apic_write(u32 reg, u32 val)
 358 {
 359         apic->write(reg, val);
 360 }
 361
 362 static inline u64 apic_icr_read(void)
 363 {
 364         return apic->icr_read();
 365 }
 366
 367 static inline void apic_icr_write(u32 low, u32 high)
 368 {
 369         apic->icr_write(low, high);
 370 }
 371
 372 static inline void apic_wait_icr_idle(void)
 373 {
 374         apic->wait_icr_idle();
 375 }
 376
 377 static inline u32 safe_apic_wait_icr_idle(void)
 378 {
 379         return apic->safe_wait_icr_idle();
 380 }
 381
 382
 383 static inline void ack_APIC_irq(void)
 384 {
 385 #ifdef CONFIG_X86_LOCAL_APIC
 386         /*
 387          * ack_APIC_irq() actually gets compiled as a single instruction
 388          * ... yummie.
 389          */
 390
 391         /* Docs say use 0 for future compatibility */
 392         apic_write(APIC_EOI, 0);
 393 #endif
 394 }
 395
 396 static inline unsigned default_get_apic_id(unsigned long x)
 397 {
 398         unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
 399
 400         if (APIC_XAPIC(ver))
 401                 return (x >> 24) & 0xFF;
 402         else
 403                 return (x >> 24) & 0x0F;
 404 }
 405
 406 /*
 407  * Warm reset vector default position:
 408  */
 409 #define DEFAULT_TRAMPOLINE_PHYS_LOW             0x467
 410 #define DEFAULT_TRAMPOLINE_PHYS_HIGH            0x469
 411
 412 #ifdef CONFIG_X86_64
 413 extern struct apic apic_flat;
 414 extern struct apic apic_physflat;
 415 extern struct apic apic_x2apic_cluster;
 416 extern struct apic apic_x2apic_phys;
 417 extern int default_acpi_madt_oem_check(char *, char *);
 418
 419 extern void apic_send_IPI_self(int vector);
 420
 421 extern struct apic apic_x2apic_uv_x;
 422 DECLARE_PER_CPU(int, x2apic_extra_bits);
 423
 424 extern int default_cpu_present_to_apicid(int mps_cpu);
 425 extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
 426 #endif
 427
 428 static inline void default_wait_for_init_deassert(atomic_t *deassert)
 429 {
 430         while (!atomic_read(deassert))
 431                 cpu_relax();
 432         return;
 433 }
 434
 435 extern void generic_bigsmp_probe(void);
 436
 437
 438 #ifdef CONFIG_X86_LOCAL_APIC
 439
 440 #include <asm/smp.h>
 441
 442 #define APIC_DFR_VALUE  (APIC_DFR_FLAT)
 443
 444 static inline const struct cpumask *default_target_cpus(void)
 445 {
 446 #ifdef CONFIG_SMP
 447         return cpu_online_mask;
 448 #else
 449         return cpumask_of(0);
 450 #endif
 451 }
 452
 453 DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
 454
 455
 456 static inline unsigned int read_apic_id(void)
 457 {
 458         unsigned int reg;
 459
 460         reg = apic_read(APIC_ID);
 461
 462         return apic->get_apic_id(reg);
 463 }
 464
 465 extern void default_setup_apic_routing(void);
 466
 467 #ifdef CONFIG_X86_32
 468 /*
 469  * Set up the logical destination ID.
 470  *
 471  * Intel recommends to set DFR, LDR and TPR before enabling
 472  * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
 473  * document number 292116).  So here it goes...
 474  */
 475 extern void default_init_apic_ldr(void);
 476
 477 static inline int default_apic_id_registered(void)
 478 {
 479         return physid_isset(read_apic_id(), phys_cpu_present_map);
 480 }
 481
 482 static inline unsigned int
 483 default_cpu_mask_to_apicid(const struct cpumask *cpumask)
 484 {
 485         return cpumask_bits(cpumask)[0];
 486 }
 487
 488 static inline unsigned int
 489 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 490                                const struct cpumask *andmask)
 491 {
 492         unsigned long mask1 = cpumask_bits(cpumask)[0];
 493         unsigned long mask2 = cpumask_bits(andmask)[0];
 494         unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
 495
 496         return (unsigned int)(mask1 & mask2 & mask3);
 497 }
 498
 499 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
 500 {
 501         return cpuid_apic >> index_msb;
 502 }
 503
 504 extern int default_apicid_to_node(int logical_apicid);
 505
 506 #endif
 507
 508 static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid)
 509 {
 510         return physid_isset(apicid, bitmap);
 511 }
 512
 513 static inline unsigned long default_check_apicid_present(int bit)
 514 {
 515         return physid_isset(bit, phys_cpu_present_map);
 516 }
 517
 518 static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map)
 519 {
 520         return phys_map;
 521 }
 522
 523 /* Mapping from cpu number to logical apicid */
 524 static inline int default_cpu_to_logical_apicid(int cpu)
 525 {
 526         return 1 << cpu;
 527 }
 528
 529 static inline int __default_cpu_present_to_apicid(int mps_cpu)
 530 {
 531         if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
 532                 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
 533         else
 534                 return BAD_APICID;
 535 }
 536
 537 static inline int
 538 __default_check_phys_apicid_present(int boot_cpu_physical_apicid)
 539 {
 540         return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
 541 }
 542
 543 #ifdef CONFIG_X86_32
 544 static inline int default_cpu_present_to_apicid(int mps_cpu)
 545 {
 546         return __default_cpu_present_to_apicid(mps_cpu);
 547 }
 548
 549 static inline int
 550 default_check_phys_apicid_present(int boot_cpu_physical_apicid)
 551 {
 552         return __default_check_phys_apicid_present(boot_cpu_physical_apicid);
 553 }
 554 #else
 555 extern int default_cpu_present_to_apicid(int mps_cpu);
 556 extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
 557 #endif
 558
 559 static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid)
 560 {
 561         return physid_mask_of_physid(phys_apicid);
 562 }
 563
 564 #endif /* CONFIG_X86_LOCAL_APIC */
 565
 566 #ifdef CONFIG_X86_32
 567 extern u8 cpu_2_logical_apicid[NR_CPUS];
 568 #endif
 569
 570 #endif /* _ASM_X86_APIC_H */