arch/x86/include/asm/bigsmp/apic.h

   1 #ifndef __ASM_MACH_APIC_H
   2 #define __ASM_MACH_APIC_H
   3
   4 #define xapic_phys_to_log_apicid(cpu) (per_cpu(x86_bios_cpu_apicid, cpu))
   5 #define esr_disable (1)
   6
   7 static inline int apic_id_registered(void)
   8 {
   9         return (1);
  10 }
  11
  12 static inline cpumask_t target_cpus(void)
  13 {
  14 #ifdef CONFIG_SMP
  15         return cpu_online_map;
  16 #else
  17         return cpumask_of_cpu(0);
  18 #endif
  19 }
  20
  21 #undef APIC_DEST_LOGICAL
  22 #define APIC_DEST_LOGICAL       0
  23 #define APIC_DFR_VALUE          (APIC_DFR_FLAT)
  24 #define INT_DELIVERY_MODE       (dest_Fixed)
  25 #define INT_DEST_MODE           (0)    /* phys delivery to target proc */
  26 #define NO_BALANCE_IRQ          (0)
  27 #define WAKE_SECONDARY_VIA_INIT
  28
  29
  30 static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
  31 {
  32         return (0);
  33 }
  34
  35 static inline unsigned long check_apicid_present(int bit)
  36 {
  37         return (1);
  38 }
  39
  40 static inline unsigned long calculate_ldr(int cpu)
  41 {
  42         unsigned long val, id;
  43         val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
  44         id = xapic_phys_to_log_apicid(cpu);
  45         val |= SET_APIC_LOGICAL_ID(id);
  46         return val;
  47 }
  48
  49 /*
  50  * Set up the logical destination ID.
  51  *
  52  * Intel recommends to set DFR, LDR and TPR before enabling
  53  * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
  54  * document number 292116).  So here it goes...
  55  */
  56 static inline void init_apic_ldr(void)
  57 {
  58         unsigned long val;
  59         int cpu = smp_processor_id();
  60
  61         apic_write(APIC_DFR, APIC_DFR_VALUE);
  62         val = calculate_ldr(cpu);
  63         apic_write(APIC_LDR, val);
  64 }
  65
  66 static inline void setup_apic_routing(void)
  67 {
  68         printk("Enabling APIC mode:  %s.  Using %d I/O APICs\n",
  69                 "Physflat", nr_ioapics);
  70 }
  71
  72 static inline int multi_timer_check(int apic, int irq)
  73 {
  74         return (0);
  75 }
  76
  77 static inline int apicid_to_node(int logical_apicid)
  78 {
  79         return apicid_2_node[hard_smp_processor_id()];
  80 }
  81
  82 static inline int cpu_present_to_apicid(int mps_cpu)
  83 {
  84         if (mps_cpu < NR_CPUS)
  85                 return (int) per_cpu(x86_bios_cpu_apicid, mps_cpu);
  86
  87         return BAD_APICID;
  88 }
  89
  90 static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
  91 {
  92         return physid_mask_of_physid(phys_apicid);
  93 }
  94
  95 extern u8 cpu_2_logical_apicid[];
  96 /* Mapping from cpu number to logical apicid */
  97 static inline int cpu_to_logical_apicid(int cpu)
  98 {
  99         if (cpu >= NR_CPUS)
 100                 return BAD_APICID;
 101         return cpu_physical_id(cpu);
 102 }
 103
 104 static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
 105 {
 106         /* For clustered we don't have a good way to do this yet - hack */
 107         return physids_promote(0xFFL);
 108 }
 109
 110 static inline void setup_portio_remap(void)
 111 {
 112 }
 113
 114 static inline void enable_apic_mode(void)
 115 {
 116 }
 117
 118 static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
 119 {
 120         return (1);
 121 }
 122
 123 /* As we are using single CPU as destination, pick only one CPU here */
 124 static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
 125 {
 126         int cpu;
 127         int apicid;
 128
 129         cpu = first_cpu(cpumask);
 130         apicid = cpu_to_logical_apicid(cpu);
 131         return apicid;
 132 }
 133
 134 static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
 135 {
 136         return cpuid_apic >> index_msb;
 137 }
 138
 139 #endif /* __ASM_MACH_APIC_H */