1 #ifndef _ASM_X86_MACH_DEFAULT_MACH_APIC_H
2 #define _ASM_X86_MACH_DEFAULT_MACH_APIC_H
4 #ifdef CONFIG_X86_LOCAL_APIC
6 #include <mach_apicdef.h>
9 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
11 static inline cpumask_t
target_cpus(void)
14 return cpu_online_map
;
16 return cpumask_of_cpu(0);
20 #define NO_BALANCE_IRQ (0)
21 #define esr_disable (0)
24 #include <asm/genapic.h>
25 #define INT_DELIVERY_MODE (genapic->int_delivery_mode)
26 #define INT_DEST_MODE (genapic->int_dest_mode)
27 #define TARGET_CPUS (genapic->target_cpus())
28 #define apic_id_registered (genapic->apic_id_registered)
29 #define init_apic_ldr (genapic->init_apic_ldr)
30 #define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid)
31 #define phys_pkg_id (genapic->phys_pkg_id)
32 #define vector_allocation_domain (genapic->vector_allocation_domain)
33 #define read_apic_id() (GET_APIC_ID(apic_read(APIC_ID)))
34 #define send_IPI_self (genapic->send_IPI_self)
35 extern void setup_apic_routing(void);
37 #define INT_DELIVERY_MODE dest_LowestPrio
38 #define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */
39 #define TARGET_CPUS (target_cpus())
41 * Set up the logical destination ID.
43 * Intel recommends to set DFR, LDR and TPR before enabling
44 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
45 * document number 292116). So here it goes...
47 static inline void init_apic_ldr(void)
51 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
52 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
53 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
54 apic_write(APIC_LDR
, val
);
57 static inline int apic_id_registered(void)
59 return physid_isset(read_apic_id(), phys_cpu_present_map
);
62 static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask
)
64 return cpus_addr(cpumask
)[0];
67 static inline u32
phys_pkg_id(u32 cpuid_apic
, int index_msb
)
69 return cpuid_apic
>> index_msb
;
72 static inline void setup_apic_routing(void)
74 #ifdef CONFIG_X86_IO_APIC
75 printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
80 static inline int apicid_to_node(int logical_apicid
)
83 return apicid_2_node
[hard_smp_processor_id()];
89 static inline cpumask_t
vector_allocation_domain(int cpu
)
91 /* Careful. Some cpus do not strictly honor the set of cpus
92 * specified in the interrupt destination when using lowest
93 * priority interrupt delivery mode.
95 * In particular there was a hyperthreading cpu observed to
96 * deliver interrupts to the wrong hyperthread when only one
97 * hyperthread was specified in the interrupt desitination.
99 cpumask_t domain
= { { [0] = APIC_ALL_CPUS
, } };
104 static inline unsigned long check_apicid_used(physid_mask_t bitmap
, int apicid
)
106 return physid_isset(apicid
, bitmap
);
109 static inline unsigned long check_apicid_present(int bit
)
111 return physid_isset(bit
, phys_cpu_present_map
);
114 static inline physid_mask_t
ioapic_phys_id_map(physid_mask_t phys_map
)
119 static inline int multi_timer_check(int apic
, int irq
)
124 /* Mapping from cpu number to logical apicid */
125 static inline int cpu_to_logical_apicid(int cpu
)
130 static inline int cpu_present_to_apicid(int mps_cpu
)
132 if (mps_cpu
< NR_CPUS
&& cpu_present(mps_cpu
))
133 return (int)per_cpu(x86_bios_cpu_apicid
, mps_cpu
);
138 static inline physid_mask_t
apicid_to_cpu_present(int phys_apicid
)
140 return physid_mask_of_physid(phys_apicid
);
143 static inline void setup_portio_remap(void)
147 static inline int check_phys_apicid_present(int boot_cpu_physical_apicid
)
149 return physid_isset(boot_cpu_physical_apicid
, phys_cpu_present_map
);
152 static inline void enable_apic_mode(void)
155 #endif /* CONFIG_X86_LOCAL_APIC */
156 #endif /* _ASM_X86_MACH_DEFAULT_MACH_APIC_H */
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