arch/x86/include/asm/mce.h

   1 #ifndef _ASM_X86_MCE_H
   2 #define _ASM_X86_MCE_H
   3
   4 #include <uapi/asm/mce.h>
   5
   6 /*
   7  * Machine Check support for x86
   8  */
   9
  10 /* MCG_CAP register defines */
  11 #define MCG_BANKCNT_MASK        0xff         /* Number of Banks */
  12 #define MCG_CTL_P               (1ULL<<8)    /* MCG_CTL register available */
  13 #define MCG_EXT_P               (1ULL<<9)    /* Extended registers available */
  14 #define MCG_CMCI_P              (1ULL<<10)   /* CMCI supported */
  15 #define MCG_EXT_CNT_MASK        0xff0000     /* Number of Extended registers */
  16 #define MCG_EXT_CNT_SHIFT       16
  17 #define MCG_EXT_CNT(c)          (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
  18 #define MCG_SER_P               (1ULL<<24)   /* MCA recovery/new status bits */
  19 #define MCG_ELOG_P              (1ULL<<26)   /* Extended error log supported */
  20 #define MCG_LMCE_P              (1ULL<<27)   /* Local machine check supported */
  21
  22 /* MCG_STATUS register defines */
  23 #define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
  24 #define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
  25 #define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */
  26 #define MCG_STATUS_LMCES (1ULL<<3)   /* LMCE signaled */
  27
  28 /* MCG_EXT_CTL register defines */
  29 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Enable LMCE */
  30
  31 /* MCi_STATUS register defines */
  32 #define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
  33 #define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
  34 #define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
  35 #define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
  36 #define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
  37 #define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
  38 #define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
  39 #define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
  40 #define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
  41
  42 /* AMD-specific bits */
  43 #define MCI_STATUS_DEFERRED     (1ULL<<44)  /* uncorrected error, deferred exception */
  44 #define MCI_STATUS_POISON       (1ULL<<43)  /* access poisonous data */
  45 #define MCI_STATUS_TCC          (1ULL<<55)  /* Task context corrupt */
  46
  47 /*
  48  * McaX field if set indicates a given bank supports MCA extensions:
  49  *  - Deferred error interrupt type is specifiable by bank.
  50  *  - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers,
  51  *    But should not be used to determine MSR numbers.
  52  *  - TCC bit is present in MCx_STATUS.
  53  */
  54 #define MCI_CONFIG_MCAX         0x1
  55 #define MCI_IPID_MCATYPE        0xFFFF0000
  56 #define MCI_IPID_HWID           0xFFF
  57
  58 /*
  59  * Note that the full MCACOD field of IA32_MCi_STATUS MSR is
  60  * bits 15:0.  But bit 12 is the 'F' bit, defined for corrected
  61  * errors to indicate that errors are being filtered by hardware.
  62  * We should mask out bit 12 when looking for specific signatures
  63  * of uncorrected errors - so the F bit is deliberately skipped
  64  * in this #define.
  65  */
  66 #define MCACOD            0xefff     /* MCA Error Code */
  67
  68 /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
  69 #define MCACOD_SCRUB    0x00C0  /* 0xC0-0xCF Memory Scrubbing */
  70 #define MCACOD_SCRUBMSK 0xeff0  /* Skip bit 12 ('F' bit) */
  71 #define MCACOD_L3WB     0x017A  /* L3 Explicit Writeback */
  72 #define MCACOD_DATA     0x0134  /* Data Load */
  73 #define MCACOD_INSTR    0x0150  /* Instruction Fetch */
  74
  75 /* MCi_MISC register defines */
  76 #define MCI_MISC_ADDR_LSB(m)    ((m) & 0x3f)
  77 #define MCI_MISC_ADDR_MODE(m)   (((m) >> 6) & 7)
  78 #define  MCI_MISC_ADDR_SEGOFF   0       /* segment offset */
  79 #define  MCI_MISC_ADDR_LINEAR   1       /* linear address */
  80 #define  MCI_MISC_ADDR_PHYS     2       /* physical address */
  81 #define  MCI_MISC_ADDR_MEM      3       /* memory address */
  82 #define  MCI_MISC_ADDR_GENERIC  7       /* generic */
  83
  84 /* CTL2 register defines */
  85 #define MCI_CTL2_CMCI_EN                (1ULL << 30)
  86 #define MCI_CTL2_CMCI_THRESHOLD_MASK    0x7fffULL
  87
  88 #define MCJ_CTX_MASK            3
  89 #define MCJ_CTX(flags)          ((flags) & MCJ_CTX_MASK)
  90 #define MCJ_CTX_RANDOM          0    /* inject context: random */
  91 #define MCJ_CTX_PROCESS         0x1  /* inject context: process */
  92 #define MCJ_CTX_IRQ             0x2  /* inject context: IRQ */
  93 #define MCJ_NMI_BROADCAST       0x4  /* do NMI broadcasting */
  94 #define MCJ_EXCEPTION           0x8  /* raise as exception */
  95 #define MCJ_IRQ_BROADCAST       0x10 /* do IRQ broadcasting */
  96
  97 #define MCE_OVERFLOW 0          /* bit 0 in flags means overflow */
  98
  99 /* Software defined banks */
 100 #define MCE_EXTENDED_BANK       128
 101 #define MCE_THERMAL_BANK        (MCE_EXTENDED_BANK + 0)
 102
 103 #define MCE_LOG_LEN 32
 104 #define MCE_LOG_SIGNATURE       "MACHINECHECK"
 105
 106 /* AMD Scalable MCA */
 107 #define MSR_AMD64_SMCA_MC0_MISC0        0xc0002003
 108 #define MSR_AMD64_SMCA_MC0_CONFIG       0xc0002004
 109 #define MSR_AMD64_SMCA_MC0_IPID         0xc0002005
 110 #define MSR_AMD64_SMCA_MC0_MISC1        0xc000200a
 111 #define MSR_AMD64_SMCA_MCx_MISC(x)      (MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x))
 112 #define MSR_AMD64_SMCA_MCx_CONFIG(x)    (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
 113 #define MSR_AMD64_SMCA_MCx_IPID(x)      (MSR_AMD64_SMCA_MC0_IPID + 0x10*(x))
 114 #define MSR_AMD64_SMCA_MCx_MISCy(x, y)  ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))
 115
 116 /*
 117  * This structure contains all data related to the MCE log.  Also
 118  * carries a signature to make it easier to find from external
 119  * debugging tools.  Each entry is only valid when its finished flag
 120  * is set.
 121  */
 122 struct mce_log {
 123         char signature[12]; /* "MACHINECHECK" */
 124         unsigned len;       /* = MCE_LOG_LEN */
 125         unsigned next;
 126         unsigned flags;
 127         unsigned recordlen;     /* length of struct mce */
 128         struct mce entry[MCE_LOG_LEN];
 129 };
 130
 131 struct mca_config {
 132         bool dont_log_ce;
 133         bool cmci_disabled;
 134         bool lmce_disabled;
 135         bool ignore_ce;
 136         bool disabled;
 137         bool ser;
 138         bool recovery;
 139         bool bios_cmci_threshold;
 140         u8 banks;
 141         s8 bootlog;
 142         int tolerant;
 143         int monarch_timeout;
 144         int panic_timeout;
 145         u32 rip_msr;
 146 };
 147
 148 struct mce_vendor_flags {
 149         /*
 150          * Indicates that overflow conditions are not fatal, when set.
 151          */
 152         __u64 overflow_recov    : 1,
 153
 154         /*
 155          * (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and
 156          * Recovery. It indicates support for data poisoning in HW and deferred
 157          * error interrupts.
 158          */
 159               succor            : 1,
 160
 161         /*
 162          * (AMD) SMCA: This bit indicates support for Scalable MCA which expands
 163          * the register space for each MCA bank and also increases number of
 164          * banks. Also, to accommodate the new banks and registers, the MCA
 165          * register space is moved to a new MSR range.
 166          */
 167               smca              : 1,
 168
 169               __reserved_0      : 61;
 170 };
 171 extern struct mce_vendor_flags mce_flags;
 172
 173 extern struct mca_config mca_cfg;
 174 extern void mce_register_decode_chain(struct notifier_block *nb);
 175 extern void mce_unregister_decode_chain(struct notifier_block *nb);
 176
 177 #include <linux/percpu.h>
 178 #include <linux/atomic.h>
 179
 180 extern int mce_p5_enabled;
 181
 182 #ifdef CONFIG_X86_MCE
 183 int mcheck_init(void);
 184 void mcheck_cpu_init(struct cpuinfo_x86 *c);
 185 void mcheck_cpu_clear(struct cpuinfo_x86 *c);
 186 void mcheck_vendor_init_severity(void);
 187 #else
 188 static inline int mcheck_init(void) { return 0; }
 189 static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
 190 static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
 191 static inline void mcheck_vendor_init_severity(void) {}
 192 #endif
 193
 194 #ifdef CONFIG_X86_ANCIENT_MCE
 195 void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
 196 void winchip_mcheck_init(struct cpuinfo_x86 *c);
 197 static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
 198 #else
 199 static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
 200 static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
 201 static inline void enable_p5_mce(void) {}
 202 #endif
 203
 204 void mce_setup(struct mce *m);
 205 void mce_log(struct mce *m);
 206 DECLARE_PER_CPU(struct device *, mce_device);
 207
 208 /*
 209  * Maximum banks number.
 210  * This is the limit of the current register layout on
 211  * Intel CPUs.
 212  */
 213 #define MAX_NR_BANKS 32
 214
 215 #ifdef CONFIG_X86_MCE_INTEL
 216 void mce_intel_feature_init(struct cpuinfo_x86 *c);
 217 void mce_intel_feature_clear(struct cpuinfo_x86 *c);
 218 void cmci_clear(void);
 219 void cmci_reenable(void);
 220 void cmci_rediscover(void);
 221 void cmci_recheck(void);
 222 #else
 223 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
 224 static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
 225 static inline void cmci_clear(void) {}
 226 static inline void cmci_reenable(void) {}
 227 static inline void cmci_rediscover(void) {}
 228 static inline void cmci_recheck(void) {}
 229 #endif
 230
 231 #ifdef CONFIG_X86_MCE_AMD
 232 void mce_amd_feature_init(struct cpuinfo_x86 *c);
 233 #else
 234 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
 235 #endif
 236
 237 int mce_available(struct cpuinfo_x86 *c);
 238
 239 DECLARE_PER_CPU(unsigned, mce_exception_count);
 240 DECLARE_PER_CPU(unsigned, mce_poll_count);
 241
 242 typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
 243 DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
 244
 245 enum mcp_flags {
 246         MCP_TIMESTAMP   = BIT(0),       /* log time stamp */
 247         MCP_UC          = BIT(1),       /* log uncorrected errors */
 248         MCP_DONTLOG     = BIT(2),       /* only clear, don't log */
 249 };
 250 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
 251
 252 int mce_notify_irq(void);
 253
 254 DECLARE_PER_CPU(struct mce, injectm);
 255
 256 extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
 257                                     const char __user *ubuf,
 258                                     size_t usize, loff_t *off));
 259
 260 /* Disable CMCI/polling for MCA bank claimed by firmware */
 261 extern void mce_disable_bank(int bank);
 262
 263 /*
 264  * Exception handler
 265  */
 266
 267 /* Call the installed machine check handler for this CPU setup. */
 268 extern void (*machine_check_vector)(struct pt_regs *, long error_code);
 269 void do_machine_check(struct pt_regs *, long);
 270
 271 /*
 272  * Threshold handler
 273  */
 274
 275 extern void (*mce_threshold_vector)(void);
 276 extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
 277
 278 /* Deferred error interrupt handler */
 279 extern void (*deferred_error_int_vector)(void);
 280
 281 /*
 282  * Thermal handler
 283  */
 284
 285 void intel_init_thermal(struct cpuinfo_x86 *c);
 286
 287 void mce_log_therm_throt_event(__u64 status);
 288
 289 /* Interrupt Handler for core thermal thresholds */
 290 extern int (*platform_thermal_notify)(__u64 msr_val);
 291
 292 /* Interrupt Handler for package thermal thresholds */
 293 extern int (*platform_thermal_package_notify)(__u64 msr_val);
 294
 295 /* Callback support of rate control, return true, if
 296  * callback has rate control */
 297 extern bool (*platform_thermal_package_rate_control)(void);
 298
 299 #ifdef CONFIG_X86_THERMAL_VECTOR
 300 extern void mcheck_intel_therm_init(void);
 301 #else
 302 static inline void mcheck_intel_therm_init(void) { }
 303 #endif
 304
 305 /*
 306  * Used by APEI to report memory error via /dev/mcelog
 307  */
 308
 309 struct cper_sec_mem_err;
 310 extern void apei_mce_report_mem_error(int corrected,
 311                                       struct cper_sec_mem_err *mem_err);
 312
 313 /*
 314  * Enumerate new IP types and HWID values in AMD processors which support
 315  * Scalable MCA.
 316  */
 317 #ifdef CONFIG_X86_MCE_AMD
 318 enum amd_ip_types {
 319         SMCA_F17H_CORE = 0,     /* Core errors */
 320         SMCA_DF,                /* Data Fabric */
 321         SMCA_UMC,               /* Unified Memory Controller */
 322         SMCA_PB,                /* Parameter Block */
 323         SMCA_PSP,               /* Platform Security Processor */
 324         SMCA_SMU,               /* System Management Unit */
 325         N_AMD_IP_TYPES
 326 };
 327
 328 struct amd_hwid {
 329         const char *name;
 330         unsigned int hwid;
 331 };
 332
 333 extern struct amd_hwid amd_hwids[N_AMD_IP_TYPES];
 334
 335 enum amd_core_mca_blocks {
 336         SMCA_LS = 0,    /* Load Store */
 337         SMCA_IF,        /* Instruction Fetch */
 338         SMCA_L2_CACHE,  /* L2 cache */
 339         SMCA_DE,        /* Decoder unit */
 340         RES,            /* Reserved */
 341         SMCA_EX,        /* Execution unit */
 342         SMCA_FP,        /* Floating Point */
 343         SMCA_L3_CACHE,  /* L3 cache */
 344         N_CORE_MCA_BLOCKS
 345 };
 346
 347 extern const char * const amd_core_mcablock_names[N_CORE_MCA_BLOCKS];
 348
 349 enum amd_df_mca_blocks {
 350         SMCA_CS = 0,    /* Coherent Slave */
 351         SMCA_PIE,       /* Power management, Interrupts, etc */
 352         N_DF_BLOCKS
 353 };
 354
 355 extern const char * const amd_df_mcablock_names[N_DF_BLOCKS];
 356 #endif
 357
 358 #endif /* _ASM_X86_MCE_H */