arch/x86/include/asm/mce.h

   1 #ifndef _ASM_X86_MCE_H
   2 #define _ASM_X86_MCE_H
   3
   4 #include <uapi/asm/mce.h>
   5
   6 /*
   7  * Machine Check support for x86
   8  */
   9
  10 /* MCG_CAP register defines */
  11 #define MCG_BANKCNT_MASK        0xff         /* Number of Banks */
  12 #define MCG_CTL_P               (1ULL<<8)    /* MCG_CTL register available */
  13 #define MCG_EXT_P               (1ULL<<9)    /* Extended registers available */
  14 #define MCG_CMCI_P              (1ULL<<10)   /* CMCI supported */
  15 #define MCG_EXT_CNT_MASK        0xff0000     /* Number of Extended registers */
  16 #define MCG_EXT_CNT_SHIFT       16
  17 #define MCG_EXT_CNT(c)          (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
  18 #define MCG_SER_P               (1ULL<<24)   /* MCA recovery/new status bits */
  19 #define MCG_ELOG_P              (1ULL<<26)   /* Extended error log supported */
  20
  21 /* MCG_STATUS register defines */
  22 #define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
  23 #define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
  24 #define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */
  25
  26 /* MCi_STATUS register defines */
  27 #define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
  28 #define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
  29 #define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
  30 #define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
  31 #define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
  32 #define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
  33 #define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
  34 #define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
  35 #define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
  36
  37 /*
  38  * Note that the full MCACOD field of IA32_MCi_STATUS MSR is
  39  * bits 15:0.  But bit 12 is the 'F' bit, defined for corrected
  40  * errors to indicate that errors are being filtered by hardware.
  41  * We should mask out bit 12 when looking for specific signatures
  42  * of uncorrected errors - so the F bit is deliberately skipped
  43  * in this #define.
  44  */
  45 #define MCACOD            0xefff     /* MCA Error Code */
  46
  47 /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
  48 #define MCACOD_SCRUB    0x00C0  /* 0xC0-0xCF Memory Scrubbing */
  49 #define MCACOD_SCRUBMSK 0xeff0  /* Skip bit 12 ('F' bit) */
  50 #define MCACOD_L3WB     0x017A  /* L3 Explicit Writeback */
  51 #define MCACOD_DATA     0x0134  /* Data Load */
  52 #define MCACOD_INSTR    0x0150  /* Instruction Fetch */
  53
  54 /* MCi_MISC register defines */
  55 #define MCI_MISC_ADDR_LSB(m)    ((m) & 0x3f)
  56 #define MCI_MISC_ADDR_MODE(m)   (((m) >> 6) & 7)
  57 #define  MCI_MISC_ADDR_SEGOFF   0       /* segment offset */
  58 #define  MCI_MISC_ADDR_LINEAR   1       /* linear address */
  59 #define  MCI_MISC_ADDR_PHYS     2       /* physical address */
  60 #define  MCI_MISC_ADDR_MEM      3       /* memory address */
  61 #define  MCI_MISC_ADDR_GENERIC  7       /* generic */
  62
  63 /* CTL2 register defines */
  64 #define MCI_CTL2_CMCI_EN                (1ULL << 30)
  65 #define MCI_CTL2_CMCI_THRESHOLD_MASK    0x7fffULL
  66
  67 #define MCJ_CTX_MASK            3
  68 #define MCJ_CTX(flags)          ((flags) & MCJ_CTX_MASK)
  69 #define MCJ_CTX_RANDOM          0    /* inject context: random */
  70 #define MCJ_CTX_PROCESS         0x1  /* inject context: process */
  71 #define MCJ_CTX_IRQ             0x2  /* inject context: IRQ */
  72 #define MCJ_NMI_BROADCAST       0x4  /* do NMI broadcasting */
  73 #define MCJ_EXCEPTION           0x8  /* raise as exception */
  74 #define MCJ_IRQ_BROADCAST       0x10 /* do IRQ broadcasting */
  75
  76 #define MCE_OVERFLOW 0          /* bit 0 in flags means overflow */
  77
  78 /* Software defined banks */
  79 #define MCE_EXTENDED_BANK       128
  80 #define MCE_THERMAL_BANK        (MCE_EXTENDED_BANK + 0)
  81 #define K8_MCE_THRESHOLD_BASE   (MCE_EXTENDED_BANK + 1)
  82
  83 #define MCE_LOG_LEN 32
  84 #define MCE_LOG_SIGNATURE       "MACHINECHECK"
  85
  86 /*
  87  * This structure contains all data related to the MCE log.  Also
  88  * carries a signature to make it easier to find from external
  89  * debugging tools.  Each entry is only valid when its finished flag
  90  * is set.
  91  */
  92 struct mce_log {
  93         char signature[12]; /* "MACHINECHECK" */
  94         unsigned len;       /* = MCE_LOG_LEN */
  95         unsigned next;
  96         unsigned flags;
  97         unsigned recordlen;     /* length of struct mce */
  98         struct mce entry[MCE_LOG_LEN];
  99 };
 100
 101 struct mca_config {
 102         bool dont_log_ce;
 103         bool cmci_disabled;
 104         bool ignore_ce;
 105         bool disabled;
 106         bool ser;
 107         bool bios_cmci_threshold;
 108         u8 banks;
 109         s8 bootlog;
 110         int tolerant;
 111         int monarch_timeout;
 112         int panic_timeout;
 113         u32 rip_msr;
 114 };
 115
 116 extern struct mca_config mca_cfg;
 117 extern void mce_register_decode_chain(struct notifier_block *nb);
 118 extern void mce_unregister_decode_chain(struct notifier_block *nb);
 119
 120 #include <linux/percpu.h>
 121 #include <linux/init.h>
 122 #include <linux/atomic.h>
 123
 124 extern int mce_p5_enabled;
 125
 126 #ifdef CONFIG_X86_MCE
 127 int mcheck_init(void);
 128 void mcheck_cpu_init(struct cpuinfo_x86 *c);
 129 #else
 130 static inline int mcheck_init(void) { return 0; }
 131 static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
 132 #endif
 133
 134 #ifdef CONFIG_X86_ANCIENT_MCE
 135 void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
 136 void winchip_mcheck_init(struct cpuinfo_x86 *c);
 137 static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
 138 #else
 139 static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
 140 static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
 141 static inline void enable_p5_mce(void) {}
 142 #endif
 143
 144 void mce_setup(struct mce *m);
 145 void mce_log(struct mce *m);
 146 DECLARE_PER_CPU(struct device *, mce_device);
 147
 148 /*
 149  * Maximum banks number.
 150  * This is the limit of the current register layout on
 151  * Intel CPUs.
 152  */
 153 #define MAX_NR_BANKS 32
 154
 155 #ifdef CONFIG_X86_MCE_INTEL
 156 void mce_intel_feature_init(struct cpuinfo_x86 *c);
 157 void cmci_clear(void);
 158 void cmci_reenable(void);
 159 void cmci_rediscover(void);
 160 void cmci_recheck(void);
 161 #else
 162 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
 163 static inline void cmci_clear(void) {}
 164 static inline void cmci_reenable(void) {}
 165 static inline void cmci_rediscover(void) {}
 166 static inline void cmci_recheck(void) {}
 167 #endif
 168
 169 #ifdef CONFIG_X86_MCE_AMD
 170 void mce_amd_feature_init(struct cpuinfo_x86 *c);
 171 #else
 172 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
 173 #endif
 174
 175 int mce_available(struct cpuinfo_x86 *c);
 176
 177 DECLARE_PER_CPU(unsigned, mce_exception_count);
 178 DECLARE_PER_CPU(unsigned, mce_poll_count);
 179
 180 extern atomic_t mce_entry;
 181
 182 typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
 183 DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
 184
 185 enum mcp_flags {
 186         MCP_TIMESTAMP = (1 << 0),       /* log time stamp */
 187         MCP_UC = (1 << 1),              /* log uncorrected errors */
 188         MCP_DONTLOG = (1 << 2),         /* only clear, don't log */
 189 };
 190 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
 191
 192 int mce_notify_irq(void);
 193 void mce_notify_process(void);
 194
 195 DECLARE_PER_CPU(struct mce, injectm);
 196
 197 extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
 198                                     const char __user *ubuf,
 199                                     size_t usize, loff_t *off));
 200
 201 /* Disable CMCI/polling for MCA bank claimed by firmware */
 202 extern void mce_disable_bank(int bank);
 203
 204 /*
 205  * Exception handler
 206  */
 207
 208 /* Call the installed machine check handler for this CPU setup. */
 209 extern void (*machine_check_vector)(struct pt_regs *, long error_code);
 210 void do_machine_check(struct pt_regs *, long);
 211
 212 /*
 213  * Threshold handler
 214  */
 215
 216 extern void (*mce_threshold_vector)(void);
 217 extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
 218
 219 /*
 220  * Thermal handler
 221  */
 222
 223 void intel_init_thermal(struct cpuinfo_x86 *c);
 224
 225 void mce_log_therm_throt_event(__u64 status);
 226
 227 /* Interrupt Handler for core thermal thresholds */
 228 extern int (*platform_thermal_notify)(__u64 msr_val);
 229
 230 /* Interrupt Handler for package thermal thresholds */
 231 extern int (*platform_thermal_package_notify)(__u64 msr_val);
 232
 233 /* Callback support of rate control, return true, if
 234  * callback has rate control */
 235 extern bool (*platform_thermal_package_rate_control)(void);
 236
 237 #ifdef CONFIG_X86_THERMAL_VECTOR
 238 extern void mcheck_intel_therm_init(void);
 239 #else
 240 static inline void mcheck_intel_therm_init(void) { }
 241 #endif
 242
 243 /*
 244  * Used by APEI to report memory error via /dev/mcelog
 245  */
 246
 247 struct cper_sec_mem_err;
 248 extern void apei_mce_report_mem_error(int corrected,
 249                                       struct cper_sec_mem_err *mem_err);
 250
 251 #endif /* _ASM_X86_MCE_H */